OPA684

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBOS219A MARCH 2002

Low-Power, Current Feedback

OPERATIONAL AMPLIFIER With Disable

FEATURES

MINIMAL BANDWIDTH CHANGE VERSUS GAIN

> 120MHz BANDWIDTH TO GAIN > +10

LOW DISTORTION: < 78dBc at 5MHz

HIGH OUTPUT CURRENT: 120mA

SINGLE +5V TO +12V SUPPLY OPERATION

DUAL

2.5 TO

6.0V SUPPLY OPERATION

LOW SUPPLY CURRENT: 1.7mA

LOW SHUTDOWN CURRENT: 100

V+

ERR

(S)

ERR

Low-Power

Amplifier

DESCRIPTION

The OPA684 provides a new level of performance in low-power,
wideband, current-feedback (CFB) amplifiers. This CFB

plus

ampli-

fier is the first to use an internally closed-loop input buffer stage that
enhances performance significantly over earlier low-power CFB
amplifiers. While retaining the benefits of very low power operation,
this new architecture provides many of the benefits of a more ideal
CFB amplifier. The closed-loop input stage buffer gives a very low
and linearized impedance path at the inverting input to sense the
feedback error current. This improved inverting input impedance
retains exceptional bandwidth to much higher gains and improves
harmonic distortion over earlier solutions limited by inverting input
linearity. Beyond simple high-gain applications, the OPA684 CFB

plus

amplifier permits the gain setting element to be set with consider-
able freedom from amplifier bandwidth interaction. This allows
frequency response peaking elements to be added, multiple input
inverting summing circuits to have greater bandwidth, and low-

OPA684

APPLICATIONS

LOW-POWER BROADCAST VIDEO DRIVERS

EQUALIZING FILTERS

SAW FILTER HIGH GAIN POST AMPLIFIERS

MULTICHANNEL SUMMING AMPLIFIERS

PROFESSIONAL CAMERAS

ADC INPUT DRIVERS

power line drivers to meet the demanding requirements of studio
cameras and broadcast video.

The output capability of the OPA684 also sets a new mark in
performance for low-power current feedback amplifiers. Delivering
a full

4Vp-p swing on

5V supplies, the OPA684 also has the

output current to support this swing into a 100

load. This minimal

output headroom requirement is complemented by a similar 1.2V
input stage headroom giving exceptional capability for single +5V
operation.

The OPA684's low 1.7mA supply current is precisely trimmed at
25

C. This trim, along with low shift over temperature and supply

voltage, gives a very robust design over a wide range of operating
conditions. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or holding
it HIGH, gives normal operation. If pulled LOW, the OPA684 supply
current drops to less than 100

A while the I/O pins go to a high

impedance state.

Normalized Gain

= 1k

G = 100

G = 50

G = 20

G = 10

G = 5

G = 2

100

200

BW (MHz) vs GAIN

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Patent Pending

OPA684

SBOS219A

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply ...............................................................................

6.5V

Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................................

Storage Temperature Range: ID, IDBV ......................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +175

NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

OPA684

SO-8

C to +85

OPA684D

OPA684ID

Rails, 100

OPA684IDR

Tape and Reel, 2500

OPA684

SOT23-6

DBV

C to +85

B84

OPA684IDBVT

Tape and Reel, 250

OPA684IDBVR

Tape and Reel, 3000

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

Output

Noninverting Input

DIS

Inverting Input

B84

Pin Orientation/Package Marking

Inverting Input

Noninverting Input

DIS

Output

NC = No Connection

PIN CONFIGURATION

OPA684 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

FEATURES

OPA684

OPA2684

OPA3684

Low-Power CFB

plus

OPA691

OPA2691

OPA3691

High Slew Rate CFB

OPA685

> 500MHz CFB

Top View

SOT23

NOTES: (1) For the most current specifications, and package information, refer to our web site at www.ti.com.

OPA684

SBOS219A

www.ti.com

AC PERFORMANCE (See Figure 1)
Small-Signal Bandwidth (V

= 0.5Vp-p)

G = +1, R

= 1k

210

MHz

typ

G = +2, R

= 1k

160

112

110

104

MHz

min

G = +5, R

= 1k

134

MHz

typ

G = +10, R

= 1k

120

MHz

typ

G = +20, R

= 1k

104

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

= 0.5Vp-p, R

= 1k

MHz

min

Peaking at a Gain of +1

= 1k

, V

= 0.5Vp-p

1.4

4.8

5.9

6.3

max

Large-Signal Bandwidth

G = +2, V

= 4Vp-p

MHz

typ

Slew Rate

G = 1, V

= 4V Step

820

675

650

575

min

G = +2,V

= 4V Step

750

650

620

590

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

typ

G = +2, V

= 4VStep

6.8

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

dBc

max

dBc

max

3rd-Harmonic

= 100

dBc

max

dBc

max

Input Voltage Noise

f > 1MHz

3.7

4.1

4.2

4.4

nV/

max

Non-inverting Input Current Noise

f > 1MHz

9.4

12.5

pA/

max

Inverting Input Current Noise

f > 1MHz

18.5

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.04

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.02

deg

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= 0V, R

= 1k

355

160

155

153

min

Input Offset Voltage

= 0V

1.5

3.5

4.1

4.3

max

Average Offset Voltage Drift

= 0V

max

Non-inverting Input Bias Current

= 0V

5.0

11.5

max

Average Non-inverting Input Bias Current Drift

= 0V

nA/

max

Inverting Input Bias Current

= 0V

5.0

17.5

18.5

max

Average Inverting Input Bias Current Drift

= 0V

max

INPUT
Common-Mode Input Range

(5)

(CMIR)

3.75

3.65

3.65

3.6

min

Common-Mode Rejection Ratio (CMRR)

= 0V

min

Non-inverting Input Impedance

50 || 2

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop, DC

2.5

typ

OUTPUT
Voltage Output Swing

Load

4.1

4.0

4.0

3.9

min

Current Output, Sourcing

= 0

160

140

135

130

min

Current Output, Sinking

= 0

120

110

105

100

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.006

typ

DISABLE (Disabled Low)
Power-Down Supply Current (+V

)

DIS

= 0

100

150

170

180

max

Disable Time

= +1V, G

= +2

typ

Enable Time

= +1V, G

= +2

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

1.7

typ

Enable Voltage

3.4

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0V

120

130

135

max

POWER SUPPLY
Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current

1.7

1.8

1.85

max

Min Quiescent Current

1.7

1.6

1.55

1.45

min

Power-Supply Rejection Ratio (PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: ID, IDBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV SOT-23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for 25

C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient

C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMR at

CMIR limits.

OPA684ID, IDBV

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

TYP

MIN/MAX OVER TEMPERATURE

ELECTRICAL CHARACTERISTICS: V

= 1k

, R

= 100

, and G = +2

(See Figure 1 for AC performance only), unless otherwise noted.

OPA684

SBOS219A

www.ti.com

AC PERFORMANCE (See Figure 3)
Small-Signal Bandwidth (V

= 0.5Vp-p)

G = +1, R

= 1.3k

146

MHz

typ

G = +2, R

= 1.3k

105

MHz

min

G = +5, R

= 1.3k

MHz

min

G = +10, R

= 1.3k

MHz

typ

G = +20, R

= 1.3k

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p, R

= 1.3k

MHz

min

Peaking at a Gain of +1

= 1.3k

, V

< 0.5Vp-p

0.5

2.6

3.4

3.7

max

Large-Signal Bandwidth

G = 2, V

= 2Vp-p

MHz

typ

Slew Rate

G = 2, V

= 2V Step

300

240

235

225

min

G = 2, V

= 0.5V Step

4.3

typ

Rise-and-Fall Time

G = 2, V

= 2VStep

5.3

typ

Harmonic Distortion

G = 2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

3rd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

Input Voltage Noise

f > 1MHz

3.7

4.1

4.2

4.4

nV/

max

Non-inverting Input Current Noise

f > 1MHz

9.4

12.5

pA/

max

Inverting Input Current Noise

f > 1MHz

18.5

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.04

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.07

deg

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= V

/2, R

= 100

to V

325

160

155

153

min

Input Offset Voltage

= V

1.0

3.0

3.6

3.8

max

Average Offset Voltage Drift

= V

max

Non-inverting Input Bias Current

= V

11.5

max

Average Non-inverting Input Bias Current Drift

= V

nA/

max

Inverting Input Bias Current

= V

13.5

max

Average Inverting Input Bias Current Drift

= V

max

INPUT
Least Positive Input Voltage

(5)

1.25

1.32

1.35

1.38

max

Most Positive Input Voltage

(5)

3.75

3.68

3.65

3.62

min

Common-Mode Refection Ratio (CMRR)

= V

min

Non-inverting Input Impedance

50 || 1

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop

2.5

typ

OUTPUT
Most Positive Output Voltage

= 1k

to V

4.10

4.0

4.0

3.9

min

Least Positive Output Voltage

= 1k

to V

0.9

1.0

1.0

1.1

max

Current Output, Sourcing

= V

min

Current Output, Sinking

= V

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

typ

DISABLE (Disabled LOW)
Power-Down Supply Current (+V

)

DIS

= 0

typ

Off Isolation

F = 5.0MHz

typ

Output Capacitance in Disable

1.7

typ

Turn On Glitch

G = +2, R

= 150

, V

= V

typ

Turn Off Glitch

G = +2, R

= 150

, V

= V

typ

Enable Voltage

3.4

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0V

120

130

135

max

POWER SUPPLY
Specified Single-Supply Operating Voltage

typ

Max Single-Supply Operating Voltage Range

max

Max Quiescent Current

= +5V

1.44

1.55

1.55

max

Min Quiescent Current

= +5V

1.44

1.30

1.20

1.15

min

Power-Supply Rejection Ratio (+PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: ID, IDBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV SOT23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for 25

C tested specifications. (2) Junction temperature = ambient at low temperature limit, junction temperature = ambient

C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMR at

CMIR limits.

ELECTRICAL CHARACTERISTICS: V

= +5V

= 1.3k

, R

= 100

, and G = +2

(See Figure 3 for AC performance only), unless otherwise noted.

OPA684ID, IDBV

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

TYP

MIN/MAX OVER TEMPERATURE

OPA684

SBOS219A

www.ti.com

Frequency (MHz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

= 0.5Vp-p

= 1k

G = 100

See Figure 1

G = 50

G = 1

G = 2

G = 5

G = 10

Frequency (MHz)

200

100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

= 0.5Vp-p

= 1k

See Figure 2

G = 10

G = 20

G = 1

G = 5

G = 2

Frequency (MHz)

200

100

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

G = +2

= 100

See Figure 1

= 1Vp-p

= 0.5Vp-p

5Vp-p

2Vp-p

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

Gain (dB)

G = 1

= 100

= 0.5Vp-p

See Figure 2

1Vp-p

2Vp-p

5Vp-p

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (400mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 1

G = +2

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (400mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 2

G = 1

TYPICAL CHARACTERISTICS: V

At T

= +25

C, G = +2, R

= 1k

, R

= 100

, unless otherwise noted.

OPA684

SBOS219A

www.ti.com

HARMONIC DISTORTION vs LOAD RESISTANCE

100

Load Resistance (

)

Harmonic Distortion (dBc)

= 2Vp-p

f = 5MHz

G = +2

See Figure 1

2nd-Harmonic

3rd-Harmonic

Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

= 2Vp-p

= 100

See Figure 1

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

0.5

Output Voltage (Vp-p)

Harmonic Distortion (dBc)

f = 5MHz

= 100

2nd-Harmonic

3rd-Harmonic

See Figure 1

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

2.5

3.5

4.5

5.5

Supply Voltage (

Harmonic Distortion (dBc)

= 2Vp-p

= 100

2nd-Harmonic

3rd-Harmonic

See Figure 1

HARMONIC DISTORTION vs NONINVERTING GAIN

Gain (V/V)

Harmonic Distortion (dBc)

See Figure 1

= 2Vp-p

f = 5MHz

= 100

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs INVERTING GAIN

Inverting Gain (V/V)

Harmonic Distortion (dBc)

3rd-Harmonic

2nd-Harmonic

= 2Vp-p

f = 5MHz

= 100

See Figure 2

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 1k

, R

= 100

, unless otherwise noted.

OPA684

SBOS219A

www.ti.com

100

Frequency (Hz)

100

10M

10k

100k

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Voltage Noise (nV/

Hz)

Current Noise (pA/

Hz)

Noninverting Current Noise

9.4pA/

Voltage Noise

3.7nV/

Inverting Current Noise

17pA/

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

8 7 6 5 4 3 2 1

Power at Load (each tone, dBm)

3rd-Order Spurious Level (dBc)

+5V

OPA684

20MHz

10MHz

5MHz

1MHz

Time (ms)

DISABLE TIME

DIS

OUT

and V

DIS

(V)

See Figure 1

100

Frequency (MHz)

0.1

100

DISABLED FEEDTHRU

Feedthru (dB)

G = +2

DIS

= 0

See Figure 1

LOAD

(pF)

100

vs C

LOAD

(

)

0.5dB Peaking

Frequency (MHz)

200

100

SMALL-SIGNAL BANDWIDTH vs C

LOAD

Normalized Gain (dB)

10pF

100pF

47pF

22pF

+5V

250

1.1k

OPA684

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 1k

, R

= 100

, unless otherwise noted.

OPA684

SBOS219A

www.ti.com

CMRR and PSRR vs FREQUENCY

Frequency (Hz)

Common-Mode Rejection Ratio (dB)

CMRR

+PSRR

PSRR

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

Gain = +2

NTSC, Positive Video

OUTPUT CURRENT AND VOLTAGE LIMITATIONS

150

100

150

(MA)

(V)

1W Power

Limit

= 100

= 50

= 500

1W Power

Limit

TYPICAL DC DRIFT OVER TEMPERATURE

100

125

Ambient Temperature (

Input Bias Currents (

and Of

fset V

oltage (mV)

Input Offset Voltage

Noninverting Input Bias Current

Inverting Input Bias Current

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

200

175

150

125

100

Supply Current (mA)

1.5

1.9

1.8

1.7

1.6

Sourcing Output Current

Sinking Output Current

Supply Current

Right Scale

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 1k

, R

= 100

, unless otherwise noted.

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

Frequency (Hz)

Open-Loop

ransimpedance Gain (dB

) 120

100

Open-Loop Phase (

)

120

150

180

20log (Z

)

OPA684

SBOS219A

www.ti.com

SETTLING TIME

Time (ns)

% Error to Final V

alue

0.05

0.04

0.03

0.02

0.01

0.02

0.03

0.04

0.05

2V Step

See Figure 1

DISABLED SUPPLY CURRENT vs TEMPERATURE

100

125

Ambient Temperature (

Disabled Supply Current (

120

110

100

Current

INVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Input V

oltage (1.6V/div)

Output V

oltage (1.6V/div)

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

See Figure 2

Input Voltage

Left Scale

Output Voltage

Right Scale

INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE

Supply Voltage

Input and Output V

oltage Range

Input

Voltage

Range

Output

Voltage

Range

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Frequency (Hz)

100k

10k

100

10M

100M

Output Impedance (

)

100

0.01

0.001

OPA684

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 1k

, R

= 100

, unless otherwise noted.

NONINVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Input V

oltage (0.8V/div)

Output V

oltage (1.6V/div)

4.0

3.2

2.4

1.6

0.8

1.6

2.4

3.2

4.0

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

See Figure 1

Input Voltage

Left Scale

Output Voltage

Right Scale

OPA684

SBOS219A

www.ti.com

Frequency (MHz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

G = 100

See Figure 3

G = 50

= 1.3k

G = 1

G = 2

G = 10

G = 5

Frequency (MHz)

200

100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

See Figure 4

= 1.3k

G = 1

G = 10
G = 20

G = 5

G = 2

Frequency (MHz)

200

100

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

0.5Vp-p

1Vp-p

0.2Vp-p

2Vp-p

See Figure 3.

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

Gain (dB)

= 0.5Vp-p

See Figure 4

= 1Vp-p

= 2Vp-p

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 3.

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 4

TYPICAL CHARACTERISTICS: V

= +5V

At T

= +25

C, V

= 5V, G = +2, R

= 1.3k

, R

= 100

, unless otherwise noted.

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Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

= 2Vp-p

= 100

See Figure 3

2nd-Harmonic

3rd-Harmonic

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

15 14 13 12 11 10

Power at Load (each tone, dBm)

3rd-Order Spurious Level (dBc)

See Figure 3

10MHz

20MHz

5MHz

1MHz

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

100

Supply Current (mA)

1.5

1.4

1.3

1.2

1.1

1.0

Supply Current

Right Scale

Sourcing Output Current

Left Scale

Sinking Output Current

Left Scale

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

G = +2

NTSC, Positive Video

TYPICAL CHARACTERISTICS: V

= +5V

(Cont.)

At T

= +25

C, V

= 5V, G = +2, R

= 1.3k

, R

= 100

, unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

100

Load Resistance (

)

Harmonic Distortion (dBc)

= 2Vp-p

f = 5MHz

See Figure 3

3rd-Harmonic

2nd-Harmonic

Output Voltage (Vp-p)

0.5

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Harmonic Distortion (dBc)

G = +2

= 100

f = 5MHz

3rd-Harmonic

2nd-Harmonic

See Figure 3

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APPLICATIONS INFORMATION

LOW-POWER, CURRENT-FEEDBACK OPERATION

The OPA684 gives a new level of performance in low-power,
current-feedback op amps. Using a new input stage buffer
architecture, the OPA684 CFB

plus

amplifier holds nearly

constant AC performance over a wide gain range. This
closed-loop internal buffer gives a very low and linearized
impedance at the inverting node, isolating the amplifier's AC
performance from gain element variations. This allows both
the bandwidth and distortion to remain nearly constant over
gain, moving closer to the ideal current feedback perfor-
mance of gain bandwidth independence. This low power
amplifier also delivers exceptional output power--it's

swing on

5V supplies with >100mA output drive gives

excellent performance into standard video loads or doubly-
terminated 50

cables. Single +5V supply operation is also

supported with similar bandwidths but with reduced output
power capability. For lower quiescent power in a CFB

plus

amplifier, consider the OPA683, while for higher output
power, consider the OPA691.

Figure 1 shows the DC coupled, gain of +2, dual power-
supply circuit used as the basis of the

5V Electrical and

Typical Characteristics. For test purposes, the input imped-
ance is set to 50

with a resistor to ground, and the output

impedance is set to 50

with a series output resistor. Voltage

swings reported in the characteristics are taken directly at the
input and output pins while load powers (dBm) are defined at
a matched 50

load. For the circuit of Figure 1, the total

effective load will be 100

|| 2000

= 95

. Gain changes are

most easily accomplished by simply resetting the R

value,

holding R

constant at its recommended value of 1k

. The

disable control line (DIS) is typically left open to give normal
amplifier operation. It may, however, be asserted LOW to
reduce the amplifier supply current to 100

A typically.

Figure 2 shows the DC coupled, gain of 1V/V, dual power-
supply circuit used as the basis of the Inverting Typical
Characteristics. Inverting operation offers several perfor-
mance benefits. Since there is no common-mode signal
across the input stage, the slew rate for inverting operation
is higher and the distortion performance is slightly improved.
An additional input resistor, R

, is included in Figure 2 to set

the input impedance equal to 50

. The parallel combination

of R

and R

set the input impedance. As the desired gain

increases for the inverting configuration, R

is adjusted to

achieve the desired gain, while R

is also adjusted to hold a

input match. A point will be reached where R

will equal

, R

is removed, and the input match is set by R

only.

With R

fixed to achieve an input match to 50

, increasing

will increase the gain. This will, however, quickly reduce

the achievable bandwidth as the feedback resistor increases
from its recommended value of 1k

. If the source does not

require an input match of 50

, either adjust R

to the get the

desired load, or remove it and let the R

resistor alone

provide the input load.

These circuits show

5V operation. The same circuits can be

applied with bipolar supplies from

2.5V to

6V. Internal

supply independent biasing gives nearly the same perfor-
mance for the OPA684 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nomi-
nally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA684 is reduced.

OPA684

+5V

DIS

Source

Load

0.1

6.8

0.1

6.8

FIGURE 1. DC Coupled, G = +2V/V, Bipolar Supply Speci-

fications and Test Circuit.

FIGURE 2. DC Coupled, G = 1V/V, Bipolar Supply, Speci-

fication and Test Circuit.

OPA684

+5V

DIS

52.3

Load

Source

0.1

6.8

0.1

6.8

Figure 3 shows the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis only for the +5V
Electrical and Typical Characteristics. The key requirement
of broadband single-supply operation is to maintain input and
output signal swings within the usable voltage ranges at both
the input and the output. The circuit of Figure 3 establishes
an input midpoint bias using a simple resistive divider from
the +5V supply (two 10k

resistors) to the non-inverting

input. The input signal is then AC coupled into this midpoint

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voltage bias. The input voltage can swing to within 1.25V of
either supply pin, giving a 2.5Vp-p input signal range cen-
tered between the supply pins. The input impedance of
Figure 3 is set to give a 50

input match. If the source does

not require a 50

match, remove R

and drive directly into

the blocking capacitor. The source will then see the 5k

load

of the biasing network. The gain resistor (R

) is AC coupled,

giving the circuit a DC gain of +1, which puts the non-
inverting input DC bias voltage (2.5V) on the output as well.
The feedback resistor value has been adjusted from the
bipolar supply condition to re-optimize for a flat frequency
response in +5V only, gain of +2, operation. On a single +5V
supply, the output voltage can swing to within 1.0V of either
supply pin while delivering more than 70mA output current
giving 3V output swing into 100

(8dBm maximum at a

matched 50

load). The circuit of Figure 3 shows a blocking

capacitor driving into a 50

output resistor then into a 50

load. Alternatively, the blocking capacitor could be removed
if the load is tied to a supply midpoint or to ground if the DC
current required by the load is acceptable.

The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA684.

LOW-POWER VIDEO LINE DRIVER APPLICATIONS

For low-power, video line driving, the OPA684 provides the
output current and linearity to support multiple load compos-
ite video signals. Figure 5 shows a typical

5V supply video

line driver application. The improved 2nd-harmonic distortion
of the CFB

plus

architecture, along with the OPA684's high

output current and voltage, gives exceptional differential gain
and phase performance for a low-power solution. As the
Typical Characteristics show, a single video load shows a
dG/dP of 0.04%/0.02

. Multiple loads may also be driven with

< 0.1%/0.1

dG/dP for up to 4 parallel video loads, where the

amplifier is driving an equivalent load of 37.5

1.3k

OPA684

+5V

DIS

Load

Source

0.1

6.8

10k

1.3k

0.1

FIGURE 3. Non-inverting Single-Supply Test and Character-

ization Circuit.

Figure 4 shows the AC coupled, single +5V supply, gain of
1V/V circuit configuration used as a basis for the +5V
Typical Characteristics. In this case, the midpoint DC bias on
the non-inverting input is also decoupled with an additional
0.1

F decoupling capacitor. This reduces the source imped-

ance at higher frequencies for the non-inverting input bias
current noise. This 2.5V bias on the non-inverting input pin
appears on the inverting input pin and, since R

is DC

blocked by the input capacitor, will also appear at the output
pin. One advantage to inverting operation is that since there
is no signal swing across the input stage, higher slew rates
and operation to even lower supply voltages is possible. To
retain a 1Vp-p output capability, operation down to a 3V
supply is allowed. At a +3V supply, the input stage is
saturated, but for the inverting configuration of a current
feedback amplifier, wideband operation is retained even
under this condition.

FIGURE 4. Inverting Single-Supply Test and Characteriza-

tion Circuit.

1.3k

OPA684

+5V

DIS

Load

Source

0.1

6.8

1.3k

10k

0.1

52.3

OPA684

+5V

DIS

Load

Supply Decoupling not shown.

Coax

VIDEO

FIGURE 5. Gain of +2 Video Cable Driver.

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INVERTING SUMMING APPLICATIONS

The OPA684 provides one of the most robust summing
operations available in a wideband op amp. Figure 6 shows
a typical inverting summing application where, in this case, 4
sources are summed through 500

gain resistors while also

including an 88.9

terminating impedance to present a 75

input impedance to each source. The gain for each channel
is 2 to the output pin and 1 to the matched load. The
extremely low inverting input impedance of the CFB

plus

architectures ensures noninteractive summing for all of the
channels. The amplifier bandwidth is largely independent of
variations in the gain setting elements, depending primarily
on the feedback resistor value instead. This type of circuit
may be used to sum numerous signals together or, where the
prior stages can be disabled, allow multiple channels to be
brought together with only the active channel passing on to
the output.

500

OPA684

+5V

DIS

500

88.9

Load

Supply Decoupling not shown.

2(IN

+ IN

)

FIGURE 7. Single-Supply, High-Gain SAW Post-Amplifier.

SAW FILTER POST- AMPLIFIER

While SAW filters provide unmatched selectivity in a passive
filter element, this comes at the cost of significant insertion loss
for the desired signal. The OPA684 can provide a low-cost and
low-power post-amplifier over a wide range of gains due to the
CFB

plus

internal architecture. Figure 7 shows a 44MHz SAW

filter with 20dB insertion loss followed by an OPA684 operating
at a gain of 20V/V (26dB) providing a net gain of 1 (0dB) from
the input of the SAW filter to a matched 50

load. The circuit

shown also includes a simple bandpass around 44MHz to
reduce out-of-band noise. The gain for the circuit of Figure 7
ranges from 0dB at DC to 28dB at 44MHz and then back to
< 0dB above 200MHz. The LC elements in the gain circuit peak
the response slightly above a gain of 26dB--removing those
would give a broadband gain of 26dB.

950

OPA684

DIS

Load

20k

1000pF

100pF

1000pF

160nH

SAW
Filter

44MHz

20dB

Insertion

Loss

+5V to +12V

= 0dB at 44MHz

FIGURE 6. Gain of 2 Video Summing Amplifier.

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Figure 8 shows the small-signal frequency response for the
amplifier portion of this circuit, from the non-inverting input to
the output pin. This particular example is configured as a
single-supply circuit that will operate over a supply range from
+5V to +12V. Where higher frequencies or 3rd-order intercepts
are required, consider the OPA685, a very high bandwidth
(> 500MHz) current-feedback op amp.

input to be used for the CM (Common-Mode) voltage from
the ADS825 converter. This midpoint reference biases both
the non-inverting converter input and the amplifier non-
inverting input. With an AC-coupled gain path, this +2.5V has
a gain of +1 to the output, putting the output at the DC
midpoint for the converter. The output then drives through an
isolating resistor (50

) to the inverting input of the converter,

which is further de-coupled by a 10pF external capacitance
to add to its 5pF input capacitance. This coupling network
provides a high frequency cutoff, while also giving a low
source impedance at high frequencies for the converter. The
gain for this circuit is set by adjusting R

to the desired value.

For a 2Vp-p maximum output driving the light load of Figure
9, the OPA684 will provide > 75dB SFDR through 5MHz (see
the Typical Characteristics).

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA684 in its two package
styles. Both of these are available, free, as an unpopulated
PC board delivered with descriptive documentation. The
summary information for these boards is shown in Table I.

Frequency (MHz)

100

BANDPASS SAW FILTER POST AMPLIFIER

Gain (dB)

44MHz

LOW POWER, ADC DRIVER

Where a low-power, single-supply, interface to a single-
ended input +5V ADC is required, the circuit of Figure 9 can
provide a very flexible, higher performance solution. Running
in an AC-coupled inverting mode allows the non-inverting

FIGURE 8. Bandpass SAW Filter Post-Amplifier.

FIGURE 9. Low-Power, Single-Supply, ADC Driver.

OPA684

+5V

DIS

1.3k

10pF

1.3k

0.1

ADS825

10-Bit

40MSPS

2.5V

+2.5V

2Vp-p

Max

BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA684ID

SO-8

DEM-OPA68xU

SBOU009

OPA684IDBQ

SOT23-6

DEM-OPA6xxN

SBOU010

TABLE I.

OPA684

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the open-loop voltage gain curve for a voltage-feedback
op amp. Developing the transfer function for the circuit of
Figure 10 gives Equation 1:

(1)

R NG

( )

This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(s) were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation.

(2)

R NG

Loop Gain

( )

If 20 · log(R

+ NG · R

) were drawn on top of the open-loop

transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(s) rolls
off to equal the denominator of Equation 2, at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier's closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feed-
back op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled sepa-
rately from the desired signal gain (or NG).

The OPA684 is internally compensated to give a maximally
flat frequency response for R

= 1k

at NG = 2 on

supplies. That optimum value goes to 1.3k

on a single +5V

supply. Normally, with a current-feedback amplifier, it is
possible to adjust the feedback resistor to hold this band-
width up as the gain is increased. The CFB

plus

architecture

has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Character-
istics show the small-signal bandwidth over gain with a fixed
feedback resistor.

At very high gains, 2nd-order effects in the inverting output
impedance cause the overall response to peak up. If desired,
it is possible to retain a flat frequency response at higher
gains by adjusting the feedback resistor to higher values as
the gain is increased. See Figure 11 for the empirically
determined feedback resistor and resulting 3dB bandwidth
from gains of +2 to +100 to hold a < 0.5dB peaked response.
See Figure 12 for the measured frequency response curves
with the adjusted feedback resistor value. While the band-
width for this low-power part does reduce at higher gains,

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH

Any current-feedback op amp like the OPA684 can hold high
bandwidth over signal-gain settings with the proper adjust-
ment of the external resistor values. A low-power part like the
OPA684 typically shows a larger change in bandwidth due to
the significant contribution of the inverting input impedance
to loop-gain changes as the signal gain is changed. Figure
10 shows a simplified analysis circuit for any current-feed-
back amplifier.

(S)

ERR

FIGURE 10. Current Feedback Transfer Function Analysis

Circuit.

The key elements of this current-feedback op amp model
are:

Buffer gain from the non-inverting input to the inverting input.

Buffer output impedance.

ERR

Feedback error current signal.

Z(s)

Frequency dependent open loop transimpedance gain from i

ERR

to V

The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configura-
tion. For the buffer gain

< 1.0, the CMRR = 20 · log(1

The closed-loop input stage buffer used in the OPA684 gives
a buffer gain more closely approaching 1.00 and this shows up
in a slightly higher CMRR than any previous current feedback
op amp.

, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA684 reduces this ele-
ment to approximately 2.5

, using the loop gain of the local

input buffer stage. This significant reduction in output imped-
ance, on very low power, contributes significantly to extend-
ing the bandwidth at higher gains.

A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error volt-
age for a voltage-feedback op amp) and passes this on to the
output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to

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going over a 50:1 gain range gives only a factor of 3.5
bandwidth reduction. The 50MHz bandwidth at a gain of
100V/V is equivalent to a 5GHz gain-bandwidth product
voltage-feedback amplifier capability.

OUTPUT CURRENT AND VOLTAGE

The OPA684 provides output voltage and current capabilities
that can support the needs of driving doubly-terminated 50

lines. For a 100

load at the gain of +2, (see Figure 1), the total

load is the parallel combination of the 100

load and the 2k

total feedback network impedance. This 95

load will require

no more than 40mA output current to support the

3.8V

minimum output voltage swing for 100

loads. This is well

under the specified minimum +130/100mA specifications
over the full temperature range.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" curve in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more

detailed view of the OPA684's output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.

The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, de-
creasing their V

s (increasing the available output voltage

swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.

To maintain maximum output stage linearity, no output short-
circuit protection is provided. Normally, this will not be a
problem since most applications include a series-matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in most
cases, destroy the amplifier. If additional short-circuit protec-
tion is required, consider a small-series resistor in the power-
supply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5

series resistor in each

power-supply lead will limit the internal power dissipation to
less than 1W for an output short-circuit, while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1

F power-supply

decoupling capacitors after these supply current limiting
resistors directly on the supply pins.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an Analog-to-Digital Converter
(ADC), including additional external capacitance which may
be recommended to improve ADC linearity. A high-speed,
high open-loop gain, amplifier like the OPA684 can be very
susceptible to decreased stability and closed-loop response
peaking when a capacitive load is placed directly on the
output pin. When the amplifier's open-loop output resistance
is considered, this capacitive load introduces an additional
pole in the signal path that can decrease the phase margin.
Several external solutions to this problem have been sug-
gested. When the primary considerations are frequency
response flatness, pulse response fidelity, and/or distortion,
the simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the ca-
pacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.

2000

1750

1500

1250

1000

750

500

Voltage Gain (V/V)

100

BANDWIDTH AND R

OPTIMIZED vs GAIN

Feedback Resistor (

)

200

150

100

Bandwidth (MHz)

Bandwidth

Right Scale

Left Scale

1.2

Frequency (MHz)

100

200

SMALL SIGNAL RESPONSE WITH OPTIMIZED R

Normalized Gain (dB)

G = 100

G = 50

G = 5

G = 2

G = 10

G = 20

FIGURE 11. Bandwidth and R

Optimized vs Gain.

FIGURE 12. Small-Signal Frequency Response with Opti-

mized R

OPA684

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The Typical Characteristics show the recommended "R

LOAD

" and the resulting frequency response at the load. To

reduce the required value of R

, those curves show a slight

increase in the feedback resistor value and an added load of
250

to ground. The 1k

resistor shown in parallel with the

load capacitor is a measurement path and may be omitted.
Parasitic capacitive loads greater than 5pF can begin to
degrade the performance of the OPA684. Long PC board
traces, unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA684 output pin
(see Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA684 provides very low distortion in a low-power part.
The CFB

plus

architecture also gives two significant areas of

distortion improvement. First, in operating regions where the
2nd-harmonic distortion due to output stage nonlinearities is
very low (frequencies < 1MHz, low output swings into light
loads), the linearization at the inverting node provided by the
CFB

plus

design gives 2nd-harmonic distortions that extend

into the 90dBc region. Previous current-feedback amplifiers
have been limited to approximately 85dBc due to the
nonlinearities at the inverting input. The 2nd-area of distor-
tion improvement comes in a distortion performance that is
largely gain independent. To the extent that the distortion at
a particular output power is output stage dependent, 3rd-
harmonics particularly, and to a lesser extent 2nd-harmonic
distortion, are constant as the gain is increased. This is due
to the constant loop gain versus signal gain provided by the
CFB

plus

design. As shown in the Typical Characteristics,

while the 3rd-harmonic is constant with gain, the 2nd-har-
monic degrades at higher gains. This is largely due to board
parasitic issues. Slightly imbalanced load return currents will
couple into the gain resistor to cause a portion of the 2nd-
harmonic distortion. At high gains, this imbalance has more
gain to the output giving increased 2nd-harmonic distortion.

Relative to alternative amplifiers with < 2mA supply current,
the OPA684 holds much lower distortion at higher frequen-
cies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2

harmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network--in the non-inverting configuration (see Figure 1)
this is the sum of R

+ R

, while in the inverting configuration

it is just R

. Also, providing an additional supply decoupling

capacitor (0.1

F) between the supply pins (for bipolar opera-

tion) improves the 2nd-order distortion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. A low-power part like
the OPA684 includes quiescent boost circuits to provide the
full-power bandwidth shown in the Typical Characteristics.
These act to increase the bias in a very linear fashion only
when high slew rate or output power are required. This also
acts to actually reduce the distortion slightly at higher output

power levels. The Typical Characteristics show the 2nd-
harmonic holding constant from 500mVp-p to 5Vp-p outputs,
while the 3rd harmonics actually decrease with increasing
output power.

The OPA684 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequen-
cies. This also gives low 2-tone 3rd-order intermodulation
distortion, as shown in the Typical Characteristics. Since the
OPA684 includes internal power boost circuits to retain good
full-power performance at high frequencies and outputs, it
does not show a classical 2-tone, 3rd-order intermodulation
intercept characteristic. Instead, it holds relatively low and
constant 3rd-order intermodulation spurious levels over power.
The Typical Characteristics show this spurious level as a dBc
below the carrier at fixed center frequencies swept over
single-tone power at a matched 50

load. These spurious

levels drop significantly (> 12dB) for lighter loads than the
100

used in the 2-tone 3rd-order intermodulation plot.

Converter inputs for instance will see < 82dBc 3rd-order
spurious to 10MHz for full-scale inputs. For even lower 3rd-
order intermodulation distortion to much higher frequencies,
consider the OPA685.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA684 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a low
power amplifier. The inverting current noise (17pA/

Hz) is

lower than most other current-feedback op amps, while the
input voltage noise (3.7nV/

Hz) is lower than any unity-gain

stable, comparable slew rate, voltage-feedback op amp. This
low input voltage noise was achieved at the price of higher
non-inverting input current noise (9.4pA/

Hz). As long as the

AC source impedance looking out of the non-inverting node
is less than 200

, this current noise will not contribute

significantly to the total output noise. The op amp input
voltage noise and the two input current noise terms combine
to give low output noise under a wide variety of operating
conditions. Figure 13 shows the op amp noise analysis
model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/

Hz or pA/

Hz.

4kT

OPA684

4kT = 1.6E 20J

at 290

4kTR

FIGURE 13. Op Amp Noise Analysis Model.

OPA684

SBOS219A

www.ti.com

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 13.

(3)

kTR

I R

kTR G

BN S

BI F

(

)

(

)

Dividing this expression by the noise gain (G

= (1 + R

))

will give the equivalent input referred spot noise voltage at
the non-inverting input, as shown in Equation 4.

(4)

kTR

I R

kTR

BN S

BI F

(

)

Evaluating these two equations for the OPA684 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 13.3nV/

Hz and a total equivalent input spot

noise voltage of 6.7nV/

Hz. This total input referred spot

noise voltage is higher than the 3.7nV/

Hz specification for

the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation
3 will approach just the 3.7nV/

Hz of the op amp itself. For

example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 52.3

, will give a total input

referred noise of 3.9nV/

Hz . A more complete description of

op amp noise analysis can be found in the TI application note
AB-103, "Noise Analysis for High Speed Op Amps"
(SBOA066), located at www.ti.com.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA684 provides excep-
tional bandwidth in high gains, giving fast pulse settling but
only moderate DC accuracy. The Electrical Characteristics
show an input offset voltage comparable to high slew rate
voltage-feedback amplifiers. The two input bias currents,
however, are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally re-
duce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst case +25

C input offset voltage and the

two input bias currents, gives a worst case output offset
range equal to:

· V

) + (I

· R

/2 · G

)

· R

)

(2 · 3.5mV)

(10

A · 25

· 2)

(1k

· 16

7mV + 0.5mV

16mV

23.5mV

where G

= non-inverting signal gain

While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a high-
speed amplifier, consider the OPA642 single and OPA2822
dual voltage-feedback amplifiers.

DISABLE OPERATION

The OPA684 provides an optional disable feature that may
be used to reduce system power when amplifier operation is
not required. If the V

DIS

control pin is left unconnected, the

OPA684 will operate normally. To disable, the V

DIS

control

pin must be asserted LOW. Figure 14 shows a simplified
internal circuit for the disable control feature.

In normal operation, base current to Q1 is provided through
the 250k

resistor, while the emitter current through the

40k

resistor sets up a voltage drop that is inadequate to

turn on the two diodes in Q1's emitter. As V

DIS

is pulled LOW,

additional current is pulled through the 40k

resistor eventu-

ally turning on these two diodes. At this point, any further
current pulled out of V

DIS

goes through those diodes holding

the emitter-base voltage of Q1 at approximately 0V. This
shuts off the collector current out of Q1, turning the amplifier
off. The supply current in the disable mode is only what is
required to operate the circuit of Figure 14.

25k

250k

40k

Control

DIS

When disabled, the output and input nodes go to a high
impedance state. If the OPA684 is operating at a gain of +1
(with a 1k

feedback resistor still required for stability), it will

show a very high impedance (1.7pF || 1M

) at the output and

exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (R

+ R

) will

appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (R

+ R

) giving relatively poor input to output

isolation.

FIGURE 14. Simplified Disable Control Circuit.

OPA684

SBOS219A

www.ti.com

The OPA684 provides very high power gain on low quiescent
current levels. When disabled, internal high impedance nodes
discharge slowly that, with the exceptional power gain pro-
vided, give a self-powering characteristic that leads to a slow
turn-off characteristic. Typical turn-off times to rated 100

disabled supply current are 4ms. Turn on times are very
fast--less than 40ns.

THERMAL ANALYSIS

The OPA684 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 175

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition P

= V

/(4 · R

where R

includes feedback network loading.

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As an absolute worst-case example, compute the maximum
T

using an OPA684IDBV (SOT23-6 package) in the circuit

of Figure 1 operating at the maximum specified ambient
temperature of +85

C and driving a grounded 100

load.

= 10V · 1.85mA + 5

/(4 · (100

|| 2k

)) = 84mW

Maximum T

= +85

C + (0.084W · 150

C/W) = 98

This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power
was assumed in this calculation.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-
plifier like the OPA684 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:

Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the non-inverting input, it can react with the source
impedance to cause unintentional bandlimiting. To re-
duce unwanted capacitance, a window around the sig-
nal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.

Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1

F decoupling capacitors. At

the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capaci-
tors. The power-supply connections should always be
decoupled with these capacitors. An optional supply de-
coupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion
performance. Larger (2.2

F to 6.8

F) decoupling ca-

pacitors, effective at lower frequencies, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC
board.

Careful selection and placement of external compo-
nents will preserve the high-frequency performance
of the OPA684. Resistors should be a very low reac-
tance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composi-
tion axially-leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PC-
board trace length as short as possible. Never use
wirewound type resistors in a high-frequency applica-
tion. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as close
as possible to the output pin. Other network compo-
nents, such as non-inverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place the
feedback resistor directly under the package on the
other side of the board between the output and inverting
input pins. The frequency response is primarily deter-
mined by the feedback resistor value, as described
previously. Increasing its value will reduce the peaking
at higher gains, while decreasing it will give a more
peaked frequency response at lower gains. The 1k

feedback resistor used in the electrical characteristics at
a gain of +2 on

5V supplies is a good starting point for

design. Note that a 1k

feedback resistor, rather than a

direct short, is required for the unity-gain follower appli-
cation. A current-feedback op amp requires a feedback
resistor even in the unity gain follower configuration to
control stability.

Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, con-
sider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set R

from the plot of recom-

mended "R

vs C

LOAD

". Low parasitic capacitive loads

(< 5pF) may not need an R

since the OPA684 is

OPA684

SBOS219A

www.ti.com

nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is ac-
ceptable, implement a matched impedance transmis-
sion line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50

environment is normally not

necessary onboard, and in fact a higher impedance
environment will improve distortion, as shown in the
distortion versus load plots. With a characteristic board
trace impedance defined based on board material and
trace dimensions, a matching series resistor into the
trace from the output of the OPA684 is used, as well as
a terminating shunt resistor at the input of the destina-
tion device. Remember also that the terminating imped-
ance will be the parallel combination of the shunt resistor
and the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA684 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as
shown in the plot of "R

vs C

LOAD

". This will not preserve

signal integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating imped-
ance.

Socketing a high-speed part like the OPA684 is not
recommended. The additional lead length and pin-to-
pin capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable fre-
quency response. Best results are obtained by soldering
the OPA684 onto the board.

External

Internal
Circuitry

FIGURE 15. Internal ESD Protection.

INPUT AND ESD PROTECTION

The OPA684 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table where an absolute maximum 13V across the
supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies, as
shown in Figure 15.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g. in systems with

15V supply parts

driving into the OPA684), current limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.

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