OPA687
Wideband, Ultra-Low Noise,
Voltage Feedback OPERATIONAL AMPLIFIER
With Power Down
FEATURES
q
HIGH GAIN BANDWIDTH: 3.8GHz
q
LOW INPUT VOLTAGE NOISE: 0.95nV/
Hz
q
VERY LOW DISTORTION: 95dBc (5MHz)
q
LOW DISABLED POWER: 2mW
q
VERY HIGH SLEW RATE: 900V/
s
q
STABLE FOR G
12
DESCRIPTION
The OPA687 combines a very high gain bandwidth and
large signal performance with an ultra-low input noise
voltage (0.95nV/
Hz) while dissipating only 18mA sup-
ply current. Where power savings is paramount, the
OPA687 also includes an optional power down pin that,
when pulled low, will disable the amplifier and decrease
the quiescent current to only 1% of its powered up value.
This optional feature may be left disconnected to insure
normal amplifier operation when no power-down is re-
quired.
The combination of low input voltage and current noise,
along with a 3.8GHz gain bandwidth product, make the
OPA687 an ideal amplifier for wideband transimpedance
APPLICATIONS
q
LOW DISTORTION ADC DRIVER
q
OC-3 FIBER OPTIC RECEIVER
q
LOW NOISE DIFFERENTIAL AMPLIFIERS
q
EQUALIZING RECEIVERS
q
ULTRASOUND CHANNEL AMPLIFIERS
q
IMPROVED REPLACEMENT FOR THE
CLC425
TM
stages. As a voltage gain stage, the OPA687 is opti-
mized for a flat frequency response at a gain of +20 and
is guaranteed stable down to gains of +12. New external
compensation techniques allows the OPA687 to be used
at any inverting gain with excellent frequency response
control. Using this compensation can give an extremely
high dynamic range ADC driver to support > 40MSPS
12- and 14-bit converters.
Ultra-High Dynamic Range
Differential Input ADC Driver
+5V
5V
OPA687
+5V
+5V
5V
850
39pF
OPA687
1.7pF
80pF
V
IN
+
V
IN
80pF
1.7pF
850
39pF
100
20
20
1:2
50
Source
< 6dB
Noise
Figure
ADS852
14-Bit
65MSPS
100
V
CM
V
CM
OPA687
Center Frequency (MHz)
3rd-Order Spurious (dBc)
0
60
65
70
75
80
85
5
10
15
20
25
30
35
40
45
50
4Vp-p
2Vp-p
Measured 2-Tone, 3rd-Order Distortion for
Differential ADC Driver.
OPA687 RELATED PRODUCTS
INPUT NOISE
GAIN BANDWIDTH
SINGLES
DUAL
VOLTAGE (nV/
Hz)
PRODUCT (MHz)
OPA642
--
2.7
210
OPA643
--
2.3
800
OPA686
OPA2686
1.3
1600
Copyright 1998, Texas Instruments Incorporated
SBOS065A
Printed in U.S.A. January, 2001
www.ti.com
2
OPA687
SBOS065A
OPA687U, N
TYP
GUARANTEED
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX LEVEL
(1)
SPECIFICATIONS: V
S
=
5V
R
L
= 100
, R
F
= 750
,
and R
G
= 39.2
, G = +20 (Figure 1 for AC performance only), unless otherwise noted.
NOTES: (1) Test Levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for +25
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. V
CM
is the input common-mode voltage. (5) Tested <3dB below minimum specified CMRR at
CMIR limits.
AC PERFORMANCE (Figure 1)
Closed-Loop Bandwidth
G = +12, R
G
= 39.2
, V
O
= 200mVp-p
600
MHz
typ
C
G = +20, R
G
= 39.2
, V
O
= 200mVp-p
290
180
160
140
MHz
min
B
G = +50, R
G
= 39.2
, V
O
= 200mVp-p
75
60
54
48
MHz
min
B
Gain Bandwidth Product
G
+50
3800
3000
2700
2400
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +20, R
L
= 100
35
24
20
18
MHz
min
B
Peaking at a Gain of +12
3
8
10
14
dB
max
B
Harmonic Distortion
G = +20, f = 5MHz, V
O
= 2Vp-p
2nd Harmonic
R
L
= 100
74
70
68
65
dBc
max
B
R
L
= 500
95
90
88
85
dBc
max
B
3rd Harmonic
R
L
= 100
108
95
90
85
dBc
max
B
R
L
= 500
110
105
100
95
dBc
max
B
Two-Tone, 3rd-Order Intercept
G = +20, f = 20MHz
43
40
39
37
dBm
min
B
Input Voltage Noise Density
f > 1MHz
0.95
1.1
1.15
1.3
nV/
Hz
max
B
Input Current Noise Density
f > 1MHz
2.5
3.2
3.3
3.5
pA/
Hz
max
B
Pulse Response
Rise/Fall Time
0.2V Step
1.2
2.0
2.2
2.5
ns
max
B
Slew Rate
2V Step
900
675
550
450
V/
s
min
B
Settling Time to 0.01%
2V Step
17
ns
typ
C
0.1%
2V Step
15
18
20
25
ns
max
B
1%
2V Step
8
11
13
17
ns
max
B
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V
85
78
75
70
dB
min
A
Input Offset Voltage
V
CM
= 0V
0.1
1
1.2
1.6
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
5
10
V/
C
max
B
Input Bias Current
V
CM
= 0V
20
33
36
40
A
max
A
Input Bias Current Drift (magnitude)
V
CM
= 0V
50
100
nA/
C
max
B
Input Offset Current
V
CM
= 0V
0.2
1.0
1.5
1.8
A
max
A
Input Offset Current Drift
V
CM
= 0V
12
15
nA/
C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.2
3.0
2.9
2.8
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
=
0.5V, Input Referred
100
88
83
78
dB
min
A
Input Impedance
Differential
V
CM
= 0V
2.5 || 2.5
k
|| pF
typ
C
Common-Mode
V
CM
= 0V
1.0 || 1.2
M
|| pF
typ
C
OUTPUT
Output Voltage Swing
400
Load
3.6
3.3
3.1
3.0
V
min
A
100
Load
3.5
3.2
2.9
2.8
V
min
A
Current Output, Sourcing
V
O
= 0V
80
60
50
40
mA
min
A
Current Output, Sinking
V
O
= 0V
80
60
50
40
mA
min
A
Closed-Loop Output Impedance
G = +20, f = < 100kHz
0.006
typ
C
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage
6
6
6
6
V
max
A
Quiescent Current, max
V
S
=
5V
18.5
19
19.5
20.5
mA
max
A
Quiescent Current, min
V
S
=
5V
18.5
18
17.5
16
mA
min
A
Power Supply Rejection Ratio
+PSRR, PSRR
|V
S
| = 4.5V to 5.5V, Input Referred
85
80
78
75
dB
min
A
POWER-DOWN (Disabled Low)
(Pin 8 SO-8; Pin 5 on SOT23-6)
Power-Down Quiescent Current (+V
S
)
225
300
350
400
A
max
A
On Voltage (Enabled High or Floated)
3.3
3.5
3.6
3.7
V
min
A
Off Voltage (Disabled Asserted Low)
1.8
1.7
1.6
1.5
V
max
A
Power-Down Pin Input Bias Current
(V
DIS
= 0)
100
160
160
160
A
max
A
Power-Down Time
200
ns
typ
C
Power-Up Time
60
ns
typ
C
Off Isolation
5MHz, Input to Output
70
dB
typ
C
THERMAL
Specification U, N
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction to Ambient
U 8-Pin, SO-8
125
C/W
typ
C
N 6-Pin, SOT23
150
C/W
typ
C
3
OPA687
SBOS065A
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
OPA687U
SO-8 Surface-Mount
182
40
C to +85
C
OPA687U
OPA687U
Rails
"
"
"
"
"
OPA687U/2K5
Tape and Reel
OPA687N
6-Lead SOT23-6
332
40
C to +85
C
A87
OPA687N/250
Tape and Reel
"
"
"
"
"
OPA687N/3K
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "OPA687U/2K5" will get a single 2500-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................
6.5V
DC
Internal Power Dissipation ...................................... See Thermal Analysis
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: U, N ................................. 40
C to +125
C
Lead Temperature (soldering, 10s) ............................................... +300
C
Junction Temperature (T
J
) ............................................................. +175
C
PIN CONFIGURATION
Top View
SO-8
Top View
SOT23-6
1
2
3
6
5
4
Output
V
S
Noninverting Input
+V
S
DIS
Inverting Input
OPA687
1
2
3
6
5
4
A87
Pin Orientation/Package Marking
8
7
6
5
1
2
3
4
OPA687
NC: No Connection
NC
Inverting Input
Noninverting Input
V
S
DIS
+V
S
Output
NC
4
OPA687
SBOS065A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
R
F
= 750
, R
G
= 39.2
, G = +20 and R
L
= 100
,
unless otherwise noted.
6
3
0
3
6
9
12
15
18
21
24
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (3dB/div)
1
10
100
1000
R
G
= 39.2
V
O
= 0.2Vp-p
G = +30
G = +50
See Figure 1
G = +12
G = +20
6
3
0
3
6
9
12
15
18
21
24
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (3dB/div)
1
10
100
1000
R
G
= R
S
= 50
V
O
= 0.2Vp-p
G = 40
G = 50
See Figure 2
G = 20
G = 30
32
29
26
23
20
17
14
11
8
5
2
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (3dB/div)
1
10
100
1000
R
G
= 39.2
G = +20V/V
V
O
= 2Vp-p
V
O
= 0.2Vp-p
V
O
= 5Vp-p
See Figure 1
V
O
= 1Vp-p
200
100
0
100
200
1.2
0.8
0.4
0
0.4
0.8
1.2
NONINVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
Output Voltage (400mV/div)
G = +20V/V
See Figure 1
Large Signal
1V
Small Signal
100mV
Right Scale
Left Scale
200
100
0
100
200
1.2
0.8
0.4
0
0.4
0.8
1.2
INVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
Output Voltage (400mV/div)
G = 40V/V
See Figure 2
Large Signal
1V
Small Signal
100mV
Right Scale
Left Scale
38
35
32
29
26
23
20
17
14
11
8
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (3dB/div)
1
10
100
1000
R
G
= R
S
= 50
G = 40V/V
V
O
= 2Vp-p
V
O
= 0.2Vp-p
See Figure 2
V
O
= 1Vp-p
V
O
= 5Vp-p
5
OPA687
SBOS065A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
R
F
= 750
, R
G
= 39.2
, G = +20 and R
L
= 100
,
unless otherwise noted (Figure 1).
70
80
90
100
110
Output Voltage (Vp-p)
0.1
10
1
5MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
2nd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
70
80
90
100
110
Output Voltage (Vp-p)
0.1
10
1
5MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
3rd Harmonic Distortion (dBc)
R
L
= 100
R
L
= 500
R
L
=200
60
70
80
90
100
Output Voltage (Vp-p)
0.1
10
1
10MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
2nd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
60
70
80
90
100
Output Voltage (Vp-p)
0.1
10
1
10MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
3rd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
50
60
70
80
90
Output Voltage (Vp-p)
0.1
10
1
20MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
2nd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
50
60
70
80
90
Output Voltage (Vp-p)
0.1
10
1
20MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
3rd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
6
OPA687
SBOS065A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
R
F
= 750
, R
G
= 39.2
, G = +20 and R
L
= 100
,
unless otherwise noted (Figure 1).
2nd HARMONIC DISTORTION vs FREQUENCY
50
60
70
80
90
100
2nd Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
Frequency (MHz)
1
10
20
G = +51
G = +30
G = +20
10.0
1.0
0.10
INPUT VOLTAGE and CURRENT NOISE DENSITY
Frequency (Hz)
100
10M
1k
10k
100k
1M
Current Noise (pA/
Hz)
Voltage Noise (nV/
Hz)
2.5pA/
Hz
0.95nV/
Hz
Current Noise
Voltage Noise
3rd HARMONIC DISTORTION vs FREQUENCY
50
60
70
80
90
100
3rd Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
Frequency (MHz)
1
10
20
G = +51
G = +30
G = +20
TWO-TONE, 3rd-ORDER INTERMODULATION
INTERCEPT vs FREQUENCY
Frequency (MHz)
Intercept (dBm)
10
50
45
40
35
30
25
20
15
10
20
30
40
50
60
70
80
90
100
OPA687
50
39.2
750
50
50
P
I
P
O
50
45
40
35
30
25
20
15
10
5
0
R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
R
S
(
)
28
27
26
25
24
23
22
21
20
19
18
Frequency (MHz)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1
100
10
500
Gain to Capacitive Load (1dB/div)
C
L
= 10pF
C
L
= 50pF
C
L
= 20pF
C
L
= 100pF
OPA687
R
S
V
IN
V
O
C
L
1k
750
39.2
1k
is optional
7
OPA687
SBOS065A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
V
S
=
5V, G = +20, R
G
= 39.2
, and R
L
= 100
,
unless otherwise noted (Figure 1).
CMRR and PSRR
Frequency (Hz)
100
10M
100M
1k
10k
100k
1M
Rejection Ratio (dB)
CMRR
+PSRR
PSRR
120
100
80
60
40
20
0
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
10M
100M
10k
100k
1M
Output Impedance (
)
10
1
0.1
0.01
0.001
OPA687
750
39.2
50
Z
O
POWER SUPPLY and OUTPUT CURRENT
vs TEMPERATURE
Temperature (
C)
Power Supply Current (mA)
Output Current (mA)
50
24
20
16
12
8
4
0
120
100
80
60
40
20
0
25
0
25
50
75
100
125
Output Current Sourcing
Output Current Sinking
Power Supply Current
100
90
80
70
60
50
40
30
20
10
0
0
30
60
90
120
150
180
210
240
270
300
OPEN-LOOP GAIN and PHASE
Frequency (Hz)
100
10M
100M
1G
10G
1k
10k
100k
1M
Open-Loop Gain (10dB/div)
Open-Loop Phase (30
/div)
| A
OL
|
A
OL
INPUT DC ERRORS vs TEMPERATURE
Temperature (
C)
Input Of
fset V
oltage (mV)
Input Bias and Of
fset Current (
A)
50
1.1
0.9
0.7
0.5
0.3
0.1
0.1
29
24
19
14
9
4
1
25
0
25
50
75
100
125
Input Bias Current
Input Offset Voltage
Input Offset Current (0.2
A)
1M
100k
10k
1k
COMMON-MODE and
DIFFERENTIAL INPUT IMPEDANCE
Frequency (Hz)
100
10M
1k
10k
100k
1M
Impedance (Magnitude)
Common-Mode Input Impedance
Differential Input Impedance
8
OPA687
SBOS065A
APPLICATIONS INFORMATION
WIDEBAND, NON-INVERTING OPERATION
The OPA687 provides a unique combination of a very low
input voltage noise along with a very low distortion output
stage to give one of the highest dynamic range op amps
available. Its very high Gain Bandwidth Product (GBP) can
be used to either deliver high signal bandwidths at high
gains, or to deliver very low distortion signals at moderate
frequencies and lower gains. To achieve the full perfor-
mance of the OPA687, careful attention to PC board layout
and component selection is required as discussed in the
remaining sections of this data sheet.
Figure 1 shows the non-inverting gain of +20 circuit used as
the basis for most of the Typical Performance Curves. Most
of the curves were characterized using signal sources with
50
driving impedance, and with measurement equipment
presenting a 50
load impedance. In Figure 1, the 50
shunt resistor at the V
I
terminal matches the source imped-
ance of the test generator, while the 50
series resistor at the
V
O
terminal provides a matching resistor for the measure-
ment equipment load. Generally, data sheet voltage swing
specifications are at the output pin (V
O
in Figure 1), while
output power specifications are at the matched 50
load.
The total 100
load at the output, combined with the 790
total feedback network load, presents the OPA687 with an
effective output load of 89
for the circuit of Figure 1.
Voltage feedback op amps, unlike current feedback designs,
can use a wide range of resistor values to set their gain. The
circuit of Figure 1, and the specifications at other gains, use
an R
G
set to 39.2
and R
F
adjusted to get the desired gain.
Using this guideline will guarantee that the noise added at the
output due to Johnson noise of the resistors will not signifi-
cantly increase the total over that due to the 0.95nV/
Hz input
voltage noise for the op amp itself. This R
G
is suggested as a
good starting point for design. Other values are certainly
acceptable if required by the design.
OPA687
+5V
5V
V
S
+V
S
50
V
O
V
I
50
+
0.1
F
+
6.8
F
6.8
F
R
G
39.2
R
F
750
50
Source
50
Load
0.1
F
FIGURE 1. Non-Inverting G = +20 Specifications and Test
Circuit.
WIDEBAND, INVERTING GAIN OPERATION
There can be significant benefits to operating the OPA687 as
an inverting amplifier. This is particularly true when a
matched input impedance is required. Figure 2 shows the
inverting gain circuit used as a starting point for the Typical
Performance Curves showing inverting mode performance.
OPA687
+5V
5V
+V
S
V
S
95.3
50
V
O
V
I
+
6.8
F
0.1
F
+
6.8
F
0.1
F
0.1
F
R
F
2k
R
G
50
50
Source
50
Load
Driving this circuit from a 50
source, and constraining the
gain resistor, R
G
, to equal 50
, will give both a signal
bandwidth and noise advantage. R
G
, in this case, is acting
as both the input termination resistor and the gain setting
resistor for the circuit. Although the signal gain for the
circuit of Figure 2 is double that for Figure 1, their noise
gains are equal when the 50
source resistor is included.
This has the interesting effect of doubling the equivalent
GBP for the amplifier. This can be seen in comparing the
G = +12 and G = 20 small-signal frequency response
curves. Both show approximately 500MHz bandwidth with
3dB peaking, but the inverting configuration of Figure 2 is
giving 4.4dB higher signal gain. The noise gains are ap-
proximately equal in this case. If the signal source is
actually the low impedance output of another amplifier, R
G
should be increased to be greater than the minimum value
allowed at the output of that amplifier and R
F
adjusted to
get the desired gain. It is critical for stable operation of the
OPA687 that this driving amplifier show a very low output
impedance through frequencies exceeding the expected
closed-loop bandwidth for the OPA687.
WIDEBAND, HIGH SENSITIVITY,
TRANSIMPEDANCE DESIGN
The high Gain Bandwidth Product (GBP) and low input voltage
and current noise for the OPA687 make it an ideal wideband
transimpedance amplifier for low to moderate transimpedance
gains. Very high transimpedance gains (> 100k
) will benefit
from the low input noise current of a FET-input op amp such
as the OPA655. Unity gain stability in the op amp is NOT
FIGURE 2. Inverting G = 40 Specifications and Test
Circuit.
9
OPA687
SBOS065A
required for application as a transimpedance amplifier. Fig-
ure 3 shows one possible transimpedance design example
that would be particularly suitable for the 155Mbit data rate
of an OC-3 receiver. Designs that require high bandwidth
from a large area detector with relatively low transimpedance
gain will benefit from the low input voltage noise for the
OPA687. The amplifier's input voltage noise is peaked up,
at the output, over frequency by the diode source capaci-
tance and can, in many cases, become the dominant output
noise contribution. The key elements to the design are the
expected diode capacitance (C
D
) with the reverse bias volt-
age (V
B
) applied, the desired transimpedance gain, R
F
, and
the GBP for the OPA687 (3600MHz). With these three
variables set (and including the parasitic input capacitance
for the OPA687 added to C
D
), the feedback capacitor value
(C
F
) may be set to control the frequency response.
FIGURE 3. Wideband, High Sensitivity, OC-3
Transimpedance Amplifier.
To achieve a maximally flat 2nd-order Butterworth fre-
quency response, the feedback pole should be set to:
1/(2
R
F
C
F
) =
(GBP/(4
R
F
C
D
))
Adding the common-mode and differential-mode input ca-
pacitance (1.2 + 2.5)pF to the 1pF diode source capacitance
of Figure 3 (C
D
), and targeting a 12k
transimpedance gain
using the 3600MHz GBP for the OPA687, will require a
feedback pole set to 71MHz to get a maximum bandwidth
design. This will require a total feedback capacitance of
0.16pF.
Using this maximum bandwidth, maximally flat frequency
response target will give an approximate 3dB bandwidth
set by:
f
3dB
=
(GBP/2
R
F
C
D
)Hz
The example of Figure 3 will give approximately 100MHz
flat bandwidth using the 0.16pF feedback compensation
capacitor. This bandwidth will easily support an OC-3 re-
ceiver with exceptional sensitivity.
If the total output noise is bandlimited to a frequency less
than the feedback pole frequency, a very simple expression
for the equivalent input noise current can be derived as:
Where:
i
EQ
= Equivalent input noise current if the output noise is
bandlimited to f < 1/(2
R
F
C
D
)
i
N
= Input current noise for the op amp inverting input
e
N
= Input voltage noise for the op amp
C
D
= Total Inverting Node Capacitance
f
= Bandlimiting frequency in Hz (usually a post filter
prior to further signal processing)
Evaluating this expression up to the feedback pole frequency
at 71MHz for the circuit of Figure 3, gives an equivalent
input noise current of 3.0pA/
Hz. This is somewhat higher
than the 2.5pA/
Hz for just the op amp itself. This total
equivalent input current noise is being slightly increased by
the last term in the equivalent input noise expression. It is
essential in this case to use a low voltage noise op amp. For
example, if a slightly higher input noise voltage, but other-
wise identical, op amp were used instead of the OPA687 in
this application (say 2.0nV/
Hz), the total input-referred
current noise would increase to 4.0pA/
Hz. Low input
voltage noise is required for the best sensitivity in these
wideband transimpedance applications. This is often un-
specified for dedicated transimpedance amplifiers with a
total output noise for a specified source capacitance given
instead. It is the relatively high input voltage noise for those
components that cause higher than expected output noise if
the source capacitance is higher than expected.
LOW GAIN COMPENSATION FOR IMPROVED SFDR
A new external compensation technique may be used at low
signal gains to retain the full slew rate and noise benefits of
the OPA687, while maintaining the increased loop gain and
the associated improvement in distortion offered by the
decompensated architecture. This technique shapes the loop
gain for good stability while giving an easily controlled
second-order low pass frequency response. This technique
was used for the circuit on the front page of the data sheet
in a differential configuration to achieve extremely high
SFDR through high frequencies. That circuit is set up for a
differential gain of 8.5V/V from a differential input signal to
the output. Using the transformer shown will improve the
noise figure and translate from a single to a differential
i
i
kT
R
e
R
e
C f
EQ
N
F
N
F
N
D
=
+
+
+
(
)
2
2
2
4
2
3
R
F
12k
12k
0.1
F
100pF
Supply Decoupling
Not Shown
OPA687
+5V
5V
V
B
C
F
0.16pF
1pF
Photodiode
10
OPA687
SBOS065A
signal. If the source is differential already, it may be con-
nected through blocking capacitors into the gain setting
resistors. To set the compensation capacitors for this circuit
(C
S
and C
F
), consider the 1/2 circuit of Figure 4 where the
50
source is reflected through the 1:2 transformer and then
cut in 1/2 and grounded to give a total impedance to AC
ground (for the circuit on the front page of this data sheet)
equal to the 200
.
Considering only the noise gain (this is the same as the non-
inverting signal gain) for the circuit of Figure 4, the low
frequency noise gain, (NG
1
) will be set by the resistor ratios
while the high frequency noise gain (NG
2
) will be set by the
capacitor ratios. The capacitor values set both the transition
frequencies and the high frequency noise gain. If the high
frequency noise gain, determined by NG
2
= 1 + C
S
/C
F
, is set
to a value greater than the recommended minimum stable
gain for the op amp, and the noise gain pole, set by 1/R
F
C
F
,
is placed correctly, a very well-controlled, second-order low
pass frequency response will result.
To choose the values for both C
S
and C
F
, two parameters and
only three equations need to be solved. The first parameter
is the target high frequency noise gain NG
2
, which should be
greater than the minimum stable gain for the OPA687. Here,
a target NG
2
of 24 will be used. The second parameter is the
desired low frequency signal gain, which also sets the low
frequency noise gain NG
1
. To simplify this discussion, we
will target a maximally flat second-order low pass Butterworth
frequency response (Q = 0.707). The signal gain of 4.25
shown in Figure 4 will set the low frequency noise gain to
NG
1
= 1 + R
F
/R
G
(= 5.25 in this example). Then, using only
these two gains and the GBP for the OPA687 (3600MHz),
the key frequency in the compensation can be determined as:
Z
O
=
GBP
NG
1
2
1
NG
1
NG
2
1 2
NG
1
NG
2
C
F
=
1
2
R
F
Z
O
NG
2
C
S
=
NG
2
1
(
)
C
F
f
3
dB
Z
O
GBP
Physically, this Z
0
(4.1MHz for the values shown above) is
set by 1/(2
R
F
(C
F
+ C
S
)) and is the frequency at which the
rising portion of the noise gain would intersect unity gain if
projected back to 0dB gain. The actual zero in the noise gain
occurs at NG
1
Z
0
and the pole in the noise gain occurs at
NG
2
Z
0
. Since GBP is expressed in Hz, multiply Z
0
by 2
and use this to get C
F
by solving:
Finally, since C
S
and C
F
set the high frequency noise gain,
determine C
S
by [Using NG
2
= 24]:
The resulting closed-loop bandwidth will be approximately
equal to:
For the values shown in Figure 4, the f
3dB
will be approxi-
mately 121MHz. This is less than that predicted by simply
dividing the GBP product by NG
1
. The compensation
network controls the bandwidth to a lower value while
providing the full slew rate at the output and an excep-
tional distortion performance due to increased loop gain at
frequencies below NG
1
Z
0
. The capacitor values shown
in Figure 4 are calculated for NG
1
= 5.25 and NG
2
= 24
with no adjustment for parasitics. The full circuit on the
front page of this data sheet shows the capacitors adjusted
for parasitics.
The front page of this data sheet shows the measured 2-tone,
3rd-order distortion for just the amplifier portion of the
circuit.
The upper curve is for a total 2-tone envelope of 4Vp-p,
requiring two tones, each at 2Vp-p across the OPA687
outputs. The lower curve is for a 2Vp-p envelope requiring
each tone to be 1Vp-p. The basic measurement dynamic
range for the two close-in spurious tones is approximately
85dBc. The 4Vp-p test does not show measurable 3rd-order
spurious until 25MHz, while the 2Vp-p is ummeasurable up
to 40MHz center frequency. Two-tone, 2nd-order
intermodulation distortion was unmeasurable for the circuit
on the front page of this data sheet.
(= 1.90pF)
(= 43.8pF)
(= 121MHz)
FIGURE 4. Broadband Low Inverting Gain External Com-
pensation.
R
F
850
C
S
44pF
OPA687
+5V
5V
V
O
V
I
C
F
1.9pF
R
G
200
11
OPA687
SBOS065A
LOW NOISE FIGURE, HIGH DYNAMIC
RANGE AMPLIFIER
The low input noise voltage of the OPA687 and its very high
2-tone intercept can be used to good advantage as a fixed-
gain IF amplifier. While input noise figures in the 10dB
range (for a matched 50
input) are easily achieved with
just the OPA687, Figure 5 shows a technique to reduce the
noise figure even further while providing a broadband, high
gain IF amplifier stage using two stages of the OPA687.
This circuit uses two stages of forward gain with an overall
feedback loop to set the input impedance match. The input
transformer provides both a noiseless voltage gain and a
signal inversion to retain an overall non-inverting signal
path from P
I
to P
O
--since the 2nd amplifier stage is invert-
ing to provide the correct feedback polarity through the
6.19k
resistor. To achieve a 50
input match at the
primary of the 1:2 transformer, the secondary must see a
200
load impedance. At higher frequencies, the match is
provided by the 200
resistor in series with 10pF. At lower
signal frequencies (f < 80MHz), the input match is set by the
feedback through the 6.19k
resistor. The low noise figure
(5dB) for this circuit is achieved by using the transformer,
the low voltage noise OPA687, and the input match set by
feedback. The first stage amplifier provides a gain of +15.
The very high SFDR is provided by operating the output
stage a low signal gain of 2 and using the inverting
compensation to hold it stable. Depending on the load that
is driven, this circuit can give a 2-tone SFDR that exceeds
90dB through 30MHz. Besides offering a very high dynamic
range, this circuit improves on standard IF amplifiers by
offering a precisely controlled gain and a very flexible
output load driving capability.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evalua-
tion of circuit performance using the OPA687 in its two
package styles. Both of these are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in the table below.
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA687U
8-Pin SO-8
DEM-OPA68xU
MKT-351
OPA687N
6-Lead SOT23-6
DEM-OPA6xxN
MKT-348
Contact the Texas Instruments applications support line to
request any of these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA687 is available through either the
Texas Instruments web site (www.ti.com) or as one model
on a disk from the Texas Instruments Applications depart-
ment (1-800-548-6132). The Applications department is
also available for design assistance at this number. These
models do a good job of predicting small-signal AC and
transient performance under a wide variety of operating
conditions. They do not do as well in predicting the har-
monic distortion characteristics. These models do not at-
tempt to distinguish between the package types in their
small-signal AC performance.
FIGURE 5. Very High Dynamic Range High Gain Amplifier.
OPA687
10pF
P
I
1.6pF
6.19k
750
1.5k
200
30.1
420
5dB
Noise
Figure
1:2
50
Source
P
O
OPA687
46pF
Input match
set by this
feedback path
Overall Gain = 35.6dB
P
O
P
I
12
OPA687
SBOS065A
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE NOISE
The OPA687 provides a very low input noise voltage while
requiring a low 18.5mA of quiescent current. To take full
advantage of this low input noise, careful attention to the
other possible noise contributors is required. Figure 6 shows
the op amp noise analysis model with all the noise terms
included. In this model, all the noise terms are taken to be
noise voltage or current density terms in either nV/
Hz or
pA/
Hz.
E
E
I
R
kTR NG
I R
kTR NG
O
NI
BN
S
S
BI
F
F
=
+
(
)
+
(
)
+
(
)
+
2
2
2
2
4
4
E
N
=
E
NI
2
+
I
BN
R
S
(
)
2
+ 4
kTR
S
+
I
BI
R
F
NG
2
+ 4
kTR
F
NG
4kT
R
G
R
G
R
F
R
S
OPA687
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
FIGURE 6. Op Amp Noise Analysis Model.
The total output spot-noise voltage can be computed as the
square root of the squared contributing terms to the output
noise voltage. This computation is adding all the contribut-
ing noise powers at the output by superposition, then taking
the square root to get back to a spot-noise voltage. Equation
1 shows the general form for this output noise voltage using
the terms shown in Figure 6.
Equation 1
Dividing this expression by the noise gain (NG = 1 + R
F
/R
G
)
will give the equivalent input-referred, spot-noise voltage at
the non-inverting input as shown in Equation 2.
Equation 2
Putting high resistor values into Equation 2 can quickly
dominate the total equivalent input-referred noise. A source
impedance on the non-inverting input of 56
will add a
Johnson voltage noise term equal to just that for the ampli-
fier itself. Holding the gain and source resistors low (as was
used in the Typical Performance Curves) will minimize the
resistor noise contribution in Equation 2. Evaluating Equa-
tion 2 for the circuit of Figure 1 will give a total equivalent
input noise of 1.4nV/
Hz. This is slightly increased from the
0.95nV/
Hz for the op amp itself due to the contribution of
the resistor and bias current noise terms.
FREQUENCY RESPONSE CONTROL
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90
, as
it does in high gain configurations. At low gains (increased
feedback factors), most high-speed amplifiers will exhibit a
more complex response with lower phase margin. The
OPA687 is compensated to give a maximally flat 2nd-order
Butterworth closed-loop response at a non-inverting gain of
+20 (Figure 1). This results in a typical gain of +20 band-
width of 290MHz, far exceeding that predicted by dividing
the 3600MHz GBP by 20. Increasing the gain will cause the
phase margin to approach 90
and the bandwidth to more
closely approach the predicted value of (GBP/NG). At a
gain of +50, the OPA687 will very nearly match the 72MHz
bandwidth predicted using the simple formula and the typi-
cal GBP of 3600MHz.
Inverting operation offers some interesting opportunities to
increase the available gain bandwidth product. When the
source impedance is matched by the gain resistor (Figure 2),
the signal gain is (1 + R
F
/R
G
) while the noise gain for
bandwidth purposes is (1 + R
F
/2R
G
). This cuts the noise gain
almost in half, increasing the minimum stable gain for
inverting operation under these condition to 20 and the
equivalent gain bandwidth product to 7.2GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed, high open-loop
gain amplifier like the OPA687 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the amplifier's open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop re-
sponse, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
13
OPA687
SBOS065A
The Typical Performance Curves show the recommended
R
S
vs Capacitive Load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA687. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA687 output pin
(see Board Layout Guidelines).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA687 operating in a gain of +20, the frequency response
at the output pin is very flat to begin with, allowing rela-
tively small values of R
S
to be used for low capacitive loads.
As the signal gain is increased, the unloaded phase margin
will also increase. Driving capacitive loads at higher gains
will require lower R
S
values than shown for a gain of +20.
DISTORTION PERFORMANCE
The OPA687 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots in the Typical Performance Curves
show the typical distortion under a wide variety of condi-
tions. Most of these plots are limited to 110dB dynamic
range. The OPA687's distortion driving a 500
load does
not rise above 90dBc until either the signal level exceeds
3.0V and/or the fundamental frequency exceeds 5MHz.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd harmonic will dominate the
distortion with negligible 3rd harmonic component. Focus-
ing then on the 2nd harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network, in the non-inverting configu-
ration this is sum of R
F
+ R
G
, while in the inverting
configuration this is just R
F
(Figure 2). Increasing output
voltage swing increases harmonic distortion directly. A 6dB
increase in output swing will generally increase the 2nd
harmonic 12dB and the 3rd harmonic 18dB. Increasing the
signal gain will also increase the 2nd harmonic distortion.
Again, a 6dB increase in gain will increase the 2nd and 3rd
harmonic by about 6dB even with a constant output power
and frequency. And finally, the distortion increases as the
fundamental frequency increases due to the roll-off in the
loop gain with frequency. Conversely, the distortion will
improve going to lower frequencies down to the dominant
open-loop pole at approximately 200kHz.
In most applications, the 2nd harmonic will set the limit to
dynamic range. Even order non-linearities arise from slight
imbalances between the positive and negative halves of an
output sinusoid. These imbalanced non-linearities arise from
such mechanisms as voltage dependent base-collector ca-
pacitances and imbalanced source impedances looking out
of the two amplifier power pins. Once a circuit and board
layout has been determined, these imbalances can typically
be nulled out by adjusting the DC operating point for the
signal. An example DC tune is shown in Figure 7. This
circuit has a DC-coupled inverting signal path to the output
pin that provides gain for a small DC offsetting signal
brought into the non-inverting input pin. The output is AC-
coupled to block off this DC operating point from interact-
ing with the next stage.
FIGURE 7. DC Adjustment for 2nd Harmonic Distortion.
For a 1Vp-p output swing in the 10MHz to 20MHz region,
an output DC voltage in the
1.5V range will null the 2nd
harmonic distortion. Tests into a 200
converter input load
have shown > 20dB decrease in the 2nd harmonic using this
technique. Once the required voltage is found for a particular
board, circuit, and signal requirement, that voltage is very
repeatable from part to part and may be set permanently on
the non-inverting input. Minimal degradation from this im-
proved 2nd harmonic distortion over temperature will be
observed. An alternative means to eliminate the 2nd har-
monic distortion is to operate two OPA687s differentially as
shown on the front page of the data sheet. Both single-tone
and 2-tone even order harmonic distortions for this differen-
tial configuration are essentially unmeasureable through
30MHz for a good layout.
The OPA687 has an extremely low 3rd-order harmonic
distortion. This also gives a high 2-tone, 3rd-order
intermodulation intercept as shown in the Typical Perfor-
mance Curves. This intercept curve is defined at the 50
load when driven through a 50
matching resistor to allow
direct comparisons to RF MMIC devices. This network
attenuates the voltage swing from the output pin to the load
by 6dB. If the OPA687 drives directly into the input of a
high impedance device, such as an ADC, this 6dB attenua-
tion is not taken. Under these conditions, the intercept will
increase by a minimum 6dBm. The intercept is used to
R
F
Supply Decoupling
Not Shown
5k
5k
R
G
V
I
20
10k
0.1
F
5V
+5V
OPA687
+V
S
V
S
V
O
14
OPA687
SBOS065A
predict the intermodulation spurious for two closely-spaced
frequencies. If the two test frequencies, f
1
and f
2
, are
specified in terms of average and delta frequency, f
O
= (f
1
+
f
2
)/2 and
f = |f
2
f
1
|/2, the two, 3-order, close-in spurious
tones will appear at f
O
3
f. The difference between two
equal test-tone power levels and these intermodulation spu-
rious power levels is given by (dBc = 2 (IM3 P
O
)) where
IM3 is the intercept taken from the Typical Performance
Curve and P
O
is the power level in dBm at the 50
load for
one of the two, closely-spaced test frequencies. For instance,
at 20MHz, the OPA687--at a gain of +20, has an intercept
of 43dBm at a matched 50
load. If the full envelope of the
two frequencies needs to be 2Vp-p, this requires each tone
to be 4dBm. The 3rd-order intermodulation spurious tones
will then be 2 (43 4)=78dBc below the test-tone power
level (74dBm). If this same 2Vp-p, 2-tone envelope were
delivered directly into the input of an ADC without the
matching loss or the loading of the 50
network, the
intercept would increase to at least 49dBm. With the same
signal and gain conditions, but now driving directly into a
light load, the spurious tones will then be at least 2 (49
4) = 90dBc below the 4dBm test-tone power levels centered
on 20MHz. Tests have shown that, in reality, they are much
lower due to the lighter loading presented by most ADCs.
DC ACCURACY AND OFFSET CONTROL
The OPA687 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection,
high power supply rejection, and low input offset voltage
and bias current offset errors. To take full advantage of its
low
1.0mV input offset voltage, careful attention to input
bias current cancellation is also required. The low noise
input stage for the OPA687 has a relatively high input bias
current (20
A typ into the pins) but with a very close match
between the two input currents--typically
200nA input
offset current. The total output offset voltage may be consid-
erably reduced by matching the source impedances looking
out of the two inputs. For example, one way to add bias
current cancellation to the circuit of Figure 1 would be to
insert a 12.1
series resistor into the non-inverting input
from the 50
terminating resistor. When the 50
source
resistor is DC-coupled, this will increase the source imped-
ance for the non-inverting input bias current to 37.1
. Since
this is now equal to the impedance looking out of the
inverting input (R
F
|| R
G
) for Figure 1, the circuit will cancel
the gains for the bias currents to the output leaving only the
offset current times the feedback resistor as a residual DC
error term at the output. Using the 750
feedback resistor,
this output error will now be less than
1.8
A 750
=
1.4mV over the full temperature range for the circuit of
Figure 1 with a 12.1
resistor added as described. The
output DC offset will then be dominated by the input offset
voltage multiplied by the signal gain. For the circuit of
Figure 1, this will give a worst-case output DC offset of
1.6mV 20 =
32mV over the full temperature range.
A fine-scale output offset null, or DC operating point adjust-
ment is sometimes required. Numerous techniques are avail-
able for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to setting
up a DC current through the feedback resistor. One key
consideration to selecting a technique is to insure that it has
a minimal impact on the desired signal path frequency
response. If the signal path is intended to be non-inverting,
the offset control is best applied as an inverting summing
signal to avoid interaction with the signal source. If the
signal path is intended to be inverting, applying the offset
control to the non-inverting input can be considered. For a
DC-coupled inverting input signal, this DC offset signal will
set up a DC current back into the source that must be
considered. An offset adjustment placed on the inverting op
amp input can also change the noise gain and frequency
response flatness. Figure 8 shows one example of an offset
adjustment for a DC-coupled signal path that will have
minimum impact on the signal frequency response. In this
case, the input is brought into an inverting gain resistor with
the DC adjustment and additional current summed into the
inverting node. The resistor values setting this offset adjust-
ment are much larger than the signal path resistors. This will
insure that this adjustment has minimal impact on the loop
gain and hence, the frequency response.
FIGURE 8. DC-Coupled, Inverting Gain of 40, with Offset
Adjustment.
R
F
2k
250mV Output Adjustment
= = 40
Supply Decoupling
Not Shown
5k
5k
95.3
0.1
F
R
G
50
V
I
20k
10k
0.1
F
5V
+5V
OPA687
+5V
5V
V
O
V
O
V
I
R
F
R
G
15
OPA687
SBOS065A
DISABLE OPERATION
The OPA687 provides an optional disable feature that may
be used to reduce system power. If the DIS control pin is left
unconnected, the OPA687 will operate normally. To dis-
able, the control pin must be asserted low. Figure 9 shows
a simplified internal circuit for the disable control feature.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
T
J
using an OPA687N (SOT23-6 package) in the circuit of
Figure 1 operating at the maximum specified ambient tem-
perature of +85
C and driving a grounded 100
load.
P
D
= 10V (20.5mA) + 5
2
/(4 (100
|| 789
)) = 275mW
Maximum T
J
= +85
C + (0.28W 150
C/W) = 127
C
All actual applications will operate at a lower junction
temperature than the 127
C computed above. Compute your
actual output stage power to get an accurate estimate of
maximum junction temperature, or use the results shown
here as an absolute maximum.
BOARD LAYOUT
Achieving optimum performance with a high frequency
amplifier like the OPA687 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
non-inverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power
supply pins to high frequency 0.1
F decoupling capaci-
tors. At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections should always be decoupled with these
capacitors. Larger (2.2
F to 6.8
F) decoupling capacitors,
effective at lower frequency, should also be used on the
main supply pins. These may be placed somewhat farther
from the device and may be shared among several devices in
the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA687. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter over-
all layout. Metal-film and carbon composition, axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads and PC board trace length as short as
possible. Never use wirewound type resistors in a high
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
FIGURE 9. Simplified Disabled Control Circuit.
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1's emitter. As V
DIS
is pulled
low, additional current is pulled through the 15k
resistor,
eventually turning on these two diodes (
100
A). At this
point, any further current pulled out of V
DIS
goes through
those diodes holding the emitter-based voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode are only those required to operate the
circuit of Figure 9.
THERMAL ANALYSIS
The OPA687 will not require heatsinking or airflow in most
applications. Maximum desired junction temperature will
set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
. The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in
the output stage (P
DL
) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
= V
S
2
/(4 R
L
) where R
L
includes feedback network loading. This is the absolute
highest power that can be dissipated for a given R
L
. All
actual applications will dissipate less power in the output
stage.
16
OPA687
SBOS065A
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal-film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 2.0k
,
this parasitic capacitance can add a pole and/or a zero below
400MHz that can effect circuit operation. Keep resistor
values as low as possible, consistent with load driving
considerations. It has been suggested here that a good
starting point for design would be set the R
G
be set to 39.2
for non-inverting applications. Doing this will automatically
keep the resistor noise terms low, and minimize the effect of
their parasitic capacitance.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, consider
the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set R
S
from the plot of recommended R
S
vs Capacitive
Load. Low parasitic capacitive loads (< 4pF) may not need
an R
S
since the OPA687 is nominally compensated to
operate with a 2pF parasitic load. Higher parasitic cap. loads
without an R
S
are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long trace is
required, and the 6dB signal loss intrinsic to a doubly-
terminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50
environ-
ment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a character-
istic board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA687 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and the
input impedance of the destination device: this total effec-
tive impedance should be set to match the trace impedance.
If the 6dB attenuation of a doubly terminated transmission
line is unacceptable, a long trace can be series-terminated at
the source end only. Treat the trace as a capacitive load in
this case and set the series resistor value as shown in the plot
of R
S
vs Capacitive Load. This will not preserve signal
integrity as well as a doubly-terminated line. If the input
impedance of the destination device is low, there will be
some signal attenuation due to the voltage divider formed by
the series output into the terminating impedance.
e) Socketing a high speed part like the OPA687 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA687
onto the board.
INPUT AND ESD PROTECTION
The OPA687 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins are protected with
internal ESD protection diodes to the power supplies as
shown in Figure 10.
External
Pin
+V
CC
V
CC
Internal
Circuitry
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply
parts driving into the OPA687), current-limiting series resis-
tors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
FIGURE 10. Internal ESD Protection.
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA687N/250
ACTIVE
SOP
DBV
6
250
OPA687N/3K
ACTIVE
SOP
DBV
6
3000
OPA687U
ACTIVE
SOIC
D
8
100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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