Unity Gain Stable, Wideband

VOLTAGE LIMITING AMPLIFIER

OPA688

FEATURES

HIGH LINEARITY NEAR LIMITING

FAST RECOVERY FROM OVERDRIVE: 2.4ns

LIMITING VOLTAGE ACCURACY:

15mV

3dB BANDWIDTH (G = +1): 530MHz

SLEW RATE: 1000V/

5V AND 5V SUPPLY OPERATION

HIGH GAIN VERSION: OPA689

APPLICATIONS

FAST LIMITING ADC INPUT BUFFERS

CCD PIXEL CLOCK STRIPPING

VIDEO SYNC STRIPPING

HF MIXERS

IF LIMITING AMPLIFIERS

AM SIGNAL GENERATION

NON-LINEAR ANALOG SIGNAL PROCESSING

COMPARATORS

DESCRIPTION

The OPA688 is a wideband, unity gain stable voltage-
feedback op amp that offers bipolar output voltage lim-
iting. Two buffered limiting voltages take control of the
output when it attempts to drive beyond these limits.
This new output limiting architecture holds the limiter
offset error to

15mV. The op amp operates linearly to

within 30mV of the output limit voltages.

The combination of narrow nonlinear range and low
limiting offset allows the limiting voltages to be set
within 100mV of the desired linear output range. A fast
2.4ns recovery from limiting ensures that overdrive sig-
nals will be transparent to the signal channel. Imple-

menting the limiting function at the output, as opposed to
the input, gives the specified limiting accuracy for any
gain, and allows the OPA688 to be used in all standard
op amp applications.

Non-linear analog signal processing will benefit from
the OPA688's sharp transition from linear operation to
output limiting. The quick recovery time supports high-
speed applications.

The OPA688 is available in an industry standard pinout
SO-8 package. For higher gain, or transimpedance appli-
cations requiring output limiting with fast recovery,
consider the OPA689.

OPA6

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

LIMITED OUTPUT RESPONSE

Time (200ns/div)

Input and Output Voltage (V)

= V

= 2.0V

G = +2

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

1.60

DETAIL OF LIMITED OUTPUT VOLTAGE

Time (50ns/div)

Output Voltage (V)

www.ti.com

SBOS082A

Printed in U.S.A. February, 2001

OPA688

SBOS082A

AC PERFORMANCE (see Figure 1)
Small Signal Bandwidth

< 0.2Vp-p

G = +1, R

= 25

530

MHz

typ

G = +2

260

150

140

135

MHz

min

G = 1

230

MHz

typ

Gain-Bandwidth Product (G

+5)

< 0.2Vp-p

290

175

170

160

MHz

min

Gain Peaking

G = +1, R

= 25

, V

< 0.2Vp-p

typ

0.1dB Gain Flatness Bandwidth

< 0.2Vp-p

MHz

typ

Large Signal Bandwidth

= 4Vp-p, V

= V

= 2.5V

145

100

MHz

min

Step Response:

Slew Rate

4V Step, V

= V

= 2.5V

1000

800

770

650

min

Rise/Fall Time

0.2V Step

1.2

2.6

2.7

max

Settling Time: 0.05%

2V Step

typ

Spurious Free Dynamic Range

f = 5MHz, V

= 2Vp-p

min

Differential Gain

NTSC, PAL, R

= 500

0.02

typ

Differential Phase

NTSC, PAL, R

= 500

0.01

degrees

typ

Input Noise:

Voltage Noise Density

1MHz

6.3

7.2

7.8

nV/

max

Current Noise Density

1MHz

2.0

2.5

2.9

3.6

pA/

max

DC PERFORMANCE (V

= 0)

Open Loop Voltage Gain (A

)

0.5V

min

Input Offset Voltage

max

Average Drift

max

Input Bias Current

(3)

max

Average Drift

nA/

max

Input Offset Current

0.3

max

Average Drift

nA/

max

INPUT
Common-Mode Rejection

Input Referred, V

0.5V

min

Common-Mode Input Range

(4)

3.3

3.2

3.2

3.1

min

Input Impedance

Differential-Mode

0.4 || 1

|| pF

typ

Common-Mode

1 || 1

|| pF

typ

OUTPUT

= V

= 4.3V

Output Voltage Range

500

4.1

3.9

3.9

3.8

min

Current Output, Sourcing

= 0

105

min

Sinking

= 0

70

min

Closed-Loop Output Impedance

G = +1, R

= 25

, f < 100kHz

0.2

typ

POWER SUPPLY
Operating Voltage, Specified

typ

Maximum

max

Quiescent Current, Maximum

15.8

max

Minimum

15.8

12.8

min

Power Supply Rejection Ratio

= 4.5V to 5.5V

+PSR (Input Referred)

min

OUTPUT VOLTAGE LIMITERS

Pins 5 and 8

Default Limit Voltage

Limiter Pins Open

3.3

3.0

3.0

2.9

min

Minimum Limiter Separation (V

)

200

min

Maximum Limit Voltage

4.3

max

Limiter Input Bias Current Magnitude

(5)

= 0

Maximum

max

Minimum

min

Average Drift

nA/

max

Limiter Input Impedance

2 || 1

|| pF

typ

Limiter Feedthrough

(6)

f = 5MHz

typ

DC Performance in Limit Mode

Limiter Offset

) or (V

)

max

Op Amp Input Bias Current Shift

(3)

typ

AC Performance in Limit Mode

Limiter Small Signal Bandwidth

2V, V

< 0.02Vp-p

450

MHz

typ

Limiter Slew Rate

(7)

100

typ

Limited Step Response

2x Overdrive

Overshoot

= 0 to

2V Step

250

typ

Recovery Time

2V to 0V Step

2.4

2.8

3.0

3.2

max

Linearity Guardband

(8)

f = 5MHz, V

= 2Vp-p

typ

SPECIFICATIONS: V

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

OPA688U

TYP

GUARANTEED

(1)

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+70

+85

UNITS

MAX

LEVEL

(2)

OPA688

SBOS082A

THERMAL CHARACTERISTICS
Temperature Range

Specification: U

40 to +85

typ

Thermal Resistance

Junction-to-Ambient

8-Pin SO-8

125

C/W

typ

NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25

C guaranteed specifications. Junction Temperature = Ambient Temperature

+ 23

C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B)

Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation
from minimum CMRR at specified limits. (5) I

bias current) is positive, and I

bias current) is negative, under these conditions. See Note 3, Figure 1 and Figure

8 . (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V

(or V

) when V

= 0. (7) V

slew rate conditions are: V

= +2V, G = +2, V

= 2V, V

= step between 2V and 0V. V

slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V

= 0V

1Vp-p) centered

between the limiter levels (V

and V

). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).

SPECIFICATIONS: V

(Cont.)

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

OPA688U

TYP

GUARANTEED

(1)

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+70

+85

UNITS

MAX

LEVEL

(2)

AC PERFORMANCE (see Figure 2)
Small Signal Bandwidth

< 0.2Vp-p

G = +1, R

= 25

515

MHz

typ

G = +2

240

110

105

100

MHz

min

G = 1

190

MHz

typ

Gain-Bandwidth Product (G

+5)

< 0.2Vp-p

275

130

125

120

MHz

min

Gain Peaking

G = +1, R

= 25

, V

< 0.2Vp-p

typ

0.1dB Gain Flatness Bandwidth

< 0.2Vp-p

MHz

typ

Large Signal Bandwidth

= 2Vp-p

240

110

105

100

MHz

min

Step Response:

Slew Rate

2V Step

1000

800

770

650

min

Rise/Fall Time

0.2V Step

2.3

2.6

2.7

max

Settling Time: 0.05%

1V Step

typ

Spurious Free Dynamic Range

f = 5MHz, V

= 2Vp-p

min

Input Noise:

Voltage Noise Density

1MHz

6.3

7.2

7.8

nV/

max

Current Noise Density

1MHz

2.0

2.5

2.9

3.6

pA/

max

DC PERFORMANCE

= 2.5V

Open Loop Voltage Gain (A

)

0.5V

min

Input Offset Voltage

max

Average Drift

max

Input Bias Current

(3)

max

Average Drift

nA/

max

Input Offset Current

0.3

max

Average Drift

nA/

max

INPUT
Common-Mode Rejection

Input Referred, V

0.5V

min

Common-Mode Input Range

(4)

0.8

0.7

0.7

0.6

min

Input Impedance

Differential-Mode

0.4 || 1

|| pF

typ

Common-Mode

1 || 1

|| pF

typ

OUTPUT

= V

+1.8V, V

= = V

1.8V

Output Voltage Range

500

1.6

1.4

1.4

1.3

min

Current Output, Sourcing

= 2.5V

min

Sinking

= 2.5V

50

min

Closed-Loop Output Impedance

G = +1, R

= 25

, f < 100kHz

0.2

typ

POWER SUPPLY

Single Supply Operation

Operating Voltage, Specified

typ

Maximum

+12

+12

max

Quiescent Current, Maximum

max

Minimum

min

Power Supply Rejection Ratio

= 4.5V to 5.5V

+PSR (Input Referred)

typ

SPECIFICATIONS: V

= +5V

G = +2, R

= 500

tied to V

= 2.5V, R

= 402

, V

= V

1.2V, V

= V

+1.2V (Figure 2 for AC performance only), unless otherwise noted.

OPA688U

TYP

GUARANTEED

(1)

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+70

+85

UNITS

MAX

LEVEL

(2)

OPA688

SBOS082A

OUTPUT VOLTAGE LIMITERS

Pins 5 and 8

Default Limiter Voltage

Limiter Pins Open

0.9

0.6

0.6

min

Minimum Limiter Separation (V

)

200

min

Maximum Limit Voltage

1.8

max

Limiter Input Bias Current Magnitude

(5)

= 2.5V

Maximum

max

Minimum

min

Average Drift

nA/

max

Limiter Input Impedance

2 || 1

|| pF

typ

Limiter Feedthrough

(6)

f = 5MHz

typ

DC Performance in Limit Mode

= V

1.2V

Limiter Voltage Accuracy

) or (V

)

max

Op Amp Bias Current Shift

(3)

typ

AC Performance in Limit Mode

Limiter Small Signal Bandwidth

= V

1.2V, V

< 0.02Vp-p

300

MHz

typ

Limiter Slew Rate

(7)

typ

Limited Step Response

2x Overdrive

Overshoot

= V

to V

1.2V Step

typ

Recovery Time

= V

1.2V to V

Step

max

Linearity Guardband

(8)

f = 5MHz, V

= 2Vp-p

max

THERMAL CHARACTERISTICS
Temperature Range

Specification: P, U

40 to +85

typ

Thermal Resistance

Junction-to-Ambient

8-Pin SO-8

125

C/W

typ

NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25

C guaranteed specifications. Junction Temperature = Ambient Temperature + 23

at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B) Limits set by

characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum
CMRR at specified limits. (5) I

bias current) is negative, and I

bias current) is positive, under these conditions. See Note 3, Figures 2, and Figure 8. (6) Limiter

feedthrough is the ratio of the output magnitude to the sinewave added to V

(or V

) when V

= 0. (7) V

slew rate conditions are: V

= V

+0.4V, G = +2, V

= V

1.2V,

= step between V

+ 1.2V and V

. V

slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V

= V

1Vp-p) centered

between the limiter levels (V

and V

). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).

SPECIFICATIONS: V

= +5V

(Cont.)

G = +2, R

= 500

tied to V

= 2.5V, R

= 402

, V

= 1.2V, V

= +1.2V (Figure 2 for AC performance only), unless otherwise noted.

OPA688U

TYP

GUARANTEED

(1)

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+70

+85

UNITS

MAX

LEVEL

(2)

OPA688

SBOS082A

ABSOLUTE MAXIMUM RATINGS

Supply Voltage .............................................................................

6.5V

Internal Power Dissipation .......................... See Thermal Characteristics
Common-Mode Input Voltage .............................................................

Differential Input Voltage .....................................................................

Limiter Voltage Range ...........................................................

0.7V)

Storage Temperature Range: P, U ................................ 40

C to +125

Lead Temperature (DIP, soldering, 10s) ..................................... +300

(SO-8, soldering, 3s) ...................................... +260

Junction Temperature .................................................................... +175

PIN CONFIGURATION

Top View

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.

PACKAGE

SPECIFIED

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

NUMBER

RANGE

MARKING

NUMBER

(1)

MEDIA

OPA688U

SO-8 Surface Mount

182

C to +85

OPA688U

Rails

OPA688U/2K5

Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of OPA688U/2K5" will get a single 2500-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

Inverting Input

Non-Inverting Input

Output

OPA688

SBOS082A

TYPICAL PERFORMANCE CURVES : V

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

--LIMITED PULSE RESPONSE

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

Time (20ns/div)

Input and Output Voltages (V)

G = +2

= 2V

NON-INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (Hz)

Normalized Gain (dB)

10M

100M

= 0.2Vp-p

G = +1, R

, R

= 25

G = +1, R

= 175

, R

= 25

G = +2, R

150

G = +5, R

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (Hz)

Normalized Gain (dB)

10M

100M

= 0.2Vp-p

G = 2

G = 5

G = 1

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (V)

= 0.2Vp-p

0.25

0.20

0.15

0.10

0.05

0.10

0.15

0.20

0.25

--LIMITED PULSE RESPONSE

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

Time (20ns/div)

Input and Output Voltages (V)

= +2

= +2V

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output Voltage (V)

= 4Vp-p

= V

= 2.5V

2.5

2.0

1.5

0.10

0.05

0.5

1.0

1.5

2.0

2.5

OPA688

SBOS082A

TYPICAL PERFORMANCE CURVES : V

(Cont.)

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs FREQUENCY

2nd and 3rd Harmonic Distortion (dBc)

HD2

HD3

= 2Vp-p

= 500

Frequency (Hz)

10M

20M

HARMONIC DISTORTION NEAR LIMIT VOLTAGES

Limit Voltage (V)

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2nd and 3rd Harmonic Distortion (dBc)

= 0V

1Vp

= 5MHz

= 500

HD2

HD3

3RD HARMONIC DISTORTION vs OUTPUT SWING

Output Swing (Vp-p)

3rd Harmonic Distortion (dBc)

0.1

1.0

5.0

= 500

= 20MHz

= 10MHz

= 5MHz

= 2MHz

= 1MHz

HARMONIC DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

2nd and 3rd Harmonic Distortion (dBc)

100

1000

= 2Vp-p

= 5MHz

HD2

HD3

2ND HARMONIC DISTORTION vs OUTPUT SWING

Output Swing (Vp-p)

2nd Harmonic Distortion (dBc)

0.1

1.0

5.0

= 500

= 20MHz

= 10MHz

= 1MHz

= 5MHz

= 2MHz

LARGE-SIGNAL FREQUENCY RESPONSE

Frequency (Hz)

10M

100M

Gain (dB)

G = +2

0.2Vp-p

2Vp-p

OPA688

SBOS082A

TYPICAL PERFORMANCE CURVES : V

(Cont.)

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

OPEN-LOOP FREQUENCY RESPONSE

Frequency (Hz)

10k

100k

10M

100M

Open-Loop Gain (dB)

120

150

180

210

240

Open-Loop Phase (deg)

Gain

Phase

= 0.2Vp-p

LIMITER FEEDTHROUGH

Frequency (Hz)

Feedthrough (dB)

10M

50M

402

200

402

= 0.02Vp-p + 2V

LIMITER SMALL-SIGNAL FREQUENCY RESPONSE

Frequency (Hz)

10M

100M

Limiter Gain (dB)

= 0.02Vp-p

402

200

402

= 0.02Vp-p + 2.0V

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (Hz)

10M

100M

Gain to Capacitive Load (dB)

= 0.2Vp-p

= 100pF

= 0

= 10pF

OPA688

200

is optional

402

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

300

(

)

100

INPUT NOISE DENSITY

Frequency (Hz)

100

10k

100k

10M

Input Voltage Noise Density (nV/

Hz)

Input Current Noise Density (pA/

Hz)

Voltage Noise

6.3nV/

Current Noise

2.0pA/

OPA688

SBOS082A

TYPICAL PERFORMANCE CURVES : V

(Cont.)

G = +2, R

= 500

, R

= 402

, V

= V

= 2V (Figure 1 for AC performance only), unless otherwise noted.

100

0.1

CLOSED-LOOP OUTPUT IMPEDANCE

Frequency (Hz)

10M

100M

Output Impedance (

)

G = +1
R

= 25

= 0.2Vp-p

100

PSR AND CMR vs TEMPERATURE

Ambient Temperature (

100

PSR and CMR, Input Referred (dB)

PSR

PSRR

PSR+

CMRR

5.0

4.5

4.0

3.5

3.0

VOLTAGE RANGES vs TEMPERATURE

Ambient Temperature (°C)

100

±Voltage Range (V)

Output Voltage Range

= V

= 4.3V

Common-Mode Input Range

SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE

Ambient Temperature (

100

Supply Current (mA)

120

110

100

Output Current (mA)

Output Current, Sourcing

Supply Current

| Output Current, Sinking |

100

LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE

Limiter Headroom (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Limter Input Bias Current (

Maximum Over Temperature

Minimum Over Temperature

Limiter Headroom = +V

Current = I

or I

= V

)

OPA688

SBOS082A

TYPICAL PERFORMANCE CURVES : V

= +5V

G = +2, R

= 402

, R

= 500

tied to V

= 2.5V,

= V

1.2V

= V

+1.2V, (Figure 2 for AC performance only), unless otherwise noted.

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (Hz)

Normalized Gain (dB)

10M

100M

= 0.2Vp-p

G = 5

G = 2

G = 1

12.0

9.0

6.0

3.0

6.0

9.0

12.0

15.0

18.0

LARGE-SIGNAL FREQUENCY RESPONSE

Frequency (Hz)

10M

100M

Gain (dB)

2.0Vp-p

0.2Vp-p

G = +2

HARMONIC DISTORTION vs FREQUENCY

Frequency (Hz)

10M

20M

2nd and 3rd Harmonic Distortion (dBc)

= 2Vp-p

= 500

HD2

HD3

NON-INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Frequency (Hz)

10M

100M

= 0.2Vp-p

G = +1, R

, R

= 25

G = +1, R

= 175

, R

= 25

G = +2, R

G = +5, R

Normalized Gain (dB)

150

HARMONIC DISTORTION NEAR LIMIT VOLTAGES

Limit Voltages 2.5V

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

2nd and 3rd Harmonic Distortion (dBc)

= 2.5V

1Vp

= 5MHz

= 500

HD2

HD3

AND

--LIMITED PULSE RESPONSE

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Time (20ns/div)

Input and Output Voltages (V)

= V

+1.2V

= V

1.2V

= 2.5V

OPA688

SBOS082A

TYPICAL APPLICATIONS

DUAL-SUPPLY, NON-INVERTING AMPLIFIER

Figure 1 shows a non-inverting gain amplifier for dual-
supply operation. This circuit was used for AC characteriza-
tion of the OPA688, with a 50

source, which it matches,

and a 500

load. The power-supply bypass capacitors are

shown explicitly in Figures 1 and 2, but will be assumed in
the other figures. The limiter voltages (V

and V

) and their

bias currents (I

and I

) have the polarities shown.

SINGLE-SUPPLY, NON-INVERTING AMPLIFIER

Figure 2 shows an AC-coupled, non-inverting gain amplifier
for single +5V supply operation. This circuit was used for
AC characterization of the OPA688, with a 50

source,

which it matches, and a 500

load. The power-supply

bypass capacitors are shown explicitly in Figures 1 and 2,
but will be assumed in the other figures. The limiter voltages
(V

and V

) and their bias currents (I

and I

) have the

polarities shown. Notice that the single-supply circuit can
use three resistors to set V

and V

, where the dual-supply

circuit usually uses four to reference the limit voltages to
ground.

LIMITED OUTPUT, ADC INPUT DRIVER

Figure 3 shows a simple ADC (Analog-to-Digital Con-
verter) driver that operates on a single supply, and gives
excellent distortion performance. The limit voltages track
the input range of the converter, completely protecting
against input overdrive.

FIGURE 1. DC-Coupled, Dual Supply Amplifier.

FIGURE 2. AC-Coupled, Single Supply Amplifier.

FIGURE 3. Single Supply, Limiting ADC Input Driver.

OPA688

49.9

= 5V

402

500

0.1

174

3.01k

1.91k

3.01k

1.91k

0.1

= +2V

= 2V

2.2

= +5V

OPA688

57.6

= 3.7V

= 1.3V

806

523

976

523

402

500

0.1

2.2

0.1

= +5V

0.1

OPA688

= +5V

+3.5V

+1.5V

REFB

REFT

0.1

100pF

= +3.6V

= +1.4V

0.1

402

24.9

562

102

402

715

102

562

ADS822

10-Bit

40MSPS

10-Bit

Data

= +5V

INT/EXT

RSEL

GND

OPA688

SBOS082A

PRECISION HALF WAVE RECTIFIER

Figure 4 shows a half wave rectifier with outstanding preci-
sion and speed. V

(pin 8) will default to a voltage between

3.1 and 3.8V if left open, while the negative limit is set to
ground.

When V

tries to go below ground, CCII charges C

through

, which restores the output back to ground. D

adds a

propagation delay to the restoration process, which then has
an exponential decay with time constant R

/G (G = +2 =

the OPA688 gain). When the signal is above ground, it
decays to ground with a time constant of R

. The OPA688

output recovers very quickly from overdrive.

FIGURE 6. Unity-Gain Buffer.

FIGURE 4. Precision Half Wave Rectifier.

OPA688

= 5V

= +5V

402

200

VERY HIGH SPEED SCHMITT TRIGGER

Figure 5 shows a very high-speed Schmitt trigger. The
output levels are precisely defined, and the switching time
is exceptional. The output voltage swings between

2V.

UNITY-GAIN BUFFER

Figure 6 shows a unity-gain voltage buffer using the OPA688.
The feedback resistor (R

) isolates the output from any board

inductance between pins 2 and 6. We recommend that
R

24.9

for unity-gain buffer applications. R

is an optional

compensation resistor that reduces the peaking typically seen at
G = +1. Choosing R

= R

+ R

gives a unity gain buffer with

approximately the G = +2 frequency response.

DC RESTORER

Figure 7 shows a DC restorer using the OPA688 and
OPA660. The OPA660's OTA amplifier is used as a Current
Conveyor (CCII) in this circuit, with a current gain of 1.0.

OPA688

= 1V

= +3V

40.2

402

100k

402

200

100pF

CCII

U1 = OPA660
R

= 1k

(sets U1's I

)

, D

= 1N4148

FIGURE 7. DC Restorer.

OPA688

= 5V

0.1

3.01k

1.91k

3.01k

1.91k

402

= +5V

200

133

FIGURE 5. Very High Speed Schmitt Trigger.

OPA688

24.9

OPA688

SBOS082A

DESIGN-IN TOOLS

APPLICATIONS SUPPORT

The Texas Instruments Applications Department is available
for design assistance at 1-972-644-5580. The Texas
Instrments web site (http://www.ti.com) has the latest data
sheets and other design aids.

DEMONSTRATION BOARDS

A PC board is available to assist in the initial evaluation of
circuit performance of the OPA688U. It is available as an
unpopulated PCB with descriptive documentation. See the
demonstration board literature for more information. The
summary information for this board is shown in Table I.

c) Place external components close to the OPA688. This
minimizes inductance, ground loops, transmission line ef-
fects and propagation delay problems. Be extra careful with
the feedback (R

), input and output resistors.

d) Use high-frequency components to minimize parasitic
elements. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter lay-
out. Metal film or carbon composition axially-leaded resis-
tors can also provide good performance when their leads are
as short as possible. Never use wirewound resistors for high-
frequency applications. Remember that most potentiometers
have large parasitic capacitances and inductances.

Multilayer ceramic chip capacitors work best and take up
little space. Monolithic ceramic capacitors also work very
well. Use RF type capacitors with low ESR and ESL. The
large power pin bypass capacitors (2.2

F to 6.8

F) should

be tantalum for better high-frequency and pulse perfor-
mance.

e) Choose low resistor values to minimize the time constant
set by the resistor and its parasitic parallel capacitance. Good
metal film or surface mount resistors have approximately
0.2pF parasitic parallel capacitance. For resistors > 1.5k

this adds a pole and/or zero below 500MHz.

Make sure that the output loading is not too heavy. The
recommended 402

feedback resistor is a good starting

point in your design.

f) Use short direct traces to other wideband devices on the
board. Short traces act as a lumped capacitive load. Wide traces
(50 to 100 mils) should be used. Estimate the total capacitive
load at the output, and use the series isolation resistor recom-
mended in the typical performance curve "R

vs Capacitive

Load". Parasitic loads < 2pF may not need the isolation resistor.

g) When long traces are necessary, use transmission line
design techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50

transmis-

sion line is not required on board--a higher characteristic
impedance will help reduce output loading. Use a matching
series resistor at the output of the op amp to drive a
transmission line, and a matched load resistor at the other
end to make the line appear as a resistor. If the 6dB of
attenuation that the matched load produces is not acceptable,
and the line is not too long, use the series resistor at the
source only. This will isolate the source from the reactive
load presented by the line, but the frequency response will
be degraded.

Multiple destination devices are best handled as separate
transmission lines, each with its own series source and shunt
load terminations. Any parasitic impedances acting on the
terminating resistors will alter the transmission line match,
and can cause unwanted signal reflections and reactive
loading.

h) Do not use sockets for high-speed parts like the OPA688.
The additional lead length and pin-to-pin capacitance intro-
duced by the socket creates an extremely troublesome para-
sitic network. Best results are obtained by soldering the part
onto the board.

LITERATURE

DEMONSTRATION

REQUEST

BOARD

PACKAGE

PRODUCT

NUMBER

DEM-OPA68xU

SO-8

OPA68xU

MKT-351

TABLE I. Demo Board Summary Information.

Contact the Texas Instruments Technical Applications Sup-
port Line at 1-972-644-5580 for availability of these boards.

OPERATING INFORMATION

THEORY OF OPERATION

The OPA688 is a voltage-feedback op amp that is unity-gain
stable. The output voltage is limited to a range set by the voltage
on the limiter pins (5 and 8). When the input tries to overdrive the
output, the limiters take control of the output buffer. This avoids
saturating any part of the signal path, giving quick overdrive
recovery and excellent limiter accuracy at any signal gain.

The limiters have a very sharp transition from the linear region
of operation to output limiting. This allows the limiter voltages to
be set very near (< 100mV) the desired signal range. The
distortion performance is also very good near the limiter voltages.

CIRCUIT LAYOUT

Achieving optimum performance with the high-frequency
OPA688 requires careful attention to layout design and
component selection. Recommended PCB layout techniques
and component selection criteria are:

a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins, and leave the
ground and power planes unbroken elsewhere.

b) Provide a high quality power supply. Use linear regulators,
ground plane and power planes to provide power. Place high-
frequency 0.1

F decoupling capacitors < 0.2" away from each

power-supply pin. Use wide, short traces to connect to these
capacitors to the ground and power planes. Also use larger
(2.2

F to 6.8

F) high-frequency decoupling capacitors to by-

pass lower frequencies. They may be somewhat further from the
device, and be shared among several adjacent devices.

OPA688

SBOS082A

POWER SUPPLIES

The OPA688 is nominally specified for operation using
either

5V supplies or a single +5V supply. The maximum

specified total supply voltage of 12V allows reasonable
tolerances on the supplies. Higher supply voltages can break
down internal junctions, possibly leading to catastrophic
failure. Single-supply operation is possible as long as com-
mon mode voltage constraints are observed. The common
mode input and output voltage specifications can be inter-
preted as a required headroom to the supply voltage. Observ-
ing this input and output headroom requirement will allow
design of non-standard or single-supply operation circuits.
Figure 2 shows one approach to single-supply operation.

ESD PROTECTION

ESD damage has been known to damage MOSFET devices,
but any semiconductor device is vulnerable to ESD damage.
This is particularly true for very high-speed, fine geometry
processes.

ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are required when handling the OPA688.

OUTPUT LIMITERS

The output voltage is linearly dependent on the input(s)
when it is between the limiter voltages V

(pin 8) and V

(pin 5). When the output tries to exceed V

or V

, the

corresponding limiter buffer takes control of the output
voltage and holds it at V

or V

Because the limiters act on the output, their accuracy does
not change with gain. The transition from the linear region
of operation to output limiting is very sharp--the desired
output signal can safely come to within 30mV of V

or V

with no onset of non-linearity.

The limiter voltages can be set to within 0.7V of the supplies
(V

+ 0.7V, V

0.7V). They must also be at

least 200mV apart (V

0.2V).

When pins 5 and 8 are left open, V

and V

go to the Default

Voltage Limit; the minimum values are in the Specifications.
Looking at Figure 8 for the zero bias current case will show the
expected range of (V

default limit voltages) = headroom.

When the limiter voltages are more than 2.1V from the supplies
(V

+ 2.1V or V

2.1V), you can use simple

resistor dividers to set V

and V

(see Figure 1). Make sure you

include the Limiter Input Bias Currents (Figure 8) in the
calculations (i.e., I

A out of pin 5, and I

+50

out of pin 8). For good limiter voltage accuracy, run at least
1mA quiescent bias current through these resistors.

When the limiter voltages need to be within 2.1V of the
supplies (V

+ 2.1V or V

2.1V), consider using

low impedance buffers to set V

and V

to minimize errors due

to bias current uncertainty. This will typically be the case for
single supply operation (V

= +5V). Figure 2 runs 2.5mA

through the resistive divider that sets V

and V

. This keeps

errors due to I

and I

1% of the target limit voltages.

The limiters' DC accuracy depends on attention to detail. The
two dominant error sources can be improved as follows:

· Power supplies, when used to drive resistive dividers that set

and V

, can contribute large errors (e.g.,

5%). Using a

more accurate source, and bypassing pins 5 and 8 with good
capacitors, will improve limiter PSRR.

· The resistor tolerances in the resistive divider can also

dominate. Use 1% resistors.

Other error sources also contribute, but should have little
impact on the limiters' DC accuracy:

· Reduce offsets caused by the Limiter Input Bias Currents.

Select the resistors in the resistive divider(s) as described
above.

· Consider the signal path DC errors as contributing to uncer-

tainty in the useable output swing.

· The Limiter Offset Voltage only slightly degrades limiter

accuracy.

Figure 9 shows how the limiters affect distortion performance.
Virtually no degradation in linearity is observed for output
voltage swinging right up to the limiter voltages.

FIGURE 8. Limiter Bias Current vs Bias Voltage.

FIGURE 9. Harmonic Distortion Near Limit Voltages.

100

LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE

Limiter Headroom (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Limter Input Bias Current (

Maximum Over Temperature

Minimum Over Temperature

Limiter Headroom = +V

Current = I

or I

= V

)

HARMONIC DISTORTION NEAR LIMIT VOLTAGES

± Limit Voltage (V)

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2nd and 3rd Harmonic Distortion (dBc)

= 0V

±1Vp

= 5MHz

= 500

HD2

HD3

OPA688

SBOS082A

OFFSET VOLTAGE ADJUSTMENT

The circuit in Figure 10 allows offset adjustment without
degrading offset drift with temperature. Use this circuit with
caution since power supply noise can inadvertently couple
into the op amp.

The operating junction temperature is: T

= T

+ P

where T

is the ambient temperature.

For example, the maximum T

for a OPA688U with G = +2,

= 402

, R

= 100

, and

5V at the maximum

= +85

C is calculated as:

C W

(

)

( )

(

)

= ° +

200

4 100

804

200

270

125

119

CAPACITIVE LOADS

Capacitive loads, such as the input to ADCs, will decrease
the amplifier's phase margin, which may cause high-fre-
quency peaking or oscillations. Capacitive loads

2pF

should be isolated by connecting a small resistor in series
with the output as shown in Figure 11. Increasing the gain
from +2 will improve the capacitive drive capabilities due to
increased phase margin.

FIGURE 10. Offset Voltage Trim.

Remember that additional offset errors can be created by the
amplifier's input bias currents. Whenever possible, match
the impedance seen by both DC input bias currents using R

This minimizes the output offset voltage caused by the input
bias currents.

OUTPUT DRIVE

The OPA688 has been optimized to drive 500

loads, such

as ADCs. It still performs very well driving 100

loads; the

specifications are shown for the 500

load. This makes the

OPA688 an ideal choice for a wide range of high-frequency
applications.

Many high-speed applications, such as driving ADCs, re-
quire op amps with low output impedance. As shown in the
typical performance curve "Output Impedance vs Frequency",
the OPA688 maintains very low closed-loop output imped-
ance over frequency. Closed-loop output impedance in-
creases with frequency, since loop gain decreases with
frequency.

THERMAL CONSIDERATIONS

The OPA688 will not require heat-sinking under most oper-
ating conditions. Maximum desired junction temperature
will set a maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and the additional power dissipated in

the output stage (P

) while delivering load power. P

simply the specified no-load supply current times the total
supply voltage across the part. P

depends on the required

output signals and loads. For a grounded resistive load, and
equal bipolar supplies, it is at a maximum when the output
is at 1/2 either supply voltage. In this condition,
P

= V

/(4R

) where R

includes the feedback network

loading. Note that it is the power in the output stage, and not
in the load, that determines internal power dissipation.

OPA688

(2)

= R

|| R

(1)

TRIM

47k

or Ground

0.1

NOTES: (1) Set R

<< R

TRIM

. (2) R

is optional and

minimizes output offset due to input bias currents.

FIGURE 11. Driving Capacitive Loads.

OPA688

is optional

In general, capacitive loads should be minimized for opti-
mum high-frequency performance. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable, or transmission line, is terminated in
its characteristic impedance.

FREQUENCY RESPONSE COMPENSATION

The OPA688 is internally compensated to be unity-gain
stable, and has a nominal phase margin of 60

at a gain of

+2. Phase margin and peaking improve at higher gains.
Recall that an inverting gain of 1 is equivalent to a gain of
+2 for bandwidth purposes (i.e., noise gain = 2).

Standard external compensation techniques work with this
device. For example, in the inverting configuration, the
bandwidth may be limited without modifying the inverting
gain by placing a series RC network to ground on the
inverting node. This has the effect of increasing the noise
gain at high frequencies, which limits the bandwidth.

OPA688

SBOS082A

FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance.

HARMONIC DISTORTION vs LOAD RESISTANCE

Load Resistance (

)

2nd and 3rd Harmonic Distortion (dBc)

100

1000

= 2Vp-p

= 5MHz

HD2

HD3

To maintain a wide bandwidth at high gains, cascade several
op amps, or use the high gain optimized OPA689.

In applications where a large feedback resistor is required,
such as photodiode transimpedance amplifier, the parasitic
capacitance from the inverting input to ground causes peak-
ing or oscillations. To compensate for this effect, connect a
small capacitor in parallel with the feedback resistor. The
bandwidth will be limited by the pole that the feedback
resistor and this capacitor create. In other high gain applica-
tions, use a three resistor "Tee" network to reduce the RC
time constants set by the parasitic capacitances. Be careful
to not increase the noise generated by this feedback network
too much.

PULSE SETTLING TIME

The OPA688 is capable of an extremely fast settling time in
response to a pulse input. Frequency response flatness and
phase linearity are needed to obtain the best settling times.
For capacitive loads, such as an ADC, use the recommended
R

in the typical performance curve "R

vs Capacitive

Load". Extremely fine-scale settling (0.01%) requires close
attention to ground return current in the supply decoupling
capacitors.

The pulse settling characteristics when recovering from
overdrive are very good.

DISTORTION

The OPA688's distortion performance is specified for a
500

load, such as an ADC. Driving loads with smaller

resistance will increase the distortion as illustrated in Figure
12. Remember to include the feedback network in the load
resistance calculations.

IMPORTANT NOTICE

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accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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