PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OPA6
98
Unity-Gain Stable, Wideband
Voltage Limiting Amplifier
FEATURES
q
HIGH LINEARITY NEAR LIMITING
q
FAST RECOVERY FROM OVERDRIVE: 1ns
q
LIMITING VOLTAGE ACCURACY:
10mV
q
3dB BANDWIDTH (G = +1): 450MHz
q
GAIN BANDWIDTH PRODUCT: 250MHz
q
SLEW RATE: 1100V/
s
q
5V AND +5V SUPPLY OPERATION
q
HIGH-GAIN VERSION AVAILABLE: OPA699
APPLICATIONS
q
FAST LIMITING ANALOG-TO-DIGITAL
CONVERTER (ADC) INPUT BUFFERS
q
CCD PIXEL CLOCK STRIPPING
q
VIDEO SYNC STRIPPING
q
HF MIXERS
q
IF LIMITING AMPLIFIERS
q
AM SIGNAL GENERATION
q
NONLINEAR ANALOG SIGNAL PROCESSING
q
OPA688 UPGRADE
DESCRIPTION
The OPA698 is a wideband, unity-gain stable voltage-
feedback op amp that offers bipolar output voltage limiting.
Two buffered limiting voltages take control of the output
when it attempts to drive beyond these limits. This new
output limiting architecture holds the limiter offset error to
10mV. The op amp operates linearly to within 20mV of the
output limit voltages.
The combination of a narrow nonlinear range and the low
limiting offset allows the limiting voltages to be set within
100mV of the desired linear output range. A fast 1ns
recovery from limiting ensures that overdrive signals will be
transparent to the signal channel. Implementing the limiting
function at the output, as opposed to the input, gives the
specified limiting accuracy for any gain, and allows the
OPA698 to be used in all standard op amp applications.
Nonlinear analog signal processing will benefit from the
ability of the OPA698 to sharply transition from linear opera-
tion to output limiting. The quick recovery time supports
high-speed applications.
The OPA698 is available in an industry standard pinout SO-8
package. For higher gain, or transimpedance applications
requiring output limiting with fast recovery, consider the
OPA699.
OPA698
SBOS258B NOVEMBER 2002 REVISED SEPTEMBER 2003
www.ti.com
Copyright 2002-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
OPA698
V
S
= +5V
4
2
3
7
5
8
6
V
S
= +5V
+3.5V
+1.5V
V
IN
REFB
REFT
IN
0.1
F
100pF
V
H
= +3.6V
V
L
= +1.4V
0.1
F
0.1
F
0.1
F
402
24.9
562
102
402
715
715
102
562
ADS822
10-Bit
40MSPS
10-Bit
Data
V
S
= +5V
INT/EXT
RSEL
+V
S
GND
Single-Supply Limiting ADC Input Driver
OPA698
2
SBOS258B
www.ti.com
SINGLES
DUALS
DESCRIPTION
Output Limiting
OPA699
High Gain BW, Non-unity
Gain Stable
Voltage Feedback
OPA690
OPA2690
High Slew, Unity Gain Stable
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA698
SO-8 Surface Mount
D
40
C to +85
C
OPA698ID
OPA698ID
Rails, 100
"
"
"
"
"
OPA698IDR
Tape and Reel, 2500
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage .............................................................................
6.5V
DC
Internal Power Dissipation .......................... See Thermal Characteristics
Common-Mode Input Voltage .............................................................
V
S
Differential Input Voltage .....................................................................
V
S
Limiter Voltage Range ...........................................................
(V
S
0.7V)
Storage Temperature Range: ID .................................... 40
C to +125
C
Lead Temperature (SO-8, soldering, 3s) ...................................... +260
C
ESD Resistance: HBM .................................................................... 2000V
MM ........................................................................ 200V
CDM .................................................................... 1000V
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PIN CONFIGURATION
Top View
SO
1
2
3
4
NC = Not Connected
8
7
6
5
NC
Inverting Input
Noninverting Input
V
S
V
H
+V
S
Output
V
L
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
RELATED PRODUCTS
OPA698
3
SBOS258B
www.ti.com
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
V
O
< 0.2V
PP
G = +1, R
F
= 25
450
MHz
typ
C
G = +2
215
150
145
140
MHz
min
B
G = 1
215
MHz
typ
C
Gain-Bandwidth Product (G
+5)
V
O
< 0.2V
PP
250
180
175
170
MHz
min
B
Gain Peaking
G = +1, R
F
= 25
, V
O
< 0.2V
PP
5
dB
typ
C
0.1dB Gain Flatness Bandwidth
V
O
< 0.2V
PP
30
MHz
typ
C
Large-Signal Bandwidth
V
O
= 4V
PP
, V
H
= V
L
= 2.5V
160
110
105
100
MHz
min
B
Step Response:
Slew Rate
4V Step, V
H
= V
L
= 2.5V
1100
750
700
650
V/
s
min
B
Rise-and-Fall Time
0.2V Step
1.6
2.3
2.4
2.5
ns
max
B
Settling Time: 0.05%
2V Step
8
ns
typ
C
Harmonic Distortion: 2nd
f = 5MHz, V
O
= 2V
PP
74
65
64
63
dB
min
B
3rd
f = 5MHz, V
O
= 2V
PP
87
83
83
82
dB
min
B
Differential Gain
NTSC, PAL, R
L
= 500
0.012
%
typ
C
Differential Phase
NTSC, PAL, R
L
= 500
0.008
degrees
typ
C
Input Noise:
Voltage Noise Density
f
1MHz
5.6
6.1
6.7
7.2
nV/
Hz
max
B
Current Noise Density
f
1MHz
2.2
2.7
2.8
3
pA/
Hz
max
B
DC PERFORMANCE (V
CM
= 0)
Open-Loop Voltage Gain (A
OL
)
V
O
=
0.5V
63
56
53
52
dB
min
A
Input Offset Voltage
2
5
6
8
mV
max
A
Average Drift
--
15
20
V/
C
max
B
Input Bias Current
(4)
+3
10
11
12
A
max
A
Average Drift
--
15
20
nA/
C
max
B
Input Offset Current
0.3
2
2.5
3
A
max
A
Average Drift
--
10
10
nA/
C
max
B
INPUT
Common-Mode Rejection
Input Referred, V
CM
=
0.5V
61
55
54
52
dB
min
A
Common-Mode Input Range
(5)
3.3
3.2
3.2
3.1
V
min
A
Input Impedance
Differential-Mode
0.32 || 1
M
|| pF
typ
C
Common-Mode
3.5 || 1
M
|| pF
typ
C
OUTPUT
V
H
= V
L
= 4.3V
Output Voltage Range
R
L
500
4.0
3.9
3.9
3.8
V
min
A
Current Output, Sourcing
V
O
= 0
+120
+90
+85
+80
mA
min
A
Sinking
V
O
= 0
120
90
85
80
mA
min
A
Closed-Loop Output Impedance
G = +1, R
F
= 25
, f < 100kHz
0.01
typ
C
POWER SUPPLY
Operating Voltage, Specified
5
V
typ
C
Maximum
--
6
6
6
V
max
A
Quiescent Current, Maximum
V
S
=
5V
15.5
15.9
16.3
16.6
mA
max
A
Minimum
V
S
=
5V
15.5
15.2
14.9
14.6
mA
min
A
Power-Supply Rejection Ratio
+V
S
= 4.5V to 5.5V
PSRR (Input Referred)
75
68
67
66
dB
min
A
OUTPUT VOLTAGE LIMITERS
Output Voltage Limited Range
Pins 5 and 8
3.8
V
max
C
Default Limit Voltage, Upper
Limiter Pins Open
+3.5
+3.3
+3.2
+3.1
V
min
A
Lower
Limiter Pins Open
3.5
3.3
3.2
3.1
V
max
A
Minimum Limiter Separation (V
H
V
L
)
400
400
400
400
mV
min
B
Maximum Limit Voltage
--
4.3
4.3
4.3
V
max
B
Limiter Input Bias Current Magnitude
(6)
V
O
= 0
Maximum
50
60
62
64
A
max
A
Minimum
50
40
38
36
A
min
A
Average Drift
--
30
35
nA/
C
max
B
Limiter Input Impedance
3.4 || 1
M
|| pF
typ
C
Limiter Feedthrough
(7)
f = 5MHz
68
dB
typ
C
DC Performance in Limit Mode
V
IN
=
2V
Limiter Offset
(V
O
V
H
) or (V
O
V
L
)
10
30
35
40
mV
max
A
Op Amp Input Bias Current Shift
(4)
Linear to Limited Output
3
A
typ
C
AC Performance in Limit Mode
Limiter Small-Signal Bandwidth
2V
DC
+ 20mV
PP
600
MHz
typ
C
Limiter Slew Rate
(8)
2x Overdrive, V
H
or V
L
125
V/
s
typ
C
OPA698ID
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
+70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
G = +2, R
F
= 402
, R
L
= 500
, and V
H
= V
L
= 2V (see Figure 1 for AC performance only), unless otherwise noted.
OPA698
4
SBOS258B
www.ti.com
OUTPUT VOLTAGE LIMITERS (Cont.)
Limited Step Response
2x Overdrive
Overshoot
V
IN
= 0 to
2V Step
250
mV
typ
C
Recovery Time
V
IN
=
2V to 0V Step
1
1.9
2
2.1
ns
max
B
Linearity Guardband
(9)
f = 5MHz, V
O
= 2V
PP
30
mV
typ
C
THERMAL CHARACTERISTICS
Temperature Range
Specification: I
40 to +85
C
typ
C
Thermal Resistance
Junction-to-Ambient
D
SO-8
125
--
--
--
C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25
C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23
C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out of node.
(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
(6) I
VH
(V
H
bias current) is positive, and I
VL
(V
L
bias current) is negative, under these conditions. See Note 3, Figure 1, and Figure 8.
(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V
H
(or V
L
) when V
IN
= 0.
(8) V
H
slew rate conditions are: V
IN
= +2V, G = +2, V
L
= 2V, V
H
= step between 2V and 0V. V
L
slew rate conditions are similar.
(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V
O
= 0V
DC
1V
PP
) centered between the limiter levels (V
H
and V
L
). It is the difference
between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).
ELECTRICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
Boldface limits are tested at +25
C.
G = +2, R
F
= 402
, R
L
= 500
, and V
H
= V
L
= 2V (see Figure 1 for AC performance only), unless otherwise noted.
OPA698ID
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
+70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
OPA698
5
SBOS258B
www.ti.com
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
V
O
< 0.2V
PP
G = +1, R
F
= 25
375
MHz
typ
C
G = +2
200
150
145
140
MHz
min
B
G = 1
200
MHz
typ
C
Gain-Bandwidth Product (G
+5)
V
O
< 0.2V
PP
230
170
165
155
MHz
min
B
Gain Peaking
G = +1, R
F
= 25
, V
O
< 0.2V
PP
7
dB
typ
C
0.1dB Gain Flatness Bandwidth
V
O
< 0.2V
PP
30
MHz
typ
C
Large-Signal Bandwidth
V
O
= 2V
PP
200
120
110
100
MHz
min
B
Step Response:
Slew Rate
2V Step
820
560
550
500
V/
s
min
B
Rise-and-Fall Time
0.2V Step
1.9
2.3
2.4
2.5
ns
max
B
Settling Time: 0.05%
1V Step
12
ns
typ
C
Harmonic Distortion: 2nd
f = 5MHz, V
O
= 2V
PP
69
63
62
61
dB
min
B
3rd
f = 5MHz, V
O
= 2V
PP
73
69
68
67
dB
min
B
Input Noise:
Voltage Noise Density
f
1MHz
5.7
nV/
Hz
typ
C
Current Noise Density
f
1MHz
2.3
pA/
Hz
typ
C
DC PERFORMANCE
V
CM
= 2.5V
Open-Loop Voltage Gain (A
OL
)
V
O
=
0.5V
60
54
52
51
dB
min
A
Input Offset Voltage
1
6
7
8
mV
max
A
Average Drift
--
15
15
V/
C
max
B
Input Bias Current
(4)
+3
10
11
12
A
max
A
Average Drift
--
25
25
nA/
C
max
B
Input Offset Current
0.4
2
2.5
3
A
max
A
Average Drift
--
15
15
nA/
C
max
B
INPUT
Common-Mode Rejection
Input Referred, V
CM
=
0.5V
58
54
53
52
dB
min
A
Common-Mode Input Range
(5)
V
CM
0.8 V
CM
0.7 V
CM
0.7 V
CM
0.6
V
min
A
Input Impedance
Differential-Mode
0.32 || 1
M
|| pF
typ
C
Common-Mode
3.5 || 1
M
|| pF
typ
C
OUTPUT
V
H
= V
CM
+1.8V, V
L
= V
CM
1.8V
Output Voltage Range
R
L
500
V
CM
1.6 V
CM
1.4 V
CM
1.4 V
CM
1.3
V
min
A
Current Output, Sourcing
V
O
= 2.5V
+70
+60
+55
+50
mA
min
A
Sinking
V
O
= 2.5V
70
60
55
50
mA
min
A
Closed-Loop Output Impedance
G = +1, R
F
= 25
, f < 100kHz
0.2
typ
C
POWER SUPPLY
Single-Supply Operation
Operating Voltage, Specified
+5
V
typ
C
Maximum
--
+12
+12
+12
V
max
A
Quiescent Current, Maximum
V
S
= +5V
14.3
14.9
15.1
15.3
mA
max
A
Minimum
V
S
= +5V
14.3
13.6
13.4
13.2
mA
min
A
Power-Supply Rejection Ratio
V
S
= 4.5V to 5.5V
+PSRR (Input Referred)
70
dB
typ
C
OUTPUT VOLTAGE LIMITERS
Maximum Limiter Voltage
Pins 5 and 8
+3.9
V
typ
C
Minimum Limiter Voltage
Pins 5 and 8
+1.1
V
typ
C
Default Limiter Voltage
Limiter Pins Open
V
CM
1.1 V
CM
0.8 V
CM
0.7 V
CM
0.6
V
min
B
Minimum Limiter Separation (V
H
V
L
)
400
400
400
400
mV
min
B
Maximum Limit Voltage
--
V
CM
1.8 V
CM
1.8 V
CM
1.8
V
max
B
Limiter Input Bias Current Magnitude
(6)
V
O
= 2.5V
16
A
typ
C
Limiter Input Impedance
3.4 || 1
M
|| pF
typ
C
Limiter Feedthrough
(7)
f = 5MHz
60
dB
typ
C
DC Performance in Limit Mode
V
IN
= V
CM
1.2V
Limiter Voltage Accuracy
(V
O
V
H
) or (V
O
V
L
)
15
30
35
40
mV
max
A
Op Amp Bias Current Shift
(4)
Linear to Limited Output
5
A
typ
C
AC Performance in Limit Mode
Limiter Small-Signal Bandwidth
V
IN
= V
CM
1.2V, V
O
< 0.02V
PP
450
MHz
typ
C
Limiter Slew Rate
(8)
2x Overdrive, V
H
or V
L
100
V/
s
typ
C
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits are tested at +25
C.
G = +2, R
L
= 500
tied to V
CM
= 2.5V, R
F
= 402
, V
L
= V
CM
1.2V, and V
H
= V
CM
+1.2V (see Figure 2 for AC performance only), unless otherwise noted.
OPA698ID
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
+70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
OPA698
6
SBOS258B
www.ti.com
OUTPUT VOLTAGE LIMITERS (Cont.)
Limited Step Response
2x Overdrive
Overshoot
V
IN
= V
CM
to V
CM
1.2V Step
55
mV
typ
C
Recovery Time
V
IN
= V
CM
1.2V to V
CM
Step
3
ns
typ
C
Linearity Guardband
(9)
f = 5MHz, V
O
= 2V
PP
30
mV
typ
C
THERMAL CHARACTERISTICS
Temperature Range
Specification: I
40 to +85
C
typ
C
Thermal Resistance
Junction-to-Ambient
D
SO-8
125
--
--
--
C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25
C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23
C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out of node.
(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
(6) I
VH
(V
H
bias current) is negative, and I
VL
(V
L
bias current) is positive, under these conditions. See Note 3, Figures 2, and Figure 8.
(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V
H
(or V
L
) when V
IN
= 0.
(8) V
H
slew rate conditions are: V
IN
= V
CM
+ 0.4V, G = +2, V
L
= V
CM
1.2V, V
H
= step between V
CM
+ 1.2V and V
CM
. V
L
slew rate conditions are similar.
(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V
O
= V
CM
1V
PP
) centered between the limiter levels (V
H
and V
L
). It is the difference between
the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).
ELECTRICAL CHARACTERISTICS: V
S
= +5V
(Cont.)
Boldface limits are tested at +25
C.
G = +2, R
L
= 500
tied to V
CM
= 2.5V, R
F
= 402
, V
L
= V
CM
1.2V, and V
H
= V
CM
+1.2V (see Figure 2 for AC performance only), unless otherwise noted.
OPA698ID
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
+70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
OPA698
7
SBOS258B
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
1
10
100
400
Frequency (MHz)
Normalized Gain (dB)
9
6
3
0
3
6
See Figure 1
V
O
= 1V
PP
V
O
=
2V
PP
V
O
= 4V
PP
V
O
= 7V
PP
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
10
1
100
800
Frequency (MHz)
Normalized Gain (dB)
6
3
0
3
6
9
12
V
O
= 0.2V
PP
G = +1, R
F
= 25
, R
C
=
G = +1, R
F
= 25
, R
C
= 175
G = +2, R
C
=
G = +5, R
C
=
OPA698
R
F
R
C
R
G
V
O
V
IN
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
10
1
100
500
Frequency (MHz)
Normalized Gain (dB)
3
0
3
6
9
12
V
O
= 0.2V
PP
R
F
= 402
, R
G
Adjusted
See Figure 3
G = 1
G = 5
G = 2
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
1
10
100
400
Frequency (MHz)
Normalized Gain (dB)
9
6
3
0
3
6
See Figure 3
V
O
= 1V
PP
V
O
= 7V
PP
V
O
= 4V
PP
V
O
= 2V
PP
G = 2V/V, R
F
= 402
V
H
--LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
Limiter Gain (dB)
Frequency (Hz)
1M
10M
100M
1G
3
0
3
6
9
OPA698
402
0.02V
PP
+ 2V
DC
402
V
O
2V
DC
G = +2
V
O
= 0.02V
PP
V
H
V
L
Open
V
L
--LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
Limiter Gain (dB)
Frequency (Hz)
1M
10M
100M
1G
3
0
3
6
9
OPA698
402
0.02V
PP
2V
DC
402
V
O
V
L
V
H
Open
2V
DC
G = +2
V
O
= 0.02V
PP
OPA698
8
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TYPICAL CHARACTERISTICS: V
S
=
5V (
Cont.)
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
DETAIL OF LIMITED OUTPUT VOLTAGE
V
OUT
(V)
Time (50ns/div)
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
V
O
SMALL-SIGNAL PULSE RESPONSE
V
OUT
(V)
Time (5ns/div)
0.25
0.20
0.15
0.10
0.05
0.00
0.05
0.10
0.15
0.20
0.25
V
O
= 0.2V
PP
See Figure 1
V
H
--LIMITED PULSE RESPONSE
V
OUT
(V)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
G = +2
V
IN
= 0
+2V
V
H
= +2V
V
OUT
V
IN
V
L
--LIMITED PULSE RESPONSE (20MHz)
V
OUT
(V)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
V
IN
= 0
2V
G = +2
V
L
= 2V
V
OUT
V
IN
LIMITED OUTPUT RESPONSE
V
IN
and V
OUT
(V)
Time (200ns/div)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
V
H
= V
L
= 2V
G = +2
V
OUT
V
IN
LARGE-SIGNAL PULSE RESPONSE
V
OUT
(V)
Time (5ns/div)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
V
O
= 4V
PP
V
H
= V
L
= 2.5V
See Figure 1
OPA698
9
SBOS258B
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TYPICAL CHARACTERISTICS: V
S
=
5V (
Cont.)
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
5MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
Harmonic Distortion (dBc)
Load Resistance (
)
100
1k
55
60
65
70
75
80
85
90
3rd-Harmonic
See Figure 1
2nd-Harmonic
V
O
= 2V
PP
f = 5MHz
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
Frequency (MHz)
0.5
1
10
20
50
60
70
80
90
100
110
3rd-Harmonic
2nd-Harmonic
V
O
= 2V
PP
R
L
= 500
See Figure 1
5MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Output Voltage (V
PP
)
0.5 1.0 1.5 2.0 2.5
3.5 4.0 4.5 5.0
3.0
5.5 6.0 6.5 7.0 7.5 8.0
50
55
60
65
70
75
80
85
90
95
3rd-Harmonic
2nd-Harmonic
R
L
= 500
V
H
= V
L
= V
OPP
/2 + 0.5V
f = 5MHz
See Figure 1
5MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
Harmonic Distortion (dBc)
Supply Voltage (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
45
50
55
60
65
70
75
80
85
90
3rd-Harmonic
2nd-Harmonic
V
O
= 2V
PP
R
L
= 500
See Figure 1
HARMONIC DISTORTION vs NONINVERTING GAIN
Harmonic Distortion (dBc)
Gain (V/V)
1
2
3
4
5
6
7
8
9
10
60
70
80
90
100
3rd-Harmonic
2nd-Harmonic
V
O
= 2V
PP
R
L
= 500
f = 5MHz
HARMONIC DISTORTION vs INVERTING GAIN
Harmonic Distortion (dBc)
Gain (V/V)
1
2
3
4
5
6
7
8
9
10
60
65
70
75
80
85
90
3rd-Harmonic
2nd-Harmonic
V
O
= 2V
PP
R
L
= 500
f = 5MHz
OPA698
10
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TYPICAL CHARACTERISTICS: V
S
=
5V (
Cont.)
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
RECOMMENDED R
S
vs CAPACITIVE LOAD
Resistance (
)
Capacitive Load (pF)
1
10
100
140
120
100
80
60
40
20
0
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
Harmonic Distortion (dBc)
Limit Voltage (V)
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7 1.8
1.9
2.0
40
50
60
70
80
90
3rd-Harmonic
2nd-Harmonic
V
O
= 0V
DC
1V
P
f = 5MHz
R
L
= 500
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain to Capacitive Load (dB)
Frequency (Hz)
1
10
100
1k
9
6
3
0
3
6
V
O
= 0.2V
PP
C
L
= 100pF
C
L
= 47pF
C
L
= 10pF
C
L
= 22pF
OPA698
402
R
S
402
NOTE: (1) 1k
is optional.
1k
(1)
C
L
V
IN
2-TONE, 3RD-ORDER INTERMODULATION
INTERCEPT
5V 500
Intercept Point (dBm)
Frequency (MHz)
0
10
20
30
40
50
50
45
40
35
30
25
20
G = +2V/V
OPA698
402
402
50
500
P
O
P
I
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Voltage Noise (nV/
Hz)
Current Noise (pA/
Hz)
Frequency (Hz)
100
1k
1M
100k
10k
10M
100
10
1
Current Noise (2.2pA/
Hz)
Voltage Noise (5.6nV/
Hz)
OPEN-LOOP FREQUENCY RESPONSE
Open-Loop Gain (dB)
Frequency (Hz)
10k
100k
100M
10M
1M
1G
70
60
50
40
30
20
10
0
10
Open-Loop Phase (
)
0
30
60
90
120
150
180
210
240
V
O
= 0.5V
PP
Phase
Gain
OPA698
11
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TYPICAL CHARACTERISTICS: V
S
=
5V (
Cont.)
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
VOLTAGE RANGE vs TEMPERATURE
Voltage Range (V)
Ambient Temperature (
C)
50
25
0
75
50
25
100
5.0
4.5
4.0
3.5
3.0
Common-Mode Input Range
Output Voltage Range
V
H
= V
L
= 4.3V
LIMITED VOLTAGE RANGE vs TEMPERATURE
Voltage Range (V)
Ambient Temperature (
C)
50
25
0
75
50
25
100
3.8
3.7
3.6
3.5
3.4
3.3
3.2
V
L
V
H
V
H
and V
L
left open
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION vs FREQUENCY
CMRR, PSRR (dB)
Frequency (Hz)
10k
100k
10M
1M
100M
80
70
60
50
40
30
20
10
0
PSRR
+PSRR
CMRR
TYPICAL DC DRIFT OVER TEMPERATURE
Input Bias and Offset Current (
A)
Ambient Temperature (
C)
50
25
0
75
50
25
100
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
Input Offset Voltage (mV)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Input Bias Current (I
B
)
Input Offset Current (V
OS
)
Input Offset Current (I
OS
)
SUPPLY AND OUTPUT CURRENTS
vs TEMPERATURE
Supply Current (mA)
Ambient Temperature (
C)
50
25
0
75
50
25
100
20
18
16
14
12
10
Output Currents (mA)
100
98
96
94
92
90
Output Current, Sourcing
Supply Current
Output Current, Sinking
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Input Bias Current (
A)
Limiter Headroom (V)
0
1.0
0.5
4.0
4.5
3.5
3.0
2.5
2.0
1.5
5.0
100
75
50
25
0
25
50
75
100
Maximum Over Temperature
Minimum Over Temperature
Limiter Headroom = +V
S
V
H
= V
L
(V
S
)
Current = I
VH
or I
VL
OPA698
12
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TYPICAL CHARACTERISTICS: V
S
=
5V (
Cont.)
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
, V
H
= V
L
= 2V, unless otherwise noted.
PSRR AND CMRR vs TEMPERATURE
PSRR and CMRR, Input Referred (dB)
Ambient Temperature (
C)
50
25
0
75
50
25
100
90
85
80
75
70
65
60
55
50
PSRR+
PSRR
CMRR
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
Output Voltage (V)
Output Current (mA)
400
300
200
100
0
200
100
300
400
5
4
3
2
1
0
1
2
3
4
5
1W Internal
Power Limit
1W Internal
Power Limit
R
L
= 25
V
H
= V
L
= 4.3V
R
L
= 50
R
L
= 100
LIMITER FEEDTHROUGH
Feedthrough (dB)
Frequency (MHz)
1
10
100
45
50
55
60
65
70
75
80
85
90
95
OPA698
402
0.02V
PP
+ 2V
DC
Open
402
V
O
V
H
V
L
CLOSED-LOOP OUTPUT IMPEDANCE
Output Impedance (
)
Frequency (Hz)
1M
100M
10M
1G
100
10
1
0.1
0.01
0.001
G = +1
R
F
= 25
V
O
= 0.2V
PP
OPA698
13
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TYPICAL CHARACTERISTICS: V
S
= +5V
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
to V
CM
= +2.5V, V
L
= V
CM
1.2V, V
H
= V
CM
+ 1.2V, unless otherwise noted.
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
1
10
100
400
Frequency (MHz)
Normalized Gain (dB)
3
0
3
6
9
12
15
G = 1
G = 2
G = 5
V
O
= 0.2V
PP
R
F
= 402
, R
G
Adjusted
SMALL-SIGNAL PULSE RESPONSE
V
OUT
(V)
Time (5ns/div)
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
G = +2
LARGE-SIGNAL PULSE RESPONSE
V
OUT
(V)
Time (5ns/div)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
O
= 2V
PP
V
H
= V
CM
+ 1.2V
V
L
= V
CM
1.2V
LARGE-SIGNAL FREQUENCY RESPONSE
1
10
100
400
Frequency (MHz)
Normalized Gain (dB)
9
6
3
0
3
6
V
O
= 3V
PP
V
H
= V
CM
+ 2V
V
L
= V
CM
2V
V
O
= 1V
PP
, V
H
= V
CM
+ 1.2V,
V
L
= V
CM
1.2V
V
O
= 2V
PP
, V
H
= V
CM
+ 1.5V,
V
L
= V
CM
1.5V
See Figure 2
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
10
1
100
500
Frequency (MHz)
Normalized Gain (dB)
9
6
3
0
3
6
9
12
15
V
O
= 0.2V
PP
See Figure 2
G = +1, R
F
= 25
, R
C
=
G =
1, R
F
= 25
,
R
C
= 175
G = +5, R
C
=
G = +2, R
C
=
V
H
and V
L
--LIMITED PULSE RESPONSE
Input and Output Voltage (V)
Time (5ns/div)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
H
= V
CM
+ 1.2V
V
L
= V
CM
1.2V
V
IN
V
OUT
OPA698
14
SBOS258B
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TYPICAL CHARACTERISTICS: V
S
= +5V
T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 500
to V
CM
= +2.5V, V
L
= V
CM
1.2V, V
H
= V
CM
+ 1.2V, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
Load Resistance (
)
100
1k
45
50
55
60
65
70
75
80
3rd-Harmonic
See Figure 2
2nd-Harmonic
V
O
= 2V
PP
f = 5MHz
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
Frequency (MHz)
0.5
1
10
20
50
55
60
65
70
75
80
85
90
3rd-Harmonic
See Figure 2
2nd-Harmonic
V
O
= 2V
PP
R
L
= 500
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Output Voltage Swing (V
PP
)
0.5
1.0
2.0
1.5
2.5
65
70
75
80
85
90
3rd-Harmonic
2nd-Harmonic
R
L
= 500
to V
S
/2
f = 5MHz
V
H
= V
OPP
/2 + V
CM
+ 0.5V
V
L
= V
OPP
/2 + V
CM
0.5V
2-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
Intercept Point (+dBM)
Frequency (MHz)
0
10
40
30
20
50
45
40
35
30
25
20
G = +2V/V
OPA698
402
+2.5V
2.5V
V
S
+V
S
402
50
P
I
500
P
O
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
Harmonic Distortion (dBc)
Limit Voltages - 2.5V
0.9
1.0
1.1
1.6
1.7
1.4
1.5
1.2
1.3
1.8
40
45
50
55
60
65
70
75
80
V
O
= V
CM
1V
P
f = 5MHz
R
L
= 500
3rd-Harmonic
2nd-Harmonic
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Input Bias Current (
A)
Limiter Headroom (V)
0
0.5
2
1.5
1
2.5
100
75
50
25
0
25
50
75
100
Maximum Over Temperature
Minimum
Over Temperature
Limiter Headroom = +V
S
V
H
= V
L
(V
S
)
Current = I
VH
or I
VL
OPA698
15
SBOS258B
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TYPICAL APPLICATIONS
WIDEBAND VOLTAGE LIMITING OPERATION
The OPA698 is a voltage feedback amplifier that combines
features of a wideband, high slew rate amplifier with output
voltage limiters. Its output can swing up to 1V from each rail
and can deliver up to 120mA. These capabilities make it an
ideal interface to drive ADC while adding overdrive protection
for the ADC inputs.
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the
5V
Electrical Characteristics and Typical Characteristics. For
test purposes, the input impedance is set to 50
with a
resistor to ground and the output impedance is set to 500
.
Voltage swings reported in the specifications are taken
directly at the input and output pins. For the circuit of Figure
1, the total output load will be 500
|| 804
= 308
. The
voltage limiting pins are set to
2V through a voltage divider
network between the +Vs and ground for V
H
, and between
Vs and ground for V
L
. These limiter voltages are adequately
bypassed with a 0.1
F ceramic capacitor to ground. The
limiter voltages (V
H
and V
L
) and the respective bias currents
(I
VH
and I
VL
) have the polarities shown. One additional
component is included in Figure 1. An additional resistor
(174
) is included in series with the noninverting input.
Combined with the 25
DC source resistance looking back
towards the signal generator, this gives an input bias current-
canceling resistance that matches the 200
source resis-
tance seen at the inverting input (see the DC accuracy and
offset control section). The power-supply bypass for each
supply consists of two capacitors: one electrolytic 2.2
F and
one ceramic 0.1
F. The power-supply bypass capacitors are
shown explicitly in Figures 1 and 2, but will be assumed in the
other figures. An additional 0.01
F power-supply decoupling
capacitor (not shown here) can be included between the
two power-supply pins. In practical PC board layouts, this
optional-added capacitor will typically improve the 2nd
harmonic distortion performance by 3dB to 6dB.
SINGLE-SUPPLY, NONINVERTING AMPLIFIER
Figure 2 shows an AC-coupled, noninverting gain amplifier
for single +5V supply operation. This circuit was used for AC
characterization of the OPA698, with a 50
source (which it
matches) and a 500
load. The mid-point reference on the
noninverting input is set by two 806
resistors. This gives an
input bias current-canceling resistance that matches the
402
DC source resistance seen at the inverting input (see
the DC accuracy and offset control section). The power-
supply bypass for the supply consists of two capacitors: one
electrolytic 2.2
F and one ceramic 0.1
F. The power-supply
bypass capacitors are shown explicitly in Figures 1 and 2, but
will be assumed in the other figures. The limiter voltages (V
H
and V
L
) and the respective bias currents (I
VH
and I
VL
) have
the polarities shown. These limiter voltages are adequately
bypassed with a 0.1
F ceramic capacitor to ground. Notice
that the single-supply circuit can use three resistors to set V
H
and V
L
, where the dual-supply circuit usually uses four to
reference the limit voltages to ground. While this circuit
shows +5V operation, the same circuit may be used for
single supplies up to +12V.
OPA698
49.9
6
I
VH
V
O
V
IN
I
VL
V
S
= 5V
3
2
4
7
8
5
R
F
402
R
G
402
500
0.1
F
0.1
F
0.1
F
174
3.01k
1.91k
3.01k
1.91k
0.1
F
V
H
= +2V
V
L
= 2V
+
2.2
F
+
2.2
F
+V
S
= +5V
OPA698
57.6
6
I
VH
V
H
= 3.7V
V
O
V
L
= 1.3V
V
IN
I
VL
806
3
2
4
7
8
5
806
523
976
523
R
G
402
R
F
402
500
0.1
F
0.1
F
0.1
F
+
2.2
F
0.1
F
V
S
= +5V
0.1
F
0.1
F
FIGURE 1. DC-Coupled, Dual-Supply Amplifier.
FIGURE 2. AC-Coupled, Single-Supply Amplifier.
OPA698
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WIDEBAND INVERTING OPERATION
Operating the OPA698 as an inverting amplifier has several
benefits and is particularly useful when a matched 50
source and input impedance are required. Figure 3 shows
the inverting gain of 2 circuit used as the basis of the
inverting mode typical characteristics.
As the required R
G
resistor approaches 50
at higher gains,
the bandwidth for the circuit in Figure 3 will far exceed the
bandwidth at that same gain magnitude for the noninverting
circuit of Figure 1. This occurs due to the lower noise gain for
the circuit of Figure 3 when the 50
source impedance is
included in the analysis. For instance, at a signal gain of 8
(R
G
= 50
, R
M
= open, R
F
= 402
) the noise gain for the
circuit of Figure 3 will be 1 + 402
/(50
+ 50
) = 5 due to
the addition of the 50
source in the noise gain equation.
This approach gives considerably higher bandwidth than the
noninverting gain of +8. Using the 250MHz gain bandwidth
product for the OPA698, an inverting gain of 8 from a 50
source to a 50
R
G
will give 52MHz bandwidth, whereas
the noninverting gain of +8 will give 28MHz, as shown in
Figure 4.
0
1
10k
100k
Frequency (MHz)
Gain (dB)
21
18
15
12
9
6
G = +8
G = 8
OPA698
V
S
= +5V
4
2
3
7
5
8
6
V
S
= +5V
+3.5V
+1.5V
V
IN
REFB
REFT
IN
0.1
F
100pF
V
H
= +3.6V
V
L
= +1.4V
0.1
F
0.1
F
0.1
F
402
24.9
562
102
402
715
715
102
562
ADS822
10-Bit
40MSPS
10-Bit
Data
V
S
= +5V
INT/EXT
RSEL
+V
S
GND
LIMITED OUTPUT, ADC INPUT DRIVER
Figure 5 shows a simple ADC driver that operates on a single
supply, and gives excellent distortion performance. The limit
voltages track the input range of the converter, completely
protecting against input overdrive. Note that the limiting
voltages have been set 100mV above/below the correspond-
ing reference voltage from the converter.
OPA698
5V
V
I
2V
+5V
+2V
R
M
66.5
402
200
500
0.1
F
R
T
147
V
H
V
L
V
O
50
Source
In the inverting case, only the feedback resistor appears as
part of the total output load in parallel with the actual load.
For a 500
load used in the typical characteristics, this gives
a total load of 222
in this inverting configuration. The gain
resistor is set to get the desired gain (in this case, 200
for
a gain of 2) while an additional input resistor (R
M
) can be
used to set the total input impedance equal to the source, if
desired. In this case, R
M
= 66.5
in parallel with the 200
gain setting resistor gives a matched input impedance of
50
. This matching is only needed when the input needs to
be matched to a source impedance, as in the characteriza-
tion testing done using the circuit of Figure 3.
For bias current-cancellation matching, the noninverting in-
put requires a 147
resistor to ground. The calculation for
this resistor includes a DC-coupled 50
source impedance
along with R
G
and R
M
. Although this resistor will provide
cancellation for the bias current, it must be well-decoupled
(0.1
F in Figure 3) to filter the noise contribution of the
resistor and the input current noise.
FIGURE 3. Inverting G = 2 Specifications and Test Circuit.
FIGURE 4. G = +8 and 8 Frequency Response.
FIGURE 5. Single Supply, Limiting ADC Input Driver.
OPA698
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LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER
Figure 6 shows a differential ADC driver that takes advan-
tage of the OPA698 limiters to protect the input of the ADC.
Two OPA698s are used. The first one is an inverting configu-
ration at a gain of 2. The second one is in a noninverting
configuration at a gain of +2. Each amplifier is swinging 2V
PP
providing a 4V
PP
differential signal to drive the input of the
ADC. Limiters have been set 100mV away from the magni-
tude of each amplifier's maximum signal to provide input
protection for the ADC while maintaining an acceptable
distortion level.
PRECISION HALF WAVE RECTIFIER
Figure 7 shows a half-wave rectifier with outstanding preci-
sion and speed. V
H
(pin 8) will default to a voltage between
3.1V and 3.8V if left open, while the negative limit is set to
ground.
OPA698
+5V
5V
V
IN
=
1V
PP
200
24.9
1k
1k
0.01
F
10pF
10pF
0.01
F
24.9
100
100
OPA698
+5V
5V
200
+1.1V
1.1V
IN
V
CM
ADC
IN
+1.1V
4V
PP
1.1V
200
FIGURE 6. Single to Differential AC-Coupled, Output Limited ADC Driver.
OPA698
6
V
O
V
S
= 5V
+V
S
= +5V
V
IN
2
3
4
7
8
5
402
402
200
NC
FIGURE 7. Precision Half-Wave Rectifier.
The gain for the circuit in Figure 5 is set at +2. Figure 8 shows
a 100MHz sinewave amplifier, with a gain of +2 and rectified.
Time (2ns/div)
Output
Input
Output V
o
ltage (V)
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
FIGURE 8. 100MHz Sinewave Rectified.
HIGH-SPEED FULL WAVE RECTIFIER
There are two methods shown here to build a high-speed full
wave rectifier with a limiting amplifier: use the half-wave
rectifier described previously with another amplifier to obtain
the full wave rectified, or use the input to set the limiting
voltage.
OPA698
18
SBOS258B
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If the negative excursion of the rectified signal is not desired,
it can easily be removed by replacing the OPA693 with the
OPA698 configured as a difference amplifier with V
L
con-
nected to ground and V
H
left floating.
SOFT-CLIPPING (Compression) CIRCUIT
Figure 13 shows a soft-clipping circuit. As soon as the input
voltage exceeds either V
CH
or V
CL
, the limiting voltages are
driven by the following equations:
V
V
R
V
R
V
R
R
V
R
V
R
V
R
R
H
H
CH
IN
L
CL
IN
=
=
+
+
=
+
+
2
1
1
2
4
3
3
4
As the amplifier is operating in the limiting mode, the output
voltage is compressed with a gain of R
1
+R
2
/R
1
for the
positive excursion above V
CH
, and by a gain of R
3
+R
4
/R
3
for
the negative excursion below V
CL
. Figure 14 shows a 5V
PP
on the input being compressed above
1V with a compres-
sion gain of one-third.
Time (10ns/div)
V
IN
V
OUT
Input and Output V
oltage (V)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
FIGURE 12. 10MHz Sinewave Rectified.
(1)
(2)
High-Speed Full Wave rectifier #1
The circuit shown in Figure 9 uses only one amplifier, in an
inverting gain of 1 configuration. The upper limiting voltage
is left open, resulting in an upper limiting voltage of +3.5V.
The lower limiting voltage is connected to the input signal,
resulting in the following behavior. When the input voltage is
negative, the amplifier is not limiting, resulting in the inversion
of the input sinewave to the output. During the positive
excursion of the input signal, the output signal is being driven
by the limiting input pin. Since the output is driven from the
limiter input pin from positive inputs, the lower slew rate in the
input path restricts the application of this approach to lower
amplitude and/or frequencies. A 2MHz fully rectified sinewave
is shown in Figure 10.
V
H
V
L
V
O
402
402
500
200
50
Source
57.2
OPA698
Time (50ns/div)
Output V
o
ltage (V)
0.6
0.4
0.2
0
0.2
0.4
0.6
FIGURE 9. High-Speed Full Wave Rectifier #1.
FIGURE 10. 2MHz Sinewave Rectified.
FIGURE 11. High-Speed Full Wave Rectifier #2.
In order to reach higher frequencies, a second method is
recommended.
High Speed Full Wave rectifier #2
The circuit shown in Figure 11 combines a half-wave rectifier
driving the OPA693 in an inverting configuration, while the
input signal drives the noninverting input of the fixed gain
amplifier OPA693, resulting in a full wave rectifier function.
Results are shown in Figure 12.
OPA698
200
V
H
V
L
75
300
200
OPA693
300
50
700MHz
Internal
Gain Set
50
Load
75
OPA698
19
SBOS258B
www.ti.com
VERY HIGH-SPEED SCHMITT TRIGGER
Figure 15 shows a very high-speed Schmitt Trigger. The
output levels are precisely defined, and the switching time is
exceptional. The output voltage swings between V
H
and V
L
.
The circuit operates as follow. When the input voltage is less
than V
HL
then the output is limiting at V
H
. When the input is
greater than V
HH
then the output is limiting at V
L
, with V
HL
and
V
HH
defined as the following:
V
R
R
R
R
V
R
R
R
R
V
HL HH
REF
OUT
,
||
||
||
||
=
+
1
2
3
1
1
2
3
2
Due to the inverting function realized by the Schmitt Trigger,
V
HL
corresponds to V
OUT
= V
H
, and V
HH
corresponds to
V
OUT
= V
L
.
Time (100ns/div)
Input and Output V
oltage (V)
3
2
1
0
1
2
3
V
IN
V
OUT
OPA698
R
2
402
R
1
200
R
3
200
V
REF
V
OUT
V
H
V
L
+2V
2V
V
IN
FIGURE 13. Soft-Clipping Circuit.
FIGURE 14. Soft Clipping with a Gain of 1/3 above the clamp
level (
1V).
Figure 16 shows the Schmitt Trigger operating with V
REF
=
+5V. This gives us V
HH
= 2.4V and V
HL
= 1.6V. The propa-
gation delay for the OPA698 in a Schmitt Trigger configura-
tion is 6ns from high-to-low, and 5ns from low-to-high.
OPA698
V
H
V
L
R
4
2k
R
3
1k
24.9
R
2
2k
V
CL
1V
V
CH
+1V
V
OUT
V
IN
R
1
1k
UNITY-GAIN BUFFER
Figure 17 shows a unity-gain voltage buffer using the OPA698.
The feedback resistor (R
F
) isolates the output from the input
capacitance at the inverting input. R
F
= 24.9
is recom-
mended for unity-gain buffer applications. R
C
is an optional
compensation resistor that reduces the peaking typically
seen at G = +1. Choosing R
C
= R
S
+ R
F
gives a unity-gain
buffer with approximately the G = +2 frequency response.
The frequency response for this circuit is shown in the
electrical characteristics curves.
Time (10ns/div)
Input and Output V
oltage (V)
4
3
2
1
0
1
2
3
4
V
IN
V
OUT
FIGURE 16. Schmitt Trigger Time Domain Response for a
10MHz Sinewave.
OPA688
V
O
R
S
V
S
R
F
24.9
R
C
FIGURE 17. Unity-Gain Buffer.
FIGURE 15. Very High-Speed Schmitt Trigger.
OPA698
20
SBOS258B
www.ti.com
OPA698
V
L
V
H
Open
Open
V
L
V
H
V
OUT
R
3
402
R
4
75
OPA698
R
1
75
R
2
402
V
IN
0.2V
FIGURE 19. Sync Stripper Circuit.
BOARD
LITERATURE
PRODUCT
PACKAGE
PART NO.
REQUEST NO.
OPA698ID
SO-8
DEM-OPA68xU
SBOU009
TABLE I. Demo Board Summary Information.
DC RESTORER
Figure 18 shows a DC restore circuit using the OPA698 and
OPA660. The buffer element of the OPA660 is used to buffer
the input signal while the transconductance element is used
to restore the DC level after the decoupling capacitor C
1
. The
DC level is set using R
1
and R
2
. The OPA698 is configured
at a gain of 2 to compensate for the 75
series into a 75
load. The OPA698 also limits the output to ground.
VIDEO SYNC STRIPPER
Figure 19 shows a sync stripper using two OPA698 output-
limiting op amps. One OPA698 is configured as a limiting
inverting comparator. Referred to the input, the negative
excursions lower than 0.2V are clipped to ground, and all
excursions greater than 0.2V generate an output voltage
set by the default limiting value (3.5V). The second OPA698
is using this waveform to effectively remove the sync pulse
from the video signal.
DESIGN-IN TOOLS
APPLICATIONS SUPPORT
The Texas Instruments Applications Department is available
for design assistance at 1-972-644-5580. The Texas Instru-
ments web site (www.ti.com) has the latest product data
sheets and other design aids.
DEMONSTRATION BOARDS
A PC board is available to assist in the initial evaluation of
circuit performance of the OPA698ID. It is available as an
unpopulated PCB with descriptive documentation. See the
demonstration board literature for more information. The
summary information for this board is shown in Table I.
FIGURE 18. DC Restore to Ground.
This board can be requested through the TI web site.
OPERATING SUGGESTIONS
THEORY OF OPERATION
The OPA698 is a voltage-feedback op amp that is unity-gain
stable. The output voltage is limited to a range set by the
voltage on the limiter pins (5 and 8). When the input tries to
overdrive the output, the limiters take control of the output
buffer. This action from the limiters avoids saturating any part
of the signal path, giving quick overdrive recovery and
OPA698
V
O
75
Load
8
5
V
L
V
H
= Open
402
R
2
1k
R
3
200
D
1
402
20
V
IN
200
75
R
Q
250
R
1
19.6k
D
2
C
1
20
F
6
1
C
E
B
3
CCII
2
U1
5
+1
U1
U1 = OPA660
R
Q
= 250
(sets I
Q
for U1)
D
1
, D
2
= 1N4148
OPA698
21
SBOS258B
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excellent limiter accuracy at any signal gain. The limiters
have a very sharp transition from the linear region of opera-
tion to output limiting. This transition allows the limiter volt-
ages to be set very near (< 100mV) the desired signal range.
The distortion performance is also very good near the limiter
voltages.
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s) when
it is between the limiter voltages V
H
(pin 8) and V
L
(pin 5).
When the output tries to exceed V
H
or V
L
, the corresponding
limiter buffer takes control of the output voltage and holds it
at V
H
or V
L
. Because the limiters act on the output, their
accuracy does not change with gain. The transition from the
linear region of operation to output limiting is very sharp--the
desired output signal can safely come to within 30mV of V
H
or V
L
with no onset of non-linearity. The limiter voltages
can be set to within 0.7V of the supplies (V
L
V
S
+ 0.7V,
V
H
+V
S
0.7V). They must also be at least 400mV apart
(V
H
V
L
0.4V). When pins 5 and 8 are left open, V
H
and
V
L
go to the default voltage limit; the minimum values are
given in the electrical specifications. Looking at Figure 20 for
the zero bias current case shows the expected range of
(V
S
default limit voltages) = headroom.
limits errors due to I
VH
and I
VL
<
1% of the target limit
voltages. The limiters' DC accuracy depends on attention to
detail. The two dominant error sources can be improved as
follows:
Power supplies, when used to drive resistive dividers that
set V
H
and V
L
, can contribute large errors (for example,
5%). Using a more accurate source, and bypassing pins
5 and 8 with good capacitors, will improve limiter PSRR.
The resistor tolerances in the resistive divider can also
dominate. Use 1% resistors.
Other error sources also contribute, but should have little
impact on the limiters' DC accuracy:
Reduce offsets caused by the Limiter Input Bias Currents.
Select the resistors in the resistive divider(s) as described
above.
Consider the signal path DC errors as contributing to
uncertainty in the useable output swing.
The limiter offset voltage only slightly degrades limiter
accuracy. Figure 21 shows how the limiters affect distor-
tion performance. Virtually no degradation in linearity is
observed for output voltage swinging right up to the limiter
voltages.
Limiter Input Bias Current (
A)
Limiter Headroom (V)
0
0.5
2
1.5
1
2.5
100
75
50
25
0
25
50
75
100
Maximum Over Temperature
Minimum
Over Temperature
Limiter Headroom = +V
S
V
H
= V
L
(V
S
)
Current = I
VH
or I
VL
FIGURE 20. Limiter Bias Current vs Bias Voltage.
When the limiter voltages are more than 2.1V from the
supplies (V
L
V
S
+ 2.1V or V
H
+V
S
2.1V), you can use
simple resistor dividers to set V
H
and V
L
(see Figure 1). Make
sure to include the limiter input bias currents (Figure 8) in the
calculations (that is, I
VL
= 50
A out of pin 5, and I
VH
= +50
A
out of pin 8). For good limiter voltage accuracy, run at least
1mA quiescent bias current through these resistors. When
the limiter voltages need to be within 2.1V of the supplies (V
L
V
S
+ 2.1V or V
H
+V
S
2.1V), consider using low
impedance buffers to set V
H
and V
L
to minimize errors due
to bias current uncertainty. This condition will typically be the
case for single-supply operation (V
S
= +5V). Figure 2 runs
2.5mA through the resistive divider that sets V
H
and V
L
. This
OUTPUT DRIVE
The OPA698 has been optimized to drive 500
loads, such
as ADCs. It still performs very well driving 100
loads; the
specifications are shown for the 500
load. This makes the
OPA698 an ideal choice for a wide range of high-frequency
applications.
Many high-speed applications, such as driving ADCs, require
op amps with low output impedance. As shown in the typical
performance curve
Output Impedance vs Frequency, the
OPA698 maintains very low closed-loop output impedance
over frequency. Closed-loop output impedance increases
with frequency, since loop gain decreases with frequency.
Harmonic Distortion (dBc)
Limit Voltage (V)
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7 1.8
1.9
2
40
50
60
70
80
90
3rd-Harmonic
2nd-Harmonic
V
O
= 0V
DC
1V
P
f = 5MHz
R
L
= 500
FIGURE 21. Harmonic Distortion Near Limit Voltages.
OPA698
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SBOS258B
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FIGURE 22. Driving Capacitive Loads.
OPA698
C
L
R
L
R
T
R
S
R
G
R
F
V
O
R
L
is optional
THERMAL CONSIDERATIONS
The OPA698 will not require heat sinking under most oper-
ating conditions. Maximum desired junction temperature will
set a maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150
C.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and the additional power dissipated in
the output stage (P
DL
) while delivering load power. P
DQ
is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
depends on the required
output signals and loads. For a grounded resistive load, and
equal bipolar supplies, it is at maximum when the output is
at 1/2 either supply voltage. In this condition, P
DL
= V
S
2
/(4R
L
)
where R
L
includes the feedback network loading. Note that it
is the power in the output stage, and not in the load, that
determines internal power dissipation.
The operating junction temperature is: T
J
= T
A
+ P
D
x
JA
,
where T
A
is the ambient temperature. For example, the
maximum T
J
for a OPA698ID with G = +2, R
F
= 402
, R
L
=
100
, and
V
S
=
5V at the maximum T
A
= +85
C is
calculated as:
P
V
mA
mW
P
V
mW
P
mW
mW
mW
T
C
mW
C W
C
DQ
DL
D
J
=
(
)
=
=
( )
(
)
=
=
+
=
=
+
=
10
15 5
155
5
4
100
804
70
155
70
225
85
225
125
113
2
.
||
/
This would be the maximum T
J
from V
O
=
2.5V
DC
. Most
applications will be at a lower output stage power and have
a lower T
J
.
CAPACITIVE LOADS
Capacitive loads, such as the input to ADCs, will decrease
the amplifier phase margin, which may cause high-frequency
peaking or oscillations. Capacitive loads
2pF should be
isolated by connecting a small resistor in series with the
output, as shown in Figure 22. Increasing the gain from +2
will improve the capacitive drive capabilities due to increased
phase margin.
In general, capacitive loads should be minimized for optimum
high-frequency performance. The capacitance of coax cable
(29pF/ft for RG-58) will not load the amplifier when the
coaxial cable, or transmission line, is terminated in its char-
acteristic impedance.
FREQUENCY RESPONSE COMPENSATION
The OPA698 is internally compensated to be unity-gain
stable, and has a nominal phase margin of 60
at a gain of
+2. Phase margin and peaking improve at higher gains.
Recall that an inverting gain of 1 is equivalent to a gain of
+2 for bandwidth purposes (that is, noise gain = 2). Standard
external compensation techniques work with this device.
For example, in the inverting configuration, the bandwidth
may be limited without modifying the inverting gain by placing
a series RC network to ground on the inverting node. This
has the effect of increasing the noise gain at high frequen-
cies, which limits the bandwidth.
To maintain a wide bandwidth at high gains, cascade several
op amps, or use the high-gain optimized OPA699.
In applications where a large feedback resistor is required,
such as photodiode transimpedance amplifier, the parasitic
capacitance from the inverting input to ground causes peak-
ing or oscillations. To compensate for this effect, connect a
small capacitor in parallel with the feedback resistor. The
bandwidth will be limited by the pole that the feedback
resistor and this capacitor create. In other high-gain applica-
tions, use a three-resistor
Tee network to reduce the RC time
constants set by the parasitic capacitances. Be careful not to
increase the noise generated by this feedback network too
much.
PULSE SETTLING TIME
The OPA698 is capable of an extremely fast settling time in
response to a pulse input. Frequency response flatness and
phase linearity are needed to obtain the best settling times.
For capacitive loads, such as an ADC, use the recom-
mended R
S
in the typical performance curve
R
S
vs Capaci-
tive Load. Extremely fine-scale settling (0.01%) requires
close attention to ground return current in the supply
decoupling capacitors.
The pulse settling characteristics, when recovering from
overdrive, are very good.
DISTORTION
The OPA698 distortion performance is specified for a 500
load, such as an ADC. Driving loads with smaller resistance
will increase the distortion, as illustrated in Figure 23. Re-
member to include the feedback network in the load resis-
tance calculations.
OPA698
23
SBOS258B
www.ti.com
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.6nV/
Hz input voltage noise for
the OPA698, however, is much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 24 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/
Hz
or pA/
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 25.
E
E
I
R
kTR
NG
I R
kTR NG
O
NI
BN S
S
BI F
F
=
+
(
)
+
+
(
)
+
2
2
2
2
4
4
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at
the noninverting input, as shown in Equation 4.
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN S
S
BI F
F
=
+
(
)
+
+
+
2
2
2
4
4
Evaluating these two equations for the OPA698 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 11.9nV/
Hz and a total equivalent input spot
noise voltage of 6nV/
Hz. This total input-referred spot noise
voltage is only slightly higher than the 5.6nV/
Hz specifica-
tion for the op amp voltage noise alone. This will be the case
as long as the impedances appearing at each op amp input
are limited to a maximum value of 300
. Keeping both
(R
F
|| R
G
) and the noninverting input source impedance less
than 300
will satisfy both noise and frequency response
flatness considerations. Since the resistor-induced noise is
relatively negligible, additional capacitive decoupling across
the bias current cancellation resistor (R
T
) for the inverting op
amp configuration of Figure 3 is not required, but is still
desirable.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a large variety of
applications. The power-supply current trim for the OPA698
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically
8
A at each input terminal),
the close matching between them may be used to reduce the
output DC error caused by this current. The total output offset
voltage may be considerably reduced by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the configura-
tion of Figure 1, using worst-case +25
C input offset voltage
and current specifications, gives a worst-case output offset
voltage equal to: (NG = noninverting signal gain)
(NG V
OS(MAX)
)
(R
F
I
OS(MAX)
)
=
(2 5mV)
(402
1.4
A)
=
10.6mV
FIGURE 23. 5MHz Harmonic Distortion vs Load Resistance.
4kT
R
G
R
G
R
F
R
S
OPA698
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
FIGURE 24. Op Amp Noise Analysis Model.
(3)
(4)
40
45
50
55
60
65
70
75
80
85
90
Load Resistance (
)
2nd- and 3rd-Harmonic Distortion (dBc)
50
100
1000
V
O
= 2V
PP
f
1
= 5MHz
HD2
HD3
OPA698
24
SBOS258B
www.ti.com
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be consid-
ered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 25 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain as well as the frequency response.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with the high-frequency
OPA698 requires careful attention to layout design and
component selection. Recommended PCB layout techniques
and component selection criteria are:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins, and leave the
ground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regu-
lators, ground plane and power planes to provide power.
Place high frequency 0.1
F decoupling capacitors < 0.2"
away from each power-supply pin. Use wide, short traces to
connect to these capacitors to the ground and power planes.
Also use larger (2.2
F to 6.8
F) high-frequency decoupling
capacitors to bypass lower frequencies. They may be some-
what further from the device, and be shared among several
adjacent devices.
c) Place external components close to the OPA698. This
minimizes inductance, ground loops, transmission line ef-
fects and propagation delay problems. Be extra careful with
the feedback (R
F
), input and output resistors.
d) Use high-frequency components to minimize parasitic
elements. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter layout.
Metal film or carbon composition axially-leaded resistors can
also provide good performance when their leads are as short
as possible. Never use wirewound resistors for high-fre-
quency applications. Remember that most potentiometers
have large parasitic capacitances and inductances. Multi-
layer ceramic chip capacitors work best and take up little
space. Monolithic ceramic capacitors also work very well.
Use R
F
type capacitors with low ESR and ESL. The large
power pin bypass capacitors (2.2
F to 6.8
F) should be
tantalum for better high frequency and pulse performance.
e) Choose low resistor values to minimize the time con-
stant set by the resistor and its parasitic parallel capacitance.
Good metal film or surface mount resistors have approxi-
mately 0.2pF parasitic parallel capacitance. For resistors
> 1.5k
, this adds a pole and/or zero below 500MHz. Make
sure that the output loading is not too heavy. The recom-
mended 402
feedback resistor is a good starting point in
most designs.
f) Use short direct traces to other wideband devices on
the board. Short traces act as a lumped capacitive load.
Wide traces (50 to 100 mils) should be used. Estimate the
total capacitive load at the output, and use the series isola-
tion resistor recommended in the typical performance curve,
R
S
vs Capacitive Load. Parasitic loads < 2pF may not need
the isolation resistor.
R
F
1k
200mV Output Adjustment
= = 2
Supply Decoupling
Not Shown
5k
5k
328
0.1
F
R
G
500
V
I
20k
10k
0.1
F
5V
+5V
OPA698
+5V
5V
V
O
V
O
V
I
R
F
R
G
FIGURE 25. DC-Coupled, Inverting Gain of 2, with Offset
Adjustment.
OPA698
25
SBOS258B
www.ti.com
g) When long traces are necessary, use transmission line
design techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50
transmis-
sion line is not required on board--a higher characteristic
impedance will help reduce output loading. Use a matching
series resistor at the output of the op amp to drive a
transmission line, and a matched load resistor at the other
end to make the line appear as a resistor. If the 6dB of
attenuation that the matched load produces is not accept-
able, and the line is not too long, use the series resistor at the
source only. This will isolate the source from the reactive load
presented by the line, but the frequency response will be
degraded. Multiple destination devices are best handled as
separate transmission lines, each with its own series source
and shunt load terminations. Any parasitic impedances act-
ing on the terminating resistors will alter the transmission line
match, and can cause unwanted signal reflections and reac-
tive loading.
h) Do not use sockets for high-speed parts like the OPA698.
The additional lead length and pin-to-pin capacitance intro-
duced by the socket creates an extremely troublesome
parasitic network. Best results are obtained by soldering the
part onto the board.
POWER SUPPLIES
The OPA698 is nominally specified for operation using either
5V supplies or a single +5V supply. The maximum specified
total supply voltage of 12V allows reasonable tolerances on
the supplies. Higher supply voltages can break down internal
junctions, possibly leading to catastrophic failure. Single-
supply operation is possible as long as common mode
External
Pin
+V
CC
V
CC
Internal
Circuitry
FIGURE 26. Internal ESD Protection.
voltage constraints are observed. The common-mode input
and output voltage specifications can be interpreted as a
required headroom to the supply voltage. Observing this
input and output headroom requirement will allow design of
non-standard or single-supply operation circuits. Figure 2
shows one approach to single-supply operation.
INPUT AND ESD PROTECTION
ESD damage has been known to damage MOSFET devices,
but any semiconductor device is vulnerable to ESD damage.
This is particularly true for very high-speed, fine geometry
processes. ESD damage can cause subtle changes in ampli-
fier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
ESD handling precautions are required when handling the
OPA698.
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