SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C MARCH 1984 REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
High-Current Outputs Drive up to 15 LSTTL
Loads
D
Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The 'HCT240 devices are organized
as two 4-bit buffers/drivers with separate
output-enable (OE) inputs. When OE is low, the
device passes inverted data from the A inputs to
the Y outputs. When OE is high, the outputs are
in the high-impedance state.
The SN54HCT240 is characterized for operation
over the full military temperature range of 55
C
to 125
C. The SN74HCT240 is characterized for
operation from 40
C to 85
C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
OE
A
Y
L
H
L
L
L
H
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54HCT240 . . . J OR W PACKAGE
SN74HCT240 . . . DW, N, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54HCT240 . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2
2OE
2Y1
GND
2A1
V
CC
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C MARCH 1984 REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
2
1A1
4
1A2
6
1A3
8
1A4
EN
1
1Y1
18
1Y2
16
1Y3
14
1Y4
12
11
2A1
13
2A2
15
2A3
17
2A4
EN
19
2Y1
9
2Y2
7
2Y3
5
2Y4
3
1OE
2OE
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
2
4
6
8
19
11
13
15
17
3
5
7
9
12
14
16
18
1A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
1OE
2OE
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C MARCH 1984 REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT240
SN74HCT240
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0
0.8
0
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
tt
Input transition (rise and fall) time
0
500
0
500
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HCT240
SN74HCT240
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = 20
A
4 5 V
4.4
4.499
4.4
4.4
V
VOH
VI = VIH or VIL
IOH = 6 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI = VIH or VIL
IOL = 20
A
4 5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
VI = VCC or 0
5.5 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0,
VI = VIH or VIL
5.5 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
4.5 V
to 5.5 V
3
10
10
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT240
SN74HCT240
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t d
A
Y
4.5 V
13
25
37
32
ns
tpd
A
Y
5.5 V
12
23
33
29
ns
t
OE
Y
4.5 V
21
35
53
44
ns
ten
OE
Y
5.5 V
19
32
48
40
ns
tdi
OE
Y
4.5 V
19
35
53
44
ns
tdis
OE
Y
5.5 V
18
32
48
40
ns
tt
Y
4.5 V
8
12
18
15
ns
tt
Y
5.5 V
7
11
16
14
ns
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C MARCH 1984 REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT240
SN74HCT240
UNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
t d
A
Y
4.5 V
20
42
63
53
ns
tpd
A
Y
5.5 V
19
38
56
48
ns
t
OE
Y
4.5 V
25
52
79
65
ns
ten
OE
Y
5.5 V
22
47
71
59
ns
tt
Y
4.5 V
17
42
63
53
ns
tt
Y
5.5 V
14
38
57
48
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
40
pF
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C MARCH 1984 REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
CL
tPZH
tpd or tt
tdis
ten
tPZL
tPHZ
tPLZ
1 k
1 k
50 pF
or
150 pF
50 pF
Open
Closed
RL
S1
Closed
Open
S2
Open
Closed
Closed
Open
50 pF
or
150 pF
Open
Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
CL
(see Note A)
Test
Point
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V
1.3 V
0.3 V
0.3 V
2.7 V
2.7 V
3 V
0 V
tr
tf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V
1.3 V
10%
10%
90%
90%
3 V
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
1.3 V
tPLH
tPHL
1.3 V
1.3 V
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL
tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
0 V
1.3 V
1.3 V
tPZH
tPHZ
Output
Waveform 2
(See Note B)
Figure 1. Load Circuit and Voltage Waveforms
PDF 
ZIP