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SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Complementary Outputs
D
Direct Overriding Load (Data) Inputs
D
Gated Clock Inputs
D
Parallel-to-Serial Data Conversion
TYPE
TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL
POWER DISSIPATION
'165
26 MHz
210 mW
'LS165A
35 MHz
90 mW
description
The '165 and 'LS165A are 8-bit serial shift
registers that shift the data in the direction of Q
A
toward Q
H
when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54165, SN54LS165A . . . J OR W PACKAGE
SN74165 . . . N PACKAGE
SN74LS165A . . . D, N, OR NS PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54LS165A . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
SER
CLK INH
H
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Q
H
Q
NC No internal connection
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74LS165AN
SN74LS165AN
0
C to 70
C
SOIC
D
Tube
SN74LS165AD
LS165A
0
C to 70
C
SOIC D
Tape and reel
SN74LS165ADR
LS165A
SOP NS
Tape and reel
SN74LS165ANSR
74LS165A
CDIP
J
Tube
SN54LS165AJ
SN54LS165AJ
55
C to 125
C
CDIP J
Tube
SNJ54LS165AJ
SNJ54LS165AJ
55
C to 125
C
CFP W
Tube
SNJ54LS165AW
SNJ54LS165AW
LCCC FK
Tube
SNJ54LS165AFK
SNJ54LS165AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OUTPUT
SH/LD
CLK INH
CLK
SER
PARALLEL
A . . . H
QA
QB
QH
L
X
X
X
a . . . h
a
b
h
H
L
L
X
X
QA0
QB0
QH0
H
L
H
X
H
QAn
QGn
H
L
L
X
L
QAn
QGn
H
H
X
X
X
QA0
QB0
QH0
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
Req
SH/LD: Req = 3 k
NOM
Other Inputs: Req = 6 k
NOM
TYPICAL OF BOTH OUTPUTS
VCC
Output
'165
100
NOM
EQUIVALENT OF PARALLEL
INPUTS AND SERIAL INPUT
VCC
Input
EQUIVALENT OF ALL
OTHER INPUTS
'LS165A
CLK, CLK INH: Req = 10 k
NOM
SH/LD: Req = 13 k
NOM
TYPICAL OF BOTH OUTPUTS
Output
VCC
120
NOM
24 k
NOM
Req
Input
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
QH
11
12
13
14
3
4
5
6
A
B
C
D
E
F
G
H
Pin numbers shown are for D, J, N, NS, and W packages.
QA
QB
QC
QD
QE
QF
QG
typical shift, load, and inhibit sequences
Serial Shift
Inhibit
Load
E
Output QH
H
G
C
F
Data
Inputs
D
SH/LD
SER
CLK INH
CLK
B
A
Output QH
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.
SN54165, SN54LS165A, SN74165, SN74LS165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SDLS062D OCTOBER 1976 REVISED FEBRUARY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
: SN54165, SN74165
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN54LS165A, SN74LS165A
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interemitter voltage (see Note 2)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance
JA
(see Note 3): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '165 to the SH/LD input in
conjunction with the CLK INH input.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54165
SN74165
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
IOH
High-level output current
800
800
m
A
IOL
Low-level output current
16
16
mA
fclock
Clock frequency
0
20
0
20
MHz
tw(clock)
Width of clock input pulse
25
25
ns
tw(load)
Width of load input pulse
15
15
ns
tsu
Clock-enable setup time (see Figure 1)
30
30
ns
tsu
Parallel input setup time (see Figure 1)
10
10
ns
tsu
Serial input setup time (see Figure 1)
20
20
ns
tsu
Shift setup time (see Figure 1)
45
45
ns
th
Hold time at any input
0
0
ns
TA
Operating free-air temperature
55
125
0
70
C
The SN54165 and SN74165 devices
are obsolete and are no longer supplied.