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FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1A
3Y
2A
GND
V
CC
1Y
3A
2Y
4
3
2
1
5
6
7
8
GND
2A
3Y
1A
2Y
3A
1Y
V
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74LVC3GU04
TRIPLE INVERTER GATE
SCES539A JANUARY 2004 REVISED APRIL 2005
Available in the Texas Instruments
NanoStarTM and NanoFreeTM Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 3.9 ns at 3.3 V
Low Power Consumption, 10-
A Max I
CC
24-mA Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25C
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This triple inverter is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC3GU04 contains three inverters with unbuffered outputs and performs the Boolean function Y = A.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(2)
NanoStarTM WCSP (DSBGA)
SN74LVC3GU04YEPR
0.23-mm Large Bump YEP
Reel of 3000
_ _ _CD_
NanoFreeTM WCSP (DSBGA)
SN74LVC3GU04YZPR
0.23-mm Large Bump YZP (Pb-free)
40C to 85C
SSOP DCT
Reel of 3000
SN74LVC3GU04DCTR
CU4_ _ _
Reel of 3000
SN74LVC3GU04DCUR
VSSOP DCU
CU4_
Reel of 250
SN74LVC3GU04DCUT
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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1A
1Y
1
7
2A
2Y
3
5
3A
3Y
6
2
Absolute Maximum Ratings
(1)
SN74LVC3GU04
TRIPLE INVERTER GATE
SCES539A JANUARY 2004 REVISED APRIL 2005
FUNCTION TABLE
(EACH INVERTER)
INPUT
OUTPUT
A
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
6.5
V
V
I
Input voltage range
(2)
0.5
6.5
V
V
O
Output voltage range
(2) (3)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
50
mA
Continuous current through V
CC
or GND
100
mA
DCT package
220
JA
Package thermal impedance
(4)
DCU package
227
C/W
YEP/YZP package
102
T
stg
Storage temperature range
65
150
C
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of V
CC
is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN74LVC3GU04
TRIPLE INVERTER GATE
SCES539A JANUARY 2004 REVISED APRIL 2005
MIN
MAX
UNIT
V
CC
Supply voltage
1.65
5.5
V
V
IH
High-level input voltage
I
O
= 100
A
0.75 V
CC
V
V
IL
Low-level input voltage
I
O
= 100
A
0.25 V
CC
V
V
I
Input voltage
0
5.5
V
V
O
Output voltage
0
V
CC
V
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OH
High-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
V
CC
= 1.65 V
4
V
CC
= 2.3 V
8
I
OL
Low-level output current
16
mA
V
CC
= 3 V
24
V
CC
= 4.5 V
32
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
(1)
MAX
UNIT
I
OH
= 100 mA
1.65 V to 5.5 V
V
CC
0.1
I
OH
= 4 mA
1.65 V
1.2
I
OH
= 8 mA
2.3 V
1.9
V
OH
V
IL
= 0 V
V
I
OH
= 16 mA
2.4
3 V
I
OH
= 24 mA
2.3
I
OH
= 32 mA
4.5 V
3.8
I
OL
= 100 mA
1.65 V to 5.5 V
0.1
I
OL
= 4 mA
1.65 V
0.45
I
OL
= 8 mA
2.3 V
0.3
V
OL
V
IH
= V
CC
V
I
OL
= 16 mA
0.4
3 V
I
OL
= 24 mA
0.55
I
OL
= 32 mA
4.5 V
0.55
I
I
V
I
= 5.5 V or GND
0 to 5.5 V
5
A
I
CC
V
I
= 5.5 V or GND,
I
O
= 0
1.65 V to 5.5 V
10
A
C
i
V
I
= V
CC
or GND
3.3 V
7
pF
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25C.
3
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Switching Characteristics
Operating Characteristics
SN74LVC3GU04
TRIPLE INVERTER GATE
SCES539A JANUARY 2004 REVISED APRIL 2005
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1
)
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
FROM
TO
0.15 V
0.2 V
0.3 V
0.5 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A
Y
0.2
9.2
0.2
4
0.6
3.9
0.5
3.2
ns
T
A
= 25C
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
C
pd
Power dissipation capacitance
f = 10 MHz
8
8
11
23
pF
4
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PARAMETER MEASUREMENT INFORMATION
V
M
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
R
L
R
L
Data Input
Timing Input
V
I
0 V
V
I
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
I
0 V
Input
Output
Waveform 1
S1 at V
LOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
LOAD
/2
0 V
V
OL
+ V
V
OH
- V
0 V
V
I
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
V
LOAD
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
I
V
M
V
M
1.8 V
0.15 V
2.5 V
0.2 V
3.3 V
0.3 V
5 V
0.5 V
1 k
500
500
500
V
CC
R
L
2
V
CC
2
V
CC
6 V
2
V
CC
V
LOAD
C
L
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
V
CC
V
CC
3 V
V
CC
V
I
V
CC
/2
V
CC
/2
1.5 V
V
CC
/2
V
M
t
r
/t
f
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
SN74LVC3GU04
TRIPLE INVERTER GATE
SCES539A JANUARY 2004 REVISED APRIL 2005
Figure 1. Load Circuit and Voltage Waveforms
5
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