IMPORTANT NOTICE

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TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
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Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

2001, Texas Instruments Incorporated

iii

Contents

Section

Title

Page

Introduction

11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1

Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3

Functional Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4

Terminal Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5

Terminal Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Data Formats

21

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1

Serial Interface Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Digital Output Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

MSB-First, Right-Justified, Serial-Interface Format

. . . . . .

2.2.2

S Serial-Interface Format

. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3

MSB-Left-Justified, Serial-Interface Format

. . . . . . . . . . . . .

2.3

Switching Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Input/Output

31

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1

Analog Input

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Analog Output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1

Direct Analog Output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2

Analog Output With Gain

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3

Reference Voltage Filter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Audio Control/Enhancement Functions

41

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

Soft Volume Update

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

Software Soft Mute

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

Input Mixer Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4

Mono Mixer Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5

Treble Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6

Bass Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7

De-Emphasis Mode (DM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8

Analog Control Register (40h)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9

Dynamic Loudness Contour

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9.1

Loudness Biquads

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9.2

Loudness Gain

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9.3

Loudness Contour Operation

. . . . . . . . . . . . . . . . . . . . . . . . .

4.10

Dynamic Range Compression/Expansion (DRCE)

. . . . . . . . . . . . . . .

4.11

AllPass Function

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12

Main Control Register 1 (01h)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13

Main Control Register 2 (43h)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Filter Processor

51

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1

Biquad Block

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1

Filter Coefficients

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2

Biquad Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Serial Control Interface

61

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1

Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2

C Protocol

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1

Write Cycle Example

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.2

TAS3002 I

C Readback Example

. . . . . . . . . . . . . . . . . . . . .

6.3.3

C Wait States

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4

SMBus Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1

Block Write Protocol

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.2

Write Byte Protocol

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.3

Wait States

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.4

TAS3002 SMBus Readback

. . . . . . . . . . . . . . . . . . . . . . . . . .

Microcontroller Operation

71

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1

General Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2

Power-Up/Power-Down Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1

Power-Up Sequence

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2

Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3

Reset Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.4

Fast Load Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.5

Codec Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3

Power-Down Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1

Power-Down Timing Sequence

. . . . . . . . . . . . . . . . . . . . . . .

7.4

Test Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5

Internal Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6

GPI Terminal Programming

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.1

GPI Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.2

GPI Architecture

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7

External EEPROM Memory Maps

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics

81

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1

Absolute Maximum Ratings Over Operating Temperature Ranges

8.2

Recommended Operating Conditions

. . . . . . . . . . . . . . . . . . . . . . . . . .

8.3

Static Digital Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4

ADC Digital Filter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5

Analog-to-Digital Converter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6

Input Multiplexer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7

DAC Interpolation Filter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.8

Digital-to-Analog Converter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.9

DAC Output Performance Data

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.10

C Serial Port Timing Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . .

System Diagrams

91

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Mechanical Information

101

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Software Interface

A1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1

C Register Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2

Main Control Register Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2.1

Main Control Register 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2.2

Main Control Register 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2.3

Analog Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3

Volume Gain Command

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.4

Treble Control Register Command

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.5

Bass Control Register Command

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.6

C Mixer Register Command

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.7

Programming Instruction for the Loudness Contour

A10

. . . . . . . . . . . . . .

A.8

Examples of Dynamic Range Compression/Expansion (DRCE)

A10

. . . .

A.8.1

DRCE On/Off

A10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.8.2

Above-Threshold Ratios

A11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.8.3

Below-Threshold Ratios

A12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.8.4

Threshold

A13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.8.5

Time Constants

A13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.8.6

DRCE Example With Threshold at 12 dB

A14

. . . . . . . . . . . . .

List of Illustrations

Figure

Title

Page

TAS3002 Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Terminal Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSB-First, Right-Justified, Serial-Interface Format

. . . . . . . . . . . . . . . . . .

S Serial-Interface Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSB-Left-Justified, Serial-Interface Format

. . . . . . . . . . . . . . . . . . . . . . . . .

For Right-/Left-Justified and I

S Serial Protocols

. . . . . . . . . . . . . . . . . . . .

Analog Input to the TAS3002 Device

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCOM Decoupling Network

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Output With External Amplifier

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Reference Voltage Filter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Mixer Function

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

De-Emphasis Mode Frequency Response

. . . . . . . . . . . . . . . . . . . . . . . . .

Dynamic Loudness Contour Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Digital Signal Processing Block Diagram

. . . . . . . . . . . . . . . . . .

Biquad Cascade Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Typical I

C Data Transfer Sequence

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Reset Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power-Down Timing Sequence

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Interface Flow Chart

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Digital Filter Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC Digital Filter Stop-Band Characteristics

. . . . . . . . . . . . . . . . . . . . . . .

ADC Digital Filter Pass-Band Characteristics

. . . . . . . . . . . . . . . . . . . . . . .

ADC High-Pass Filter Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DAC Filter Overall Frequency Characteristics

. . . . . . . . . . . . . . . . . . . . . . .

DAC Digital Filter Pass-Band Ripple Characteristics

. . . . . . . . . . . . . . . . .

C Bus Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stereo Application

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 Device, 2.1 Channels

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS3002 DRCE Characteristics in the dB Domain

A11

. . . . . . . . . . . . . . . . . .

DRCE Example With Threshold at 12 dB

A14

. . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table

Title

Page

TAS3002 Terminal Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Interface Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Control Register Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Control Register 1 Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Control Register 2 Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Protocol Definitions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Address Byte Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Wait States

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPI Terminal Programming

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

512-Byte EEPROM Memory Map 2.0 Channels

. . . . . . . . . . . . . . . . . . . .

512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)

. . . . .

2048-Byte EEPROM Memory Map--2.0 Speakers With
Multiple Equalizations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2048-Byte EEPROM Memory Map--2.1 Speakers With
Multiple Equalizations

710

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Register Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Control Register 1 Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Control Register 2 Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Control Register Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Volume Versus Gain Values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Treble Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bass Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mixer1, Mixer2, and ADC Mixer Gain Values

. . . . . . . . . . . . . . . . . . . . . .

Example of a DRCE I

C Instruction With DRCE On

A10

. . . . . . . . . . . . . . . .

A10

Example of a DRCE I

C Instruction With DRCE Off

A10

. . . . . . . . . . . . . . . .

A11

Above-Threshold Ratios for Compression

A11

. . . . . . . . . . . . . . . . . . . . . . . . .

A12

Above-Threshold Ratios for Expansion

A12

. . . . . . . . . . . . . . . . . . . . . . . . . . .

A13

Below-Threshold Ratios for Expansion

A12

. . . . . . . . . . . . . . . . . . . . . . . . . . .

A14

Below-Threshold Ratios for Compression

A12

. . . . . . . . . . . . . . . . . . . . . . . . .

A15

Threshold Values

A13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A16

Time Constants

A14

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1 Introduction

1.1

Description

The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital
parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides
high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU
through the I

C slave port or from an external EEPROM through the I

C master port.

The TAS3002 device also has an integrated 24-bit stereo codec with two I

C-selectable, single-ended inputs per

channel.

The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad
filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass,
high-pass, and low-pass).

The internal loudness contour algorithm can be controlled and programmed with an I

C command.

Dynamic range compression/expansion (DRCE) is programmable through the I

C port. The system designer can set

the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.

The TAS3002 device supports 13 serial interface formats (I

S, left justified, right justified) with data word lengths of

16, 18, 20, or 24 bits. The sampling frequency (f

) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface

formats are listed and described in Section 2.1.

The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock
for the PLL is provided by an external master clock (MCLK) of 256f

or 512f

, or a 256f

crystal.

The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,
treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal
microcontroller.

1.2

Features

Programmable seven-band parametric equalization

Programmable digital volume control

Programmable digital bass and treble control

Programmable dynamic range compression/expansion (DRCE)

Programmable loudness contour/dynamic bass control

Configurable serial port for audio data

Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of
the codec (analog input). These channels are controlled by I

C commands.

Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume
to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer
channel. The output of the ADC is available for additional processing.

Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation

Serial I

C master/slave port that allows:

Downloading of control data to the device externally from the EEPROM or an I

C master

Controlling other I

C devices

1.4

Terminal Assignments

Figure 12 shows the terminal locations on the package outline, along with the signal name assigned to each
terminal.

14 15

NC
AV

NC
GPI5
GPI4
GPI3
GPI2
GPI1
GPI0
ALLPASS
SDOUT1
SDOUT0

LINA

RFILT

SS(REF)

INPA

RESET

CS1

PWR_DN

TEST

CAP_PLL

CLKSEL

MCLKO

17 18 19 20

AINRM

AINRP

AOUTR

VCOM

47 46 45 44 43

LINB

AINLP

AINLM

40 39 38

21 22 23 24

AOUTL

RINA

RINB

PACKAGE

(TOP VIEW)

ALI/MCLK

ALO

SCL

SDA

LRCLK/O

SCLK/O

IFM/S

SDIN1

SDIN2

SDOUT2

REFM

REFP

Figure 12. TAS3002 Terminal Assignments

1.5

Terminal Functions

Table 11 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type,
and a description of the terminal function.

Table 11. TAS3002 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AINLM

ADC left channel analog input (antialias capacitor)

AINLP

ADC left channel analog input (antialias capacitor)

AINRM

ADC right channel analog input (antialias capacitor)

AINRP

ADC right channel analog input (antialias capacitor)

ALLPASS

Logic high bypasses equalization filters

AOUTL

Left channel analog output

AOUTR

Right channel analog output

AVDD

Analog power supply (3.3 V)

AVSS

Analog voltage ground

AVSS(REF)

Analog ground voltage reference

Table 11. TAS3002 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CAP_PLL

Loop filter for internal phase-locked loop (PLL)

CLKSEL

Logic low selects 256fS; logic high selects 512fS MCLK

CS1

I2C address bit A0; low = 68h, high = 6Ah

DVDD

Digital power supply (3.3 V)

DVSS

Digital ground

GPI0
GPI1
GPI2
GPI3
GPI4
GPI5

28
29
30
31
32
33

Switch input terminals

IFM/S

Digital audio I/O control (low = input; high = output)

INPA

Low when analog input A is selected (will sink 4 mA)

LINA

Left channel analog input 1

LINB

Left channel analog input 2

LRCLK/O

I/O

Left/right clock input/output (output when IFM/S is high)

MCLKO

MCLK output for slave devices

No connection; Can be used as a printed circuit board routing channel

PWR_DN

Logic high places the TAS3002 device in power-down mode

RESET

Logic low resets the TAS3002 device to the initial state

RINA

Right channel analog input 1

RINB

Right channel analog input 2

SCL

I/O

I2C clock connection

SCLK/O

I/O

Shift (bit) clock input (output when IFM/S is high)

SDA

I/O

I2C data connection

SDIN1

Serial data input 1

SDIN2

Serial data input 2

SDOUT0

Serial data output from ADC

SDOUT1

Serial data output (from internal audio processing)

SDOUT2

Serial data output (a monaural mix of left and right, before processing)

TEST

Reserved manufacturing test terminal; connect to DVSS

VCOM

Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-

F and 0.1-

capacitors)

VREFM

ADC minus voltage reference

VREFP

ADC plus voltage reference

VRFILT

Voltage reference low pass filter

XTALI/MCLK

Crystal or external MCLK input

XTALO

Crystal input (crystal is connected between terminals 13 and 14)

2 Audio Data Formats

2.1

Serial Interface Formats

The TAS3002 device works in master or slave mode.

In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be
connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and
20 (SCLK/O) becoming outputs to drive slave devices.

In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options
for selecting the clock rates. If the 512f

MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate

of 512f

must be supplied. If the 256f

MCLK is selected, CLKSEL is tied low and an MCLK of 256f

must be supplied.

In both cases, an LRCLK of 64SCLK must be supplied.

MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I

S, right justified,

and left justified. Table 21 indicates how the 13 options are selected using the I

C bus and the main control register

(MCR, I

C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64f

Additionally, the 16-bit mode operates at 32f

Table 21. Serial Interface Options

MODE

MCR BIT (6)

MCR BIT (54)

MCR BIT (10)

SERIAL INTERFACE

SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0

16-bit, 32fS

16-bit, left justified, 64fS

16-bit, right justified, 64fS

16-bit, I2S, 64fS

18-bit, left justified, 64fS

18-bit, right justified, 64fS

18-bit, I2S, 64fS

20-bit, left justified, 64fS

20-bit, right justified, 64fS

20-bit, I2S, 64fS

24-bit, left justified, 64fS

24-bit, right justified, 64fS

24-bit, I2S, 64fS

Figure 21 through Figure 23 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols.

2.2

Digital Output Modes

The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.

2.2.1

MSB-First, Right-Justified, Serial-Interface Format

The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 21
shows the following characteristics of this protocol:

Left channel is transmitted when LRCLK is high.

The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.

The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.

If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = fS

MSB

LSB

... ...

MSB

LSB

... ...

SDIN

MSB

LSB

... ...

MSB

LSB

... ...

Left Channel

Right Channel

SDOUT

... ...

Figure 21. MSB-First, Right-Justified, Serial-Interface Format

3 Analog Input/Output

The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or
B analog input is accomplished by setting a bit in the analog control register (ACR) by an I

C command. Additionally,

the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).

3.1

Analog Input

Figure 31 shows the technique and components required for analog input to the TAS3002 device. The maximum
input signal must not exceed 0.7 V

rms

. Selection of the above component values gives a frequency response from

20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.

AINRP

AINRM

AINLM

AINLP

24-Bit

Stereo

ADC

RINA

RINB

AINRM

AINRP

AINLM

AINLP

LINA

LINB

Reference

Voltage

1200 pF

0.47

Analog Inputs Use 0.47

F for 20-Hz Cutoff

Anti-Alias Capacitors for fS = 48 kHz

Input Select Command

From Internal Controller

Tie unused analog inputs to analog ground through 0.1-

F capacitors.

Figure 31. Analog Input to the TAS3002 Device

3.2

Analog Output

3.2.1

Direct Analog Output

The full scale analog output from the TAS3002 device is 0.707 V

rms

. It is referenced to VCOM which is approximately

1.5 Vdc. VCOM must be decoupled with the network shown in Figure 32.

AOUTR

24-Bit

DAC

AOUTL

VCOM

0.1

AGND

Analog Output

(Adjust Capacitors for Desired

Low Frequency Response)

Figure 32. VCOM Decoupling Network

3.2.2

Analog Output With Gain

Because the maximum analog output from the TAS3002 device is 0.707 V

rms

, the output level can be increased by

using an external amplifier. The circuit shown in Figure 33 boosts the output level to 1 V

rms

(when it has a gain of

1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is
improved also.

AOUTR

Analog Output

(Adjust Capacitors for Desired

Low Frequency Response)

24-Bit

DAC

AOUTL

VCOM

0.1

AGND

+5 Op Amp/2

TLV2362

or Equilvalent

TLV2362

or Equilvalent

C1 = C2 = C3

C4 = C5

Figure 33. Analog Output With External Amplifier

4 Audio Control/Enhancement Functions

4.1

Soft Volume Update

The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and
pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute).

The volume is adjustable by downloading a gain coefficient through the I

C interface in 4.16 format--4 bits for the

integer and 16 bits for the fractional part. Table A5 lists the 4.16 coefficients converted into dB for the range of 70
dB to 18 dB with 0.5-dB step resolution.

Right and left channel volumes can be unganged and set to different values. This feature implements a balance
control.

Volume is changed by writing the desired value into the volume control registers. This is done by asserting the
volume-up or volume-down GPI terminal (see Section 7.6.1) for a limited range of volume control. Alternatively,
volume control settings can be sent to the TAS3002 device over the I

C bus.

4.2

Software Soft Mute

Soft mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down
over a duration of 2048f

samples to a final output of 0 ( infinity dB).

Soft mute can be enabled by either asserting the mute GPI terminal (see Section 7.6.1) or sending a mute command
over the I

C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on.

4.3

Input Mixer Control

The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of
serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading
values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers. See
Figure 41 for a functional block diagram of the input mixer.

The values loaded into these registers are in 4.20 format--4 bits for the integer and 20 bits for the fractional part.
Table A8 lists the 4.20 numbers converted into dB for the range of 70 dB to 18 dB, although any positive 4.20
number may be used.

To mute any of the channels, 0s are loaded into the respective mixer control register.

Mixer controls are updated instantly and can cause audible artifacts for large changes in setting when updated
dynamically outside of the fast load mode; therefore, it is desirable to use fast load in conjunction with the soft-volume
mode.

SDIN1, SDIN2, and the ADC output can be mixed with a user-selectable gain for each channel. The gain control
registers are represented in 4.20 format.

SDIN2_L

7 Biquad

Filters

Tone

Soft

Volume

DRCE

SDIN1_L

ADC_L

SDOUT1

7 Biquad

Filters

Tone

Soft

Volume

DRCE

SDIN2_R

SDIN1_R

ADC_R

SDOUT2

1/2

L + R_SUM

Right Channel Mix Coefficients
I2C Register Address 07h

SDIN1 ^ SDIN2 ^ ADC

= (3) 24-Bit Right Mix Coefficient

Left Channel Mix Coefficients
I2C Register Address 08h

= (3) 24-Bit Left Mix Coefficient

SDIN1 ^ SDIN2 ^ ADC

1/2

L_SUM

R_SUM

Figure 41. TAS3002 Mixer Function

4.4

Mono Mixer Control

The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio
data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of 6 dB so that full scale
inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.

The output of this mixer is present on terminal 24 (SDOUT2) and is generally used for a digitally-mixed subwoofer
or center channel application.

4.5

Treble Control

The treble gain level may be adjusted within the range of 15 dB to 15 dB with 0.5-dB step resolution. The level
changes are accomplished by downloading treble codes (shown in Table A6) into the treble gain register.
Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see
Section 7.6.1).

The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate.

The gain values for treble control can be found in Section A.4.

4.6

Bass Control

The bass gain level can be adjusted within the range of 15 dB to 15 dB with 0.5-dB step resolution. The level changes
are accomplished by downloading bass codes (shown in Table A7) into the bass frequency control register.
Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see
Section 7.6.1).

Bass control is a shelf filter with a corner frequency of 250 Hz at a 48-kHz sample rate.

The gain values for bass control can be found in Section A.5.

4.7

De-Emphasis Mode (DM)

De-emphasis is implemented in the DAC and is software controlled. De-emphasis is valid at 44.1 kHz and 48 kHz.

To enable de-emphasis, values are written into the analog control register via the I

C command. See Section 4.8 for

analog control register operation.

Figure 42 illustrates the frequency response of the de-emphasis mode.

Response (dB)

3.18

(50

10.6

(15

Frequency (kHz)

De-Emphasis

Figure 42. De-Emphasis Mode Frequency Response

4.8

Analog Control Register (40h)

The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC,
and analog power down.

An I

C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h.

Bit

Type

R/W

Default

Table 41. Analog Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved

R/W

Reset to 0

Reserved

R/W

Reset to 0

Reserved

R/W

Reserved. Bits 5 and 4 return 0s when read.

DM(10)

R/W

De-emphasis control

00 = De-emphasis off (initial condition after reset)
01 = 48 kHz sample rate de-emphasis selected
10 = 44.1 kHz sample rate de-emphasis selected
11 = Reserved

INP

R/W

Analog input select

0 = LINA and RINA selected (initial condition after reset)
1 = LINB and RINB selected

APD

R/W

Analog power down

0 = Normal operation (initial condition after reset)
1 = Power down

4.9

Dynamic Loudness Contour

The necessity for applying loudness compensation to playback systems to compensate for the fact that the ear
perceives bass and treble less audibly at low levels than at high ones has been established since the first data was
published by Fletcher and Munson in 1933.

There are many equal-loudness contours in publication, like Steven's contours, Robinson and Dadson contours.
Some have even reached the acceptance level of ISO recommendation.

The TAS3002 device has a simplified loudness contour algorithm that diminishes the effect of weak bass at low
listening levels. Since contour has volume level dependency, the user must define the relation between the gain of
the contour circuit and the volume level.

Figure 43 is a block diagram of this circuit.

Volume

Biquad

Gain

Figure 43. Dynamic Loudness Contour Block Diagram

The loudness contour is activated by sending an activation command via I

C from an external device. Optionally, a

contour gain command can be sent by an external device to provide tracking with the system volume control.

4.9.1

Loudness Biquads

Loudness biquad filters for the left and right channels are independently programmable via I

C. Their subaddresses

are 21h and 22h, respectively. The digital filters are written as five 24-bit (4.20) hex coefficients for each channel.

4.9.2

Loudness Gain

Loudness gain values for the left and right channels are independently programmable via I

C. Their subaddresses

are 23h and 24h, respectively. The gain values are written as one 4.20 hex coefficient for each channel.

4.9.3

Loudness Contour Operation

When the frequency of the loudness contour is determined, a digital filter must be developed. Then, the gain of the
filter is determined. These values are placed in the storage area of the system controller (microcontroller) and sent
to the TAS3002 device when it is desired to activate the loudness contour.

If it is necessary to change the frequency or gain of the contour, new gain and filter coefficients are sent by the system
controller. This function is performed normally when the volume control is changed (that is, more volume, less
contour). The gain of the loudness contour filter then tracks the volume control.

The loudness contour biquad filters are provided in addition to the seven equalization biquad filters.

See Section A.7 for programming instructions.

4.10 Dynamic Range Compression/Expansion (DRCE)

The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE
receives data, and affects scaling after the volume/loudness block. As shown in Figure 44, the DRCE is applied after
the volume/loudness control block as a DRCE scale factor. The DRCE must be adjusted such that the signal does
not reach the hard limit value. However, if the signal does reach the maximum digital value, the saturation logic serves
as a hard limiter that does not allow the signal to extend beyond the available range.

SDIN2_L

(7)

2nd Order

IIR Filters

Bass/

Treble

Soft

Volume/

LEFT_OUT

Loudness

(Parametric

Equalization)

(Tone)

LEFT_SUM

SDIN1_L

(Left Channel Mixer)

ANALOGIN_L

(DRCE Scaling)

Saturation

Logic

Dynamic

Range

Control

(Analog in From ADC)

SDIN2_R

(7)

2nd Order

IIR Filters

Bass/

Treble

Soft

Volume/

RIGHT_OUT

Loudness

(Parametric

Equalization)

(Tone)

RIGHT_SUM

SDIN1_R

(Right Channel Mixer)

ANALOGIN_R

(DRCE Scaling)

Saturation

Logic

Figure 44. TAS3002 Digital Signal Processing Block Diagram

The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code
of Table A9. Each instruction downloaded must be eight bytes. If only one byte is changed, all eight bytes must be
transmitted. The first two bytes remain the same for every instruction, however the last six bytes can be programmed
using hexadecimal values from the corresponding tables referred to in Section A.8.

With high compression ratios and fast attack times available, this function is suited for a commercial killer in a
television set application.

4.11 AllPass Function

This function is enabled by setting terminal 27 (ALLPASS) on the TAS3002 device to 1. When asserted, the internal
equalization filters are set into AllPass (flat) mode. When this terminal is reset to 0, the equalization filters are returned
to the equalization that was in use before the terminal was asserted.

In AllPass mode, the bass and treble controls are still functional.

This function is frequently used for headphones. When the headphone plug is inserted into its jack, a switched contact
in the jack enables the AllPass function.

The AllPass function also can be activated by writing a 1 to bit 2 of the analog control register.

4.12 Main Control Register 1 (01h)

The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2
(MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and
serial-port word length. It is accessed via I

C with the address 01h.

MCR1 (01h)

Bit

Type

R/W

Default

Table 42. Main Control Register 1 Description

BIT

FIELD NAME

TYPE

DESCRIPTION

R/W

Fast load

0 = Normal operation mode
1 = Fast -load mode (default)

R/W

SCLK frequency

0 = SCLK is 32 fS

1 = SCLK is 64 fS.

R/W

Serial port mode

00 = Left justified
01 = Right justified
10 = I2S
11 = Reserved

Reserved

R/W

Serial port word length

00 = 16-bit
01 = 18-bit
10 = 20-bit
11 = 24-bit

4.13 Main Control Register 2 (43h)

The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2
(MCR2). The MCR2 register contains the bits associated with the AllPass function and the download of bass and
treble control information, and it is accessed via I

C with the address 43h.

MCR2 (43h)

Bit

Type

R/W

Default

Table 43. Main Control Register 2 Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved

R/W

0 = Normal operation (initial condition after reset)
1 = Download bass and treble

Reserved

Reserved. Bits 6 and 5 return 0s when read.

Reserved

Undefined.

DM(10)

R/W

0 = Normal operation (initial condition after reset)
1 = AllPass mode (bass and treble are still functional)

INP

Reserved. Bit 0 returns 0 when read.

5 Filter Processor

5.1

Biquad Block

The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in
Figure 51. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has
independent coefficients.

Biquad 1 ...

Biquad 0

Biquad 6

Figure 51. Biquad Cascade Configuration

5.1.1

Filter Coefficients

The filter coefficients for the TAS3002 device are downloaded through the I

C port and loaded into the biquad memory

space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is
processed by the biquad block and then converted into analog waveforms by the DAC. Alternatively, filters can be
loaded by asserting terminals on the GPI port.

5.1.2

Biquad Structure

The biquad structure that is used for the parametric equalization filters is as follows:

H(z)

)

NOTE: a

is fixed at value 1 and is not downloadable.

The coefficients for these filters are represented in 4.20 format--4 bits for the integer part and 20 bits for the fractional
part. In order to transmit them over I

C, it is necessary to separate each coefficient into three bytes. The upper 4 bits

of byte 2 comprise the integer part; the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part.

The filters can be designed using the automatic loudspeaker equalization program (ALE) or a script running under
MatLab named Filtermaker. Both of these tools are available from Texas Instruments.

(1)

6 I

C Serial Control Interface

6.1

Introduction

Control parameters for the TAS3002 device can be loaded from an I

C serial EEPROM by using the TAS3002 master

interface mode. If no EEPROM is found, the TAS3002 device becomes a slave device and loads from another I

master interface. Information loaded into the TAS3002 registers is defined in Appendix A.

The I

C bus uses terminals 16 (SDA for data) and 15 (SCL for clock) to communicate between integrated circuits in

a system. These devices can be addressed by sending a unique 7-bit slave address plus R/W bit (1 byte). All
compatible devices share the same terminals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used to set the high level on the bus. The TAS3002 device operates in standard mode up to
100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF.

Furthermore, the TAS3002 device supports a subset of the SMBus protocol. When it is attached to the SMBus, then
byte, word, and block transfers are supported. The SMBus NAK function is not supported and care must be taken
with the sequence of the instructions sent to the TAS3002 device.

Additionally, the TAS3002 device operates in either master or slave mode; therefore, at least one device connected
to the I

C bus must operate in master mode.

6.2

C Protocol

The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low
transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur
within the low time of the clock period. Figure 61 shows these conditions. These start and stop conditions for the
I

C bus are required by standard protocol to be generated by the master. The master must also generate the 7-bit

slave address and the read/write (R/W) bit to open communication with another device and then wait for an
acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an acknowledgment.
When this occurs, the master transmits the next byte of the sequence.

After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the
number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master
generates a stop condition to release the bus. Figure 61 shows a generic data transfer sequence.

8-Bit Register Data

for Address (N+2)

SCL

SDA

Start

8-Bit Register Data

for Address (N+1)

8-Bit Register Data

for Address (N)

7-Bit

Slave Address

R/
W

Stop

Figure 61. Typical I

C Data Transfer Sequence

Table 61 lists the definitions used by the I

C protocol.

Table 61. I

C Protocol Definitions

DEFINITION

DESCRIPTION

Transmitter

The device that sends data

Receiver

The device that receives data

Master

The device that initiates a transfer, generates clock signals, and terminates the transfer

Slave

The device addressed by the master

Multimaster

More than one master can attempt to control the bus at the same time without corrupting the message.

Arbitration

Procedure to ensure the message is not corrupted when two masters attempt to control the bus.

Synchronization

Procedure to synchronize the clock signals of two or more devices

6.3

Operation

The 7-bit address for the TAS3002 device is 0110 10X R/W where X is a programmable address bit, set by terminal 7
(CS1). Combining CS1 and the R/W bit, the TAS3002 device can respond to four different I

C addresses (two read

and two write). These two addresses are licensed I

C addresses that do not conflict with other licensed I

C audio

devices. In addition to the 7-bit device address, subaddresses direct communication to the proper memory location
within the device. A complete table of subaddresses and control registers is provided in Appendix A. For example,
to change bass to 10-dB gain, Section 6.3.1 shows the data that is written to the I

C port:

Table 62. I

C Address Byte Table

I2C ADDRESS BYTE

A6A1

CS1 (A0)

R/W

68h

011010

69h

011010

6Ah

011010

6Bh

011010

6.3.1

Write Cycle Example

Start

Slave Address

R/W

Subaddress

Data

Stop

FUNCTION

DESCRIPTION

Start

Start condition as defined in I2C

Slave address

0110100 (CS1 = 0)

R/W

0 (write)

Acknowledgement as defined in I2C (slave)

Subaddress (treble control register)

0000 0101

Data (0 dB gain)

0111 0010

Stop

Stop condition as defined in I2C

NOTE: Table is for serial data (SDA); serial clock (SCL) is not shown but conditions apply as well.

Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle.
For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow; otherwise,
the cycle is incomplete and errors occur.

6.3.2

TAS3002 I

C Readback Example

The TAS3002 saves in a stack or first-in first-out (FIFO) buffer the last 7 bytes that were sent to it. When an I

C read

command is sent to the device (LSB=high), it answers by popping the first byte off the stack. The TAS3002 then
expects either a Send Ack command or an I

C Stop command from the host. If a Send Ack command is sent from

the host then the TAS3002 pops another byte off the stack. If an I

C Stop is sent then the TAS3002 ends this

transaction. The proper sequence for reading is described as follows:

I2C Start

Send I2C address byte with read bit set to 1 (LSB set equal to 1)

Receive Byte 0

Send Ack

Receive Byte 1

Send Ack

Receive Byte 2

Send Ack

Receive Byte 3

Send Ack

Receive Byte 4

Send Ack

Receive Byte 5

Send Ack

Receive Byte 6 (if an ACK is sent after byte 6 it locks up the TAS3002)

I2C Stop

Where:

C Start is a valid I

C Start command.

Receive Byte is a valid I

C command which reads a byte from the TAS3002.

Send Ack is a a valid I

C command that informs the TAS3002 that a byte has been read.

C Stop is a valid I

C Stop command.

NOTES:

1. The TAS3002 will appear to be locked up, if a Send Ack is issued after the last byte read. It is required to send an I2C Stop command

after the last byte and not a Send Ack.

2. The I2C Start and I2C Stop commands are the same for both I2C read and I2C write.

6.3.3

C Wait States

The TAS3002 device performs interpolation algorithms for its volume and tone controls. If a volume or tone change
is sent to the part via I

C, the command sent after the volume or tone (bass and treble) change causes an I

C wait

state to occur. This wait state lasts from 41 ms to 231 ms, depending on the system clock rate, the command sent,
and, in the case of bass or treble, the amount of the change.

Secondly, if a long series of commands is sent to the TAS3002 device, it may occasionally create a short wait state
on the order of 150

s to 300

s while it loads and processes the commands.

When a sample rate of 32 kHz is used, longer wait states can occur, occasionally up to 15 ms.

The preferred way to take care of wait states is to use an I

C controller that recognizes wait states. During the wait

state period, it stops sending data over I

C. If this function is not available on the system controller, fixed delays can

be implemented in the system software to ensure that the controller is not trying to send more data while the TAS3002
device is busy. Sending I

C data while the TAS3002 device is busy causes errors and locks up the device, which must

then be reset.

Table 63 gives typical values of the wait states that can be expected with the various functions of the part:

Table 63. I

C Wait States

SYSTEM SAMPLING FREQUENCY

32 kHz

44.1 kHz

48 kHz

Comment

Volume

62 ms

49 ms

41 ms

Not dependent on size of change

Bass

231 ms

167 ms

153 ms

0 to 18 dB

Treble

231 ms

167 ms

153 ms

0 to 18 dB

DRC on

300

Mixer

None

Loudness

None

Equalization

15 ms

190

300

Can occur with each filter

6.4

SMBus Operation

The TAS3002 device supports a subset of the SMBus protocol. With proper programming techniques, it is possible
to use the SMBus to set up the TAS3002 device.

6.4.1

Block Write Protocol

The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a
command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the
subaddress (also with MSB set high) must be programmed into the SMBus command byte. This operation signals
the TAS3002 device that the next byte is the SMBus byte-count byte. The next byte after the byte count is then entered
into the device as the first byte of data.

SMBus

Command Byte

68h

8rh

TAS3002

Address

Subaddress

(r = subaddress)

Byte Count

(Don't Care)

Data

6.4.2

Write Byte Protocol

The TAS3002 device also supports the SMBus write byte protocol. Writing to the main control register (MCR), bass,
and treble registers requires using the byte write protocol. To send a command using this protocol, the most significant
bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be
programmed into the SMBus command byte. The next byte after the command byte is then entered into the device
as the first byte of data.

SMBus

Command Byte

68h

8rh

TAS3002

Address

Subaddress

(r = subaddress)

Data

6.4.3

Wait States

If separate I

C/SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This

happens when the device is busy while performing smoothing operations and changing volume, bass, and treble.
The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed
according to the SMBus specification (worst case 200 ms).

The following is a possible bus wait state scenario:

CODE

Start

Stop

ACTUAL

Start

Wait

Stop

If the master does not recognize bus waiting or if the master times out on a long wait, the master must not send consecutive I2C/SMBus commands

without a time interval of 200 ms between transactions.

6.4.4

TAS3002 SMBus Readback

The TAS3002 device supports a subset of SMBus readback. When an SMBus read command is sent to the device
(LSB = high), it answers with the subaddress and the last six bytes written.

SMBus

Command

Byte

Count

SENT

Start

69h

xxh

07h

Stop

RECEIVED

Start

07h

aah

ddh

Stop

Byte

Count

Where:

xxh

= Command byte. It is a don't care because the response contains only the subaddress and the

last six bytes of data written to the TAS3002 device.

aah

= The last subaddress accessed in the device

ddh

= Data bytes from the TAS3002 device

NOTE: Use read sequence defined in 6.3.2

7 Microcontroller Operation

The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform
housekeeping and interface functions. Additionally, it handles I

C communication and general purpose input

functions.

7.1

General Description

The microcontroller uses a 256f

system clock and can access up to 8K bytes of memory. It interfaces with the digital

audio interface I

C master/slave for downloading data and coefficients. It also interfaces with two internal DSPs for

transferring coefficients and other information.

The TAS3002 coefficients are loaded through I

C in the master or slave mode. Standard audio processing functions

(volume, bass, and treble) can be controlled/activated through external switches connected to the six GPI terminals.
Upon reset, the internal microcontroller sets all coefficients and audio parameters to the default values. See
Section 7.2.2 for default values.

If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters
and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default
condition. If addresses other than 68h/69h are set, the TAS3002 device only operates as an I

C slave device.

If the microcontroller determines the TAS3002 device has an I

C address of 68h/69h and the EEPROM is present,

the microcontroller downloads coefficients from the EEPROM. Once the download is complete, it enables the serial
audio in the mode defined by an I

C write to the MCR to transfer data into and out of the device. Before reading the

EEPROM, the serial audio port defaults to I

S mode.

The TAS3002 device allows the user to update volume, bass, and treble dynamically by an I

C slave command or

by a simple GPI input. The GPI can select volume up and down, bass/treble up and down, or digital equalizations.
Up to five different equalizations (that is, flat, jazz, rock, voice, etc.) can be stored in the external EEPROM. Also,
DRCE, MCR1, MCR2, and loudness contour are enabled and disabled by I

When the TAS3002 device operates in the I

C master mode, it echoes changes to all of its functions to other I

addresses that are defined in its external EEPROM. If no addresses are defined, it does not echo.

7.2

Power-Up/Power-Down Reset

7.2.1

Power-Up Sequence

An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET
synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 71. On reset,
SCL and SDA go to a high-impedance state. If the I

C address is set to 68h, approximately 400

s after RESET

returns to a 1, the device sends a one-byte query via I

C to look for an EEPROM. If an EEPROM is found, the TAS3002

becomes an I

C master; otherwise, it becomes an I

C slave. When using address 68h in the slave mode, an external

master must wait until after the EEPROM query or else bus contention and improper operation occur.

C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.

7.2.2

Reset

The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks
used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the
following process:

Clears all the RAM memory content

Clears all the registers in the circuits

Purges the codec

Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low

Initializes the equalization parameters to AllPass filters

Sets the digital audio interface to the I

S 18-bit mode

Sets the bass/treble to 0 dB

Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in

Sets the volume to 40 dB

Turns off all enhancement features (DRCE, etc.)

Reads the I

C address. If the address is 68h, the device reads its EEPROM. It is possible to load the

user-defined bass/treble data and break points (optional). If there is no data, the device loads default
bass/treble delta and break points from ROM.

If the address is 6Ah, the device puts the I

C interface in slave mode and waits for input.

7.2.3

Reset Circuit

Because the TAS3002 device has an internal power-on reset (POR), in many cases, additional components are not
needed to reset the device. It resets internally at approximately 80% of V

In the case where the system power supplies are slow in reaching their final voltage or where there is a difference
in the time the system power supplies take to become stable, the TAS3002 reset can be delayed by a simple RC
circuit.

0.1

DVDD

TAS3002

RESET

10 k

DVSS

Figure 71. TAS3002 Reset Circuit

The reset delay for the above circuit can be calculated by the simple equation:

= 0.8RC + 400

Where:

= The delay before the TAS3002 device comes out of reset

C = Value of the capacitance from RESET (pin 6) to DV

R = Value of the resistance from RESET (pin 6) to DV

The circuit described in Figure 71 delays the start-up of the TAS3002 device approximately 1.2 ms.

When it is necessary to control the reset of the TAS3002 device with an external device, such as a microcontroller,
RESET (pin 6) can be treated as a logic signal. It then brings the device out of reset when the voltage on RESET
reaches V

/2.

7.2.4

Fast Load Mode

While in fast load mode--FL bit (bit 7 of main control register 1) = 0--it is possible to update the parametric
equalization without any audio processing delay. The audio processor pauses while the RAM is updated in this mode.

Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normal
mode (FL bit = 0).

Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1
(MCR1). This puts the TAS3002 device into normal mode.

7.2.5

Codec Reset

During initialization, the output of the codec is disabled. Throughout reset and initialization, the output of the DAC is
muted to prevent extraneous noise being sent to the system output.

Data from the ADC and other internal processing is purged so that when reset/initialization is complete, only valid
inputs are sent to the system output.

7.3

Power-Down Mode

The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control
registers and equalization programming of the device are stored in the device.

To enter power-down mode:

Assert the power-down control signal (1)

Set the serial audio input clocks to 0

The TAS3002 device goes into power-down mode.

To exit the power-down mode:

Assert RESET (logic 0)

Restart the serial audio clocks

Wait for a delay of 1.0 ms (to allow the PLL to lock)

Negate the power-down control signal (logic 0)

Negate RESET (logic 1)

The device then returns to the state it was in before power down (resumes normal operation).

Table 71. GPI Terminal Programming

GPI5

GPI4

GPI3

GPI2

GPI1

GPI0

VOL_UP, +1 dB

VOL_DN, 1 dB

BASS_UP, +1 dB

BASS_DN, 1 dB

TREB_UP, +1 dB

TREB_DN, 1 dB

Shift 1

Mute

EQ1

EQ2

EQ3

EQ4

EQ5

Shift 2

NOTE: x = Logic low

Initially (after reset), the TAS3002 GPI is set to control volume, bass, and treble. Simultaneously setting GPI bits 1
and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization.

To return to volume, bass, and treble control, simultaneously set GPI terminals 2 and 3 low for 1 second.

When a GPI terminal is activated, the TAS3002 device echoes its function over I

C to a TAS3001 device mapped

to address 6Ah. Therefore, a system with two audio equalization chips can be implemented without the need for a
microcontroller.

7.6.2

GPI Architecture

The GPI provides simple but flexible input port to activate the input parameters. Each terminal input is an active logic
low.

7.7

External EEPROM Memory Maps

Table 72 through Table 75 show the 512-byte and 2048-byte EEPROM memory maps.

Table 72. 512-Byte EEPROM Memory Map 2.0 Channels

ADDRESS

BYTE NUMBER

FUNCTION

000h

Signature (2Ah)

001h

ID byte = 0000 0000

002h

MCR

003h00Bh

Mixer left gain

00Ch014h

Mixer right gain

015h01Ah

DRC (ratio, threshold, energy

, attack

, decay

)

01Bh

Bass

01Ch

Treble

01Dh022h

Volume

031h03Fh

Biquad 0

040h04Eh

Biquad 1

04Fh05Dh

Biquad 2

05Eh06Ch

Biquad 3

Left channel

06Dh07Bh

Biquad 4

Left channel

07Ch08Ah

Biquad 5

08Bh099h

Biquad 6

09Ah

0 dB/bass

09Bh

0 dB/treble

09Ch0A1h

Bass break

0A2h0A7h

Treble break

0A8h110h

105

Bass delta

111h179h

105

Treble delta

17Ah17Fh

Bass set point

180h185h

Treble set point

186h194h

Biquad 0

195h1A3h

Biquad 1

1A4h1B2h

Biquad 2

1B3h1C1h

Biquad 3

Right channel

1C2h1D0h

Biquad 4

Right channel

1D1h1DFh

Biquad 5

1E0h1EEh

Biquad 6

NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

Table 73. 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)

ADDRESS

BYTE NUMBER

FUNCTION

000h

Signature (2Ah)

001h

ID byte = 0000 0011

TAS3002

002h

MCR

003h00Bh

Mixer left gain

00Ch014h

Mixer right gain

015h01Ah

DRC (ratio, threshold, energy

, attack

, decay

)

01Bh

Bass

01Ch

Treble

01Dh022h

Volume

031h03Fh

Biquad 0

040h04Eh

Biquad 1

04Fh05Dh

Biquad 2

TAS3002

05Eh06Ch

Biquad 3

TAS3002

right and left

06Dh07Bh

Biquad 4

right and left

channel

07Ch08Ah

Biquad 5

08Bh099h

Biquad 6

09Ah

0 dB/bass

09Bh

0 dB/treble

09Ch0A1h

Bass break

0A2h0A7h

Treble break

0A8h110h

105

Bass delta

111h179h

105

Treble delta

17Ah17Fh

Bass set point

180h185h

Treble set point

186h194h

Biquad 0

195h1A3h

Biquad 1

1A4h1B2h

Biquad 2

TAS3001

1B3h1C1h

Biquad 3

TAS3001

right and left

1C2h1D0h

Biquad 4

right and left

channel

1D1h1DFh

Biquad 5

1E0h1EEh

Biquad 6

TAS3001

1EFh

MCR

1F0h1F2h

SDIN1 gain

1F3h1F5h

SDIN2 gain

1F6h1F7h

DRC (ratio, threshold, energy

, attack

, decay

)

1F8h

Bass

1F9h

Treble

1FAh1FFh

Volume

NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels.

Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

Table 74. 2048-Byte EEPROM Memory Map--2.0 Speakers With Multiple Equalizations

TAS3002 ADDRESS

LEFT BIQUAD

NUMBER

OF BYTES

FUNCTION

CATEGORY

TAS3002 ADDRESS

RIGHT BIQUAD

TAS3001

000h

Signature (2Ah)

001h

002h

MCR

1EFh

003h00Bh

9/3

Mixer left gain

1F0h1F2h

00Ch014h

9/3

Mixer right gain

1F3h1F5h

015h019h

6/2

DRC (ratio, threshold, energy

, attack

, decay

)

1F6h1F7h

01Ah

Bass

1F8h

01Bh

Treble

1F9h

01Ch021h

Volume

1FAh1FFh

031h03Fh

Biquad 0

3A4h3B2h

186h194h

040h04Eh

Biquad 1

3B3h3C1h

195h1A3h

04Fh05Dh

Biquad 2

3C2h3D0h

1A4h1B2h

05Eh06Ch

Biquad 3

Set 0

3D1h3DFh

1B3h1C1h

06Dh07Bh

Biquad 4

Set 0

3E0h3EEh

1C2h1D0h

07Ch08Ah

Biquad 5

3EFh3FDh

1D1h1DFh

08Bh099h

Biquad 6

3FEh40Ch

1E0h1EEh

09Ah185h

236

Bass treble table

200h20Eh

Biquad 0

40Dh41Bh

5B1h5BFh

20Fh21Dh

Biquad 1

41Ch42Ah

5C0h5CEh

21Eh22Ch

Biquad 2

42Bh439h

5CFh5DDh

22Dh23Bh

Biquad 3

Set 1

43Ah448h

5DEh5ECh

23Ch24Ah

Biquad 4

Set 1

449h457h

5EDh5FBh

24Bh259h

Biquad 5

458h466h

5FCh60Ah

25Ah268h

Biquad 6

467h475h

60Bh619h

269h277h

Biquad 0

476h484h

61Ah628h

278h286h

Biquad 1

485h493h

629h637h

287h295h

Biquad 2

494h4A2h

638h646h

296h2A4h

Biquad 3

Set 2

4A3h4B1h

647h655h

2A5h2B3h

Biquad 4

Set 2

4B2h4C0h

656h664h

2B4h2C2h

Biquad 5

4C1h4CFh

665h673h

2C3h2D1h

Biquad 6

4D0h4DEh

674h682h

2D2h2E0h

Biquad 0

4DFh4EDh

683h691h

2E1h2EFh

Biquad 1

4EEh4FCh

692h6A0h

2F0h2FEh

Biquad 2

4FDh50Bh

6A1h6AFh

2FFh30Dh

Biquad 3

Set 3

50Ch51Ah

6B0h6BEh

30Eh31Ch

Biquad 4

Set 3

51Bh529h

6BFh6CDh

31Dh32Bh

Biquad 5

52Ah538h

6CEh6DCh

32Ch33Ah

Biquad 6

539h547h

6DDh6EBh

33Bh349h

Biquad 0

548h556h

6ECh6FAh

34Ah358h

Biquad 1

557h565h

6FBh709h

359h367h

Biquad 2

566h574h

70Ah718h

368h376h

Biquad 3

Set 4

575h583h

719h727h

377h385h

Biquad 4

Set 4

584h592h

728h736h

386h394h

Biquad 5

593h5A1h

737h745h

395h3A3h

Biquad 6

5A2h5B0h

746h754h

NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

710

Table 75. 2048-Byte EEPROM Memory Map--2.1 Speakers With Multiple Equalizations

TAS3002 ADDRESS

NUMBER

OF BYTES

FUNCTION

CATEGORY

TAS3001 ADDRESS

LEFT CHANNEL

TAS3001 ADDRESS

RIGHT CHANNEL

000h

Signature (2Ah)

001h

002h

MCR

1EFh

003h00Bh

9/3

Mixer left gain

1F0h1F2h

00Ch014h

9/3

Mixer right gain

1F3h1F5h

015h019h

6/2

DRC (ratio, threshold, energy

, attack

, decay

)

1F6h1F7h

01Ah

Bass

1F8h

01Bh

Treble

1F9h

01Ch021h

Volume

1FAh1FFh

031h03Fh

Biquad 0

186h194h

3A4h3B2h

040h04Eh

Biquad 1

195h1A3h

3B3h3C1h

04Fh05Dh

Biquad 2

1A4h1B2h

3C2h3D0h

05Eh06Ch

Biquad 3

Set 0

1B3h1C1h

3D1h3DFh

06Dh07Bh

Biquad 4

Set 0

1C2h1D0h

3E0h3EEh

07Ch08Ah

Biquad 5

1D1h1DFh

3EFh3FDh

08Bh099h

Biquad 6

1E0h1EEh

3FEh40Ch

09Ah185h

236

Bass treble table

200h20Eh

Biquad 0

5B1h5BFh

40Dh41Bh

20Fh21Dh

Biquad 1

5C0h5CEh

41Ch42Ah

21Eh22Ch

Biquad 2

5CFh5DDh

42Bh439h

22Dh23Bh

Biquad 3

Set 1

5DEh5ECh

43Ah448h

23Ch24Ah

Biquad 4

Set 1

5EDh5FBh

449h457h

24Bh259h

Biquad 5

5FCh60Ah

458h466h

25Ah268h

Biquad 6

60Bh619h

467h475h

269h277h

Biquad 0

61Ah628h

476h484h

278h286h

Biquad 1

629h637h

485h493h

287h295h

Biquad 2

638h646h

494h4A2h

296h2A4h

Biquad 3

Set 2

647h655h

4A3h4B1h

2A5h2B3h

Biquad 4

Set 2

656h664h

4B2h4C0h

2B4h2C2h

Biquad 5

665h673h

4C1h4CFh

2C3h2D1h

Biquad 6

674h682h

4D0h4DEh

2D2h2E0h

Biquad 0

683h691h

4DFh4EDh

2E1h2EFh

Biquad 1

692h6A0h

4EEh4FCh

2F0h2FEh

Biquad 2

6A1h6AFh

4FDh50Bh

2FFh30Dh

Biquad 3

Set 3

6B0h6BEh

50Ch51Ah

30Eh31Ch

Biquad 4

Set 3

6BFh6CDh

51Bh529h

31Dh32Bh

Biquad 5

6CEh6DCh

52Ah538h

32Ch33Ah

Biquad 6

6DDh6EBh

539h547h

33Bh349h

Biquad 0

6ECh6FAh

548h556h

34Ah358h

Biquad 1

6FBh709h

557h565h

359h367h

Biquad 2

70Ah718h

566h574h

368h376h

Biquad 3

Set 4

719h727h

575h583h

377h385h

Biquad 4

Set 4

728h736h

584h592h

386h394h

Biquad 5

737h745h

593h5A1h

395h3A3h

Biquad 6

746h754h

5A2h5B0h

NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.

8 Electrical Characteristics

8.1

Absolute Maximum Ratings Over Operating Temperature Ranges

Supply voltage range:

0.3 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.3 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range:

0.3 to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range:

0.3 to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature, T

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds

+122

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature from case for 10 seconds

+97.8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 1)

2000 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Human body model per Method 3015.2 of MIL-STD-833B.

8.2

Recommended Operating Conditions

= 25

C, AV

= 3.3 V, DV

= 3.3 V

Voltages at analog inputs and outputs and at AV

are with respect to ground.

MIN

NOM

MAX

UNIT

Supply voltage, AVDD

3.0

3.3

3.6

Supply voltage, DVDD

3.0

3.3

3.6

Supply current analog

Operating

Supply current, analog

Power down (see Note 2)

Supply current digital

Operating

Supply current, digital

Power down (see Note 2)

942

Power dissipation

Operating

267

Power dissipation

Power down (see Note 2)

3.5

NOTE 2: If the clocks are turned off.

8.3

Static Digital Specifications

= 25

C, AV

= 3.3 V, DV

= 3.3 V

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VIH

High-level input voltage

2.0

3.6

VIL

Low-level input voltage

0.3

0.8

VOH

High-level output voltage

IO = 1 mA

2.4

VOL

Low-level output voltage

IO = +4 mA

0.4

Input leakage current

Output load capacitance

8.4

ADC Digital Filter

= 25

C, AV

= 3.3 V, DV

= 3.3 V, f

= 48 kHz, 20-bit I

S mode

All terms characterized by frequency are scaled with the chosen sampling frequency, f

. See Figure 81 through

Figure 84 for performance curves of the ADC digital filter.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC decimation filter (LPF)

Pass band

0.0

20.0

kHz

(

)

Pass band ripple

0.01

Stop band

24.1

kHz

Stop band attenuation

Group delay

720

ADC high-pass filter (HPF)

Pass band (3 dB)

0.87

(

)

Deviation from linear phase

20 Hz to 20 kHz

1.23

degrees

150

200

Amplitude

50

100

f Frequency Hz

2 fs

4 fs

6 fs

8 fs

10 fs

12 fs

Figure 81. ADC Digital Filter Characteristics

60

100

Amplitude

40

20

80

f Frequency Hz

0.2 fs

0.4 fs

0.6 fs

0.8 fs

1 fs

Figure 82. ADC Digital Filter Stop-Band Characteristics

0.002

Amplitude

0.004

0.006

0.008

f Frequency Hz

0.1 fs

0.2 fs

0.3 fs

0.4 fs

0.5 fs

Figure 83. ADC Digital Filter Pass-Band Characteristics

0.4

Amplitude

0.2

0.6

0.8

f Frequency Hz

1 fs

2 fs

3 fs

4 fs

Figure 84. ADC High-Pass Filter Characteristics

8.5

Analog-to-Digital Converter

= 25

C, AV

= 3.3 V, DV

= 3.3 V, f

= 48 kHz, 20-bit I

S mode

All terms characterized by frequency are scaled with the chosen sampling frequency, f

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SNR (EIAJ)

A weighted

Dynamic range

60 dB, 1 kHz

Signal to (noise + distortion) ratio

1 dB, 1 kHz, 20 Hz to 20 kHz

Power supply rejection ratio

1 kHz (see Note 3)

Idle channel tone rejection

+110

Intermodulation distortion

ADC crosstalk

Overall ADC frequency response

20 Hz to 20 kHz

0.1

Gain error

Gain matching

0.02

NOTE 3: Measured with a 50-mV peak sine curve.

8.6

Input Multiplexer

= 25

C, AV

= 3.3 V, DV

= 3.3 V, f

= 48 kHz, 20-bit I

S mode

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input impedance

Crosstalk

Full-scale input voltage range

1.7

VPP

8.7

DAC Interpolation Filter

= 25

C, AV

= 3.3 V, DV

= 3.3 V, f

= 48 kHz, 20-bit I

S mode

All terms characterized by frequency are scaled with the normal mode sampling frequency, f

. See Figure 85 and

Figure 86 for performance curves of the DAC digital filter.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Pass band

0.0

20.0

kHz

Pass-band ripple

0.005

Stop band

24.1

kHz

Stop-band attenuation

28.8 kHz to 3 MHz

Group delay

700

60

100

Amplitude

40

20

f Frequency Hz

80

fs/2

1 fs

2 fs

3 fs

4 fs

5 fs

Figure 85. DAC Filter Overall Frequency Characteristics

0.1

Amplitude

0.05

0.1

0.05

f Frequency Hz

0.1 fs

0.2 fs

0.3 fs

0.4 fs

0.5 fs

Figure 86. DAC Digital Filter Pass-Band Ripple Characteristics

8.8

Digital-to-Analog Converter

= 25

C, AV

= 3.3 V, DV

= 3.3 V, f

= 48 kHz, input = 0 dB-f

sine wave at 1 kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SNR (EIAJ)

A weighted

Dynamic range

60 dB, 1 kHz

Signal to (noise + distortion) ratio

0 dB, 1 kHz, 20 Hz to 20 kHz

Power supply rejection ratio

1 kHz

Idle channel tone rejection

+118

Intermodulation distortion

Frequency response

0.5

+0.5

Deviation from linear phase

1.4

degree

DAC crosstalk

Jitter tolerance

150

Full scale, single-ended, output voltage range

1.9

VPP

DC offset

7.0

8.9

DAC Output Performance Data

= 25

C, AV

= 3.3 V, DV

= 3.3 V

The output load resistance is connected through a dc blocking capacitor.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output load resistance

Output load capacitance

VCOM internal resistance (see Note 4)

VCOM output CLOAD

100

VRFILT internal resistance (see Note 5)

NOTES:

4. VCOM may vary during power down.
5. VRFILT must never be used as a voltage reference.

8.10 I

C Serial Port Timing Characteristics

MIN

MAX

UNIT

f(SCL)

SCL clock frequency

100

kHz

t(buf)

Bus free time between start and stop

4.7

t(low)

Low period of SCL clock

4.7

t(high)

High period of SCL clock

4.0

th(sta)

Hold time repeated start

4.0

tsu(sta) Setup time repeated start

4.7

th(dat)

Data hold time (See Note 6)

tsu(dat) Data setup time

250

Rise time for SDA and SCL

1000

Fall time for SDA and SCL

300

tsu(sto) Setup time for stop condition

4.0

C(b)

Capacitive load for each bus line

400

NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of

SCL.

SDA

Valid

Change

of Data

Allowed

SCL

t(buf)

th(sta)

th(dat)

th(sta)

tsu(dat)

tsu(sta)

tsu(sto)

Data

Line

Stable

NOTE: t(low) is measured from the end of tf to the beginning of tr.

t(high) is measured from the end of tr to the beginning of tf.

Figure 87. I

C Bus Timing

Appendix A

Software Interface

A.1 I

C Register Map

Table A1 is a listing of all the registers used by the I

C interface.

Table A1. I

C Register Map

REGISTER

ADDRESS

NUMBER OF

BYTES

BYTE DESCRIPTION

Reserved

00h

Main control 1

01h

MCR1(70)

DRC

02h

Ratio(70), Threshold(70), Energy(70), Attack(70), Decay(70)

Reserved

03h

Volume

04h

VL(2316), VL(158), VL(70)
VR(2316), VR(158), VR(70)

Treble

05h

T(70)

Bass

06h

B(70)

Mixer left gain

07h

S1L(2316), S1L(158), S1L(70)
S2L(2316), S2L(158), S2L(70)
AIL(2316), AIL(158), AIL(70)

Mixer right gain

08h

S1R(2316), S1R(158), S1R(70)
S2R(2316), S2R(158), S2R(70)
AIR(2316), AIR(158), AIR(70)

Reserved

09h

Left biquad 0

0Ah

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left biquad 1

0Bh

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left biquad 2

0Ch

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left biquad 3

0Dh

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left biquad 4

0Eh

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Table A1. I

C Register Map (Continued)

REGISTER

ADDRESS

NUMBER OF

BYTES

BYTE DESCRIPTION

Left biquad 5

0Fh

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left biquad 6

10h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Reserved

11h

Reserved

12h

Right biquad 0

13h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 1

14h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 2

15h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 3

16h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 4

17h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 5

18h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Right biquad 6

19h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Reserved

20h

Left loudness
biquad

21h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Table A1. I

C Register Map (Continued)

REGISTER

ADDRESS

NUMBER OF

BYTES

BYTE DESCRIPTION

Right loudness
biquad

22h

B0(2316), B0(158), B0(70)
B1(2316), B1(158), B1(70)
B2(2316), B2(158), B2(70)
A1(2316), A1(158), A1(70)
A2(2316), A2(158), A2(70)

Left loudness
biquad gain

23h

LBG(2316), LBG(158), LBG(70)

Right loudness
biquad gain

24h

RBG(2316), RBG(158), RBG(70)

Reserved

25h28h

Reserved

Test

29h

Reserved

30h to 3Fh

Analog control

40h

Anal_ctrl(70)

Test

41h

Test

42h

Main control 2

43h

MCR2(70)

Reserved

44hFFh

A.2 Main Control Register Map

A.2.1

Main Control Register 1

MCR1 01h

C(7)

C(6)

C(5)

C(4)

C(3)

C(2)

C(1)

C(0)

Table A2 lists the bit fields making up main control register 1 and defines the function associated with each bit field.

Table A2. Main Control Register 1 Description

REGISTER

DESCRIPTOR

FUNCTION

VALUE

DESCRIPTION

C(7)

Fast load

Normal operation mode

( )

Fast load mode

C(6)

SCLK frequency

SCLK = 32fS

( )

SCLK = 64fS

C(54)

E(10)

Serial port mode

Left justified

(

)

(

)

Right justified

I2S

Reserved

C(32)

Reserved

0011

Reserved

C(10)

W(10)

Serial port word

16-bit

(

)

(

)

length

18-bit

20-bit

24-bit

A.3 Volume Gain Command

Device ID

Subaddress

VL(2316)

VL(158)

VL(70)

VR(2316)

VR(158)

VR(70)

For example, if left volume = 6 dB and right volume = 6 dB, then the command is:

Table A5 lists the possible gains for the volume gain command in 0.5 dB increments from 18 to 70 dB, with the
corresponding hexadecimal value for each gain.

Table A5. Volume Versus Gain Values

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

18.0

07, F1, 7B

3.0

01, 69, 9C

12.0

00, 40, 4E

27.0

00, 0B, 6F

42.0

00, 02, 09

17.5

07, 7F, BB

2.5

01, 55, 62

12.5

00, 3C, B5

27.5

00, 0A, CC

42.5

00, 01, EB

17.0

07, 14, 57

2.0

01, 42, 49

13.0

00, 39, 50

28.0

00, 0A, 31

43.0

00, 01, D0

16.5

06, AE, F6

1.5

01, 30, 42

13.5

00, 36, 1B

28.5

00, 09, 9F

43.5

00, 01, B6

16.0

06, 4F, 40

1.0

01, 1F, 3D

14.0

00, 33, 14

29.0

00, 09, 15

44.0

00, 01, 9E

15.5

05, F4, E5

0.5

01, 0F, 2B

14.5

00, 30, 39

29.5

00, 08, 93

44.5

00, 01, 86

15.0

05, 9F, 98

0.0

01, 00, 00

15.0

00, 2D, 86

30.0

00, 08, 18

45.0

00, 01, 71

14.5

05, 4F, 10

0.5

00, F1, AE

15.5

00, 2A, FA

30.5

00, 07, A5

45.5

00, 01, 5C

14.0

05, 03, 0A

1.0

00, E4, 29

16.0

00, 28, 93

31.0

00, 07, 37

46.0

00, 01, 48

13.5

04, BB, 44

1.5

00, D7, 66

16.5

00, 26, 4E

31.5

00, 06, D0

46.5

00, 01, 36

13.0

04, 77, 83

2.0

00, CB, 59

17.0

00, 24, 29

32.0

00, 06, 6E

47.0

00, 01, 25

12.5

04, 37, 8B

2.5

00, BF, F9

17.5

00, 22, 23

32.5

00, 06, 12

47.5

00, 01, 14

12.0

03, FB, 28

3.0

00, B5, 3C

18.0

00, 20, 3A

33.0

00, 05, BB

48.0

00, 01, 05

11.5

03, C2, 25

3.5

00, AB, 19

18.5

00, 1E, 6D

33.5

00, 05, 69

48.5

00, 00, F6

11.0

03, 8C, 53

4.0

00, A1, 86

19.0

00, 1C, B9

34.0

00, 05, 1C

49.0

00, 00, E9

10.5

03, 59, 83

4.5

00, 98, 7D

19.5

00, 1B, 1E

34.5

00, 04, D2

49.5

00, 00, DC

10.0

03, 29, 8B

5.0

00, 8F, F6

20.0

00, 19, 9A

35.0

00, 04, 8D

50.0

00, 00, CF

9.5

02, FC, 42

5.5

00, 87, E8

20.5

00, 18, 2B

35.5

00, 04, 4C

50.5

00, 00, C4

9.0

02, D1, 82

6.0

00, 80, 4E

21.0

00, 16, D1

36.0

00, 04, 0F

51.0

00, 00, B9

8.5

02, A9, 25

6.5

00, 79, 20

21.5

00, 15, 8A

36.5

00, 03, D5

51.5

00, 00, AE

8.0

02, 83, 0B

7.0

00, 72, 5A

22.0

00, 14, 56

37.0

00, 03, 9E

52.0

00, 00, A5

7.5

02, 5F, 12

7.5

00, 6B, F4

22.5

00, 13, 33

37.5

00, 03, 6A

52.5

00, 00, 9B

7.0

02, 3D, 1D

8.0

00, 65, EA

23.0

00, 12, 20

38.0

00, 03, 39

53.0

00, 00, 93

6.5

02, 1D, 0E

8.5

00, 60, 37

23.5

00, 11, 1C

38.5

00, 03, 0B

53.5

00, 00, 8B

6.0

01, FE, CA

9.0

00, 5A, D5

24.0

00, 10, 27

39.0

00, 02, DF

54.0

00, 00, 83

5.5

01, E2, 37

9.5

00, 55, C0

24.5

00, 0F, 40

39.5

00, 02, B6

54.5

00, 00, 7B

5.0

01, C7, 3D

10.0

00, 50, F4

25.0

00, 0E, 65

40.0

00, 02, 8F

55.0

00, 00, 75

4.5

01, AD, C6

10.5

00, 4C, 6D

25.5

00, 0D, 97

40.5

00, 02, 6B

55.5

00, 00, 6E

4.0

01, 95, BC

11.0

00, 48, 27

26.0

00, 0C, D5

41.0

00, 02, 48

56.0

00, 00, 68

3.5

01, 7F, 09

11.5

00, 44, 1D

26.5

00, 0C, 1D

41.5

00, 02, 27

56.5

00, 00, 62

Table A5. Volume Versus Gain Values (Continued)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

GAIN (dB)

VOLUME

V(2316),

V(158),

V(70)

57.0

00, 00, 5D

60.0

00, 00, 42

63.0

00, 00, 2E

66.0

00, 00, 21

69.0

00, 00, 17

57.5

00, 00, 57

60.5

00, 00, 3E

63.5

00, 00, 2C

66.5

00, 00, 1F

69.5

00, 00, 16

58.0

00, 00, 53

61.0

00, 00, 3A

64.0

00, 00, 29

67.0

00, 00, 1D

70.0

00, 00, 15

58.5

00, 00, 4E

61.5

00, 00, 37

64.5

00, 00, 27

67.5

00, 00, 1C

mute

00, 00, 00

59.0

00, 00, 4A

62.0

00, 00, 34

65.0

00, 00, 25

68.0

00, 00, 1A

59.5

00, 00, 45

62.5

00, 00, 31

65.5

00, 00, 23

68.5

00, 00, 19

A.4 Treble Control Register Command

Both left and right channels are given the same treble gain setting.

Device ID

Subaddress

T(70)

For example, if treble gain = 5 dB, then the command is:

Table A6 lists the possible gain adjustments in 0.5 dB increments across the range of treble control, 18 to 18 dB,
with the corresponding hexadecimal value for each gain adjustment.

Table A6. Treble Control Register

GAIN (dB)

T(70)

(hex)

GAIN (dB)

T(70)

(hex)

GAIN (dB)

T(70)

(hex)

GAIN (dB)

T(70)

(hex)

GAIN (dB)

T(70)

(hex)

18.0

01h

10.5

4Ah

3.0

6Bh

4.5

7Bh

12.0

8Ah

17.5

01h

10.0

4Dh

2.5

6Ch

5.0

7Ch

12.5

8Bh

17.0

04h

9.5

51h

2.0

6Dh

5.5

7Dh

13.0

8Ch

16.5

08h

9.0

53h

1.5

3Fh

6.0

7Eh

13.5

8Dh

16.0

13h

8.5

56h

1.0

70h

6.5

7Fh

14.0

8Eh

15.5

1Ah

8.0

59h

0.5

71h

7.0

80h

14.5

8Fh

15.0

20h

7.5

5Bh

0.0

72h

7.5

81h

15.0

90h

14.5

26h

7.0

5Dh

0.5

73h

8.0

82h

15.5

91h

14.0

2Ch

6.5

60h

1.0

74h

8.5

83h

16.0

92h

13.5

31h

6.0

62h

1.5

75h

9.0

84h

16.5

93h

13.0

36h

5.5

63h

2.0

76h

9.5

85h

17.0

94h

12.5

3Bh

5.0

65h

2.5

77h

10.0

86h

17.5

95h

12.0

3Fh

4.5

67h

3.0

78h

10.5

87h

18.0

96h

11.5

43h

4.0

68h

3.5

79h

11.0

88h

11.0

47h

3.5

69h

4.0

7Ah

11.5

89h

A.5 Bass Control Register Command

Both left and right channels are given the same bass gain setting.

Device ID

Subaddress

B(70)

For example, if bass gain = 5 dB, then the command is:

Table A7 lists the possible gain adjustments in 0.5 dB increments across the range of bass control, 18 to 18 dB,
with the corresponding hexadecimal value for each gain adjustment.

Table A7. Bass Control Register

GAIN (dB)

B(70)

(hex)

GAIN (dB)

B(70)

(hex)

GAIN (dB)

B(70)

(hex)

GAIN (dB)

B(70)

(hex)

GAIN (dB)

B(70)

(hex)

18.0

01h

10.5

4Ch

3.0

6Ah

4.5

7Bh

12.0

8Ah

17.5

0Ah

10.0

4Fh

2.5

6Bh

5.0

7Ch

12.5

8Bh

17.0

11h

9.5

52h

2.0

6Dh

5.5

7Dh

13.0

8Ch

16.5

18h

9.0

55h

1.5

6Eh

6.0

7Eh

13.5

8Dh

16.0

1Eh

8.5

58h

1.0

6Fh

6.5

7Fh

14.0

8Eh

15.5

24h

8.0

5Bh

0.5

71h

7.0

80h

14.5

8Fh

15.0

29h

7.5

5Dh

0.0

72h

7.5

81h

15.0

90h

14.5

2Eh

7.0

5Fh

0.5

73h

8.0

82h

15.5

91h

14.0

33h

6.5

61h

1.0

74h

8.5

83h

16.0

92h

13.5

37h

6.0

62h

1.5

75h

9.0

84h

16.5

93h

13.0

3Bh

5.5

63h

2.0

76h

9.5

85h

17.0

94h

12.5

3Fh

5.0

65h

2.5

77h

10.0

86h

17.5

95h

12.0

43h

4.5

66h

3.0

78h

10.5

87h

18.0

96h

11.5

46h

4.0

67h

3.5

79h

11.0

88h

11.0

49h

3.5

69h

4.0

7Ah

11.5

89h

A.6 I

C Mixer Register Command

Device ID

Subaddress

Mixer1

Mixer2

ADC Mixer

For example, if SDIN1 Mix = +6dB, SDIN2 Mix = 0dB, and ADC Mix = Mute, then the command is:

Left

1F EC 98

10 00 00

00 00 00

Right

1F EC 98

10 00 00

00 00 00

Even if only one of the mixers needs to be changed, the whole command must be sent.

Table A8 lists the possible gain settings for the I

C mixer input channels in 0.5 dB increments from 18 to 70 dB,

with the corresponding hexadecimal value for each gain.

Table A8. Mixer1, Mixer2 and ADC Mixer Gain Values

GAIN (dB)

GAIN

S(2316),

S(158),

S(70)

GAIN (dB)

GAIN

S(2316),

S(158),

S(70)

GAIN (dB)

GAIN

S(2316),

S(158),

S(70)

GAIN (dB)

GAIN

S(2316),

S(158),

S(70)

GAIN (dB)

GAIN

S(2316),

S(158),

S(70)

18.0

7F, 17, AF

0.0

10, 00, 00

18.0

02, 03, A7

36.0

00, 40, EA

54.0

00, 08, 2C

17.5

77, FB, AA

0.5

0F, 1A, DF

18.5

01, E6, CF

36.5

00, 3D, 49

54.5

00, 07, B7

17.0

71, 45, 75

1.0

0E, 42, 90

19.0

01, CB, 94

37.0

00, 39, DB

55.0

00, 07, 48

16.5

6A, EF, 5D

1.5

0D, 76, 5A

19.5

01, B1, DE

37.5

00, 36, 9E

55.5

00, 06, E0

16.0

64, F4, 03

2.0

0C, B5, 91

20.0

01, 99, 99

38.0

00, 33, 90

56.0

00, 06, 7D

15.5

5F, 4E, 52

2.5

0B, FF, 91

20.5

01, 82, AF

38.5

00, 30, AE

56.5

00, 06, 20

15.0

59, F9, 80

3.0

0B, 53, BE

21.0

01, 6D, 0E

39.0

00, 2D, F5

57.0

00, 05, C9

14.5

54, F1, 06

3.5

0A, B1, 89

21.5

01, 58, A2

39.5

00, 2B, 63

57.5

00, 05, 76

14.0

50, 30, A1

4.0

0A, 18, 66

22.0

01, 45, 5B

40.0

00, 28, F5

58.0

00, 05, 28

13.5

4B, B4, 46

4.5

09, 87, D5

22.5

01, 33, 28

40.5

00, 26, AB

58.5

00, 04, DE

13.0

47, 78, 28

5.0

08, FF, 59

23.0

01, 21, F9

41.0

00, 24, 81

59.0

00, 04, 98

12.5

43, 78, B0

5.5

08, 7E, 80

23.5

01, 11, C0

41.5

00, 22, 76

59.5

00, 04, 56

12.0

3F, B2, 78

6.0

08, 04, DC

24.0

01, 02, 70

42.0

00, 20, 89

60.0

00, 04, 18

11.5

3C, 22, 4C

6.5

07, 92, 07

24.5

00, F3, FB

42.5

00, 1E, B7

60.5

00, 03, DD

11.0

38, C5, 28

7.0

07, 25, 9D

25.0

00, E6, 55

43.0

00, 1C, FF

61.0

00, 03, A6

10.5

35, 98, 2F

7.5

06, BF, 44

25.5

00, D9, 73

43.5

00, 1B, 60

61.5

00, 03, 72

10.0

32, 98, B0

8.0

06, 5E, A5

26.0

00, CD, 49

44.0

00, 19, D8

62.0

00, 03, 40

9.5

2F, C4, 20

8.5

06, 03, 6E

26.5

00, C1, CD

44.5

00, 18, 65

62.5

00, 03, 12

9.0

2D, 18, 18

9.0

05, AD, 50

27.0

00, B6, F6

45.0

00, 17, 08

63.0

00, 02, E6

8.5

2A, 92, 54

9.5

05, 5C, 04

27.5

00, AC, BA

45.5

00, 15, BE

63.5

00, 02, BC

8.0

28, 30, AF

10.0

05, 0F, 44

28.0

00, A3, 10

46.0

00, 14, 87

64.0

00, 02, 95

7.5

25, F1, 25

10.5

04, C6, D0

28.5

00, 99, F1

46.5

00, 13, 61

64.5

00, 02, 70

7.0

23, D1, CD

11.0

04, 82, 68

29.0

00, 91, 54

47.0

00, 12, 4B

65.0

00, 02, 4D

6.5

21, D0, D9

11.5

04, 41, D5

29.5

00, 89, 33

47.5

00, 11, 45

65.5

00, 02, 2C

6.0

1F, EC, 98

12.0

04, 04, DE

30.0

00, 81, 86

48.0

00, 10, 4E

66.0

00, 02, 0D

5.5

1E, 23, 6D

12.5

03, CB, 50

30.5

00, 7A, 48

48.5

00, 0F, 64

66.5

00, 01, F0

5.0

1C, 73, D5

13.0

03, 94, FA

31.0

00, 73, 70

49.0

00, 0E, 88

67.0

00, 01, D4

4.5

1A, DC, 61

13.5

03, 61, AF

31.5

00, 6C, FB

49.5

00, 0D, B8

67.5

00, 01, BA

4.0

19, 5B, B8

14.0

03, 31, 42

32.0

00, 66, E3

50.0

00, 0C, F3

68.0

00, 01, A1

3.5

17, F0, 94

14.5

03, 03, 8A

32.5

00, 61, 21

50.5

00, 0C, 3A

68.5

00, 01, 8A

3.0

16, 99, C0

15.0

02, D8, 62

33.0

00, 5B, B2

51.0

00, 0B, 8B

69.0

00, 01, 74

2.5

15, 56, 1A

15.5

02, AF, A3

33.5

00, 56, 91

51.5

00, 0A, E5

69.5

00, 01, 5F

2.0

14, 24, 8E

16.0

02, 89, 2C

34.0

00, 51, B9

52.0

00, 0A, 49

70.0

00, 01, 4B

1.5

13, 04, 1A

16.5

02, 64, DB

34.5

00, 4D, 27

52.5

00, 09, B6

Mute

00, 00, 00

1.0

11, F3, C9

17.0

02, 42, 93

35.0

00, 48, D6

53.0

00, 09, 2B

0.5

10, F2, B4

17.5

02, 22, 35

35.5

00, 44, C3

53.5

00, 08, A8

A10

A.7 Programming Instruction for the Loudness Contour

Device ID

Subaddress

B0(230)

B1(230)

B2(230)

A1(230)

A2(230)

For example:

Left Loudness Biquad

001A82

000000

FFE57E

E03550

0FCABB

Right Loudness Biquad

001A82

000000

FFE57E

E03550

0FCABB

Left Loudness Biquad Gain

Sub

G(230)

04C6D0

Right Loudness Biquad Gain

04C6D0

A.8 Examples of Dynamic Range Compression/Expansion (DRCE)

Table A9. Example of a DRCE I

C Instruction With DRCE On

BYTE

NUMBER

INSTRUCTION

(HEX)

INSTRUCTION DEFINITION

TABLE

TAS3002 device identification

DRC subaddress

Above-threshold ratio of 5.33:1 with DRCE on

See Table A11 and Table A12

Below-threshold ratio of 1.33:1

See Table A13 and Table A14

Threshold of 30 dB

See Table A15

Integration interval for energy level detection of 212 ms

See Table A16

Attack time constant 6.7 ms

Decay time constant 106 ms

A.8.1

DRCE On/Off

The DRCE default mode in the TAS3002 device is off.

The DRCE turns on if all eight bytes in Table A9 are transmitted and the LSB of the above-threshold ratio byte is
0.

The DRCE turns off if all eight bytes in Table A10 are transmitted and the LSB of the above-threshold ratio byte is
1. Table A10 is identical to Table A9 except for this third byte.

Table A10. Example of a DRCE I

C Instruction With DRCE Off

BYTE

NUMBER

INSTRUCTION

(HEX)

INSTRUCTION DEFINITION

TABLE

TAS3002 device identification

DRC subaddress

Above threshold ratio of 5.33:1 with DRCE off

See Table A11 and Table A12

Below threshold ratio of 1.33:1

See Table A13 and Table A14

Threshold of 30 dB

See Table A15

Integration interval for energy level detection of 212 ms

See Table A16

Attack time constant 6.7 ms

Decay time constant 106 ms

A12

Table A12. Above-Threshold Ratios for Expansion

HEXADECIMAL VALUE

RATIO (IN:OUT)

1 : 1.00

1 : 1.06

1 : 1.13

1 : 1.19

1 : 1.25

1 : 1.31

1 : 1.38

1 : 1.44

1 : 1.50

A.8.3

Below-Threshold Ratios

The below-threshold ratios are applied when the energy level of the incoming signal is detected as being anywhere
between the threshold (from Table A15) and 89.625 dB. See Figure A1.

Table A13. Below-Threshold Ratios for Expansion

HEXADECIMAL VALUE

RATIO (IN:OUT)

1 : 1.00

1 : 1.06

1 : 1.13

1 : 1.19

1 : 1.25

1 : 1.31

1 : 1.38

1 : 1.44

1 : 1.50

1 : 1.56

1 : 1.63

1 : 1.69

1 : 1.75

1 : 1.81

1 : 1.88

1 : 1.94

1 : 2.00

Table A14. Below-Threshold Ratios for Compression

HEXADECIMAL VALUE

RATIO (IN:OUT)

1.00 : 1

1.07 : 1

1.14 : 1

1.23 : 1

1.33 : 1

1.45 : 1

1.60 : 1

1.78 : 1

2.00 : 1

A13

A.8.4

Threshold

Table A15 lists a range of threshold values from 0 dB to 89.625 dB in 0.75-dB decrements.

NOTE: The TAS3002 device is capable of 0.375-dB increments. The associated hexadecimal
value can be determined by interpolating between the existing hexadecimal values in
Table A15.

Table A15. Threshold Values

HEX

VALUE

HEX

VALUE

HEX

VALUE

HEX

VALUE

HEX

VALUE

18.75

37.50

56.25

75.00

0.75

19.50

38.25

57.00

75.75

1.50

20.25

39.00

57.75

76.50

2.25

21.00

39.75

58.50

77.25

3.00

21.75

40.50

59.25

78.00

3.75

22.50

41.25

60.00

78.75

4.50

23.25

42.00

60.75

79.50

5.25

24.00

42.75

61.50

80.25

6.00

24.75

43.50

62.25

80.00

6.75

25.50

44.25

63.00

81.75

7.50

26.25

45.00

63.75

82.50

8.25

27.00

45.75

64.50

83.25

9.00

27.75

46.50

65.25

84.00

9.75

28.50

47.25

66.00

84.75

10.50

29.25

48.00

66.75

85.50

11.25

30.00

48.75

67.50

86.25

12.00

30.75

49.50

68.25

87.00

12.75

31.50

50.25

69.00

87.75

13.50

32.25

51.00

69.75

88.50

14.25

33.00

51.75

70.50

89.25

15.00

33.75

52.50

71.25

89.625

15.75

34.50

53.25

72.00

16.50

35.25

54.00

72.75

17.25

36.00

54.75

73.50

18.00

36.75

55.50

74.25

A.8.5

Time Constants

Use Table A16 to program the attack time, the decay time, and the integration interval for energy level detection.

Level detection is performed by using an alpha filter at the input of the DRCE, which functions as an energy-level
detection block for the DRCE. The time constant for level detection can be thought of as an integration interval. Use
a time constant from Table A16 as an integration interval for energy level detection.

Table A16 lists the time constants used for

integration interval for energy level detection, attack time constant, and

decay time constant. All values represent the time required to reach 63% of maximum value from zero.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TAS3002PFB

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