TAS5000
Digital Audio PWM Processor
December 2000
Digital Audio
Data Manual
SLAS270
IMPORTANT NOTICE
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
2000, Texas Instruments Incorporated
iii
Contents
Section
Title
Page
1
Introduction
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagram
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Suggested System Block Diagrams
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Terminal Assignments
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Ordering Information
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Terminal Functions
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Functional Description
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Serial Audio Port
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
System Clocks Master Mode and Slave Mode
21
. . . . . . . . . . . . . . . . .
2.3
Oscillator/Sampling Frequency
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Phase Locked Loop (PLL)/Clock Generation
21
. . . . . . . . . . . . . . . . . . . .
2.5
Digital Interpolation Filter
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Digital PWM Modulator
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Control, Status, and Operational Modes
22
. . . . . . . . . . . . . . . . . . . . . . . .
2.7.1
Power Up
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2
Reset
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3
Power Down
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.4
Mute
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.5
Double Speed
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.6
De-Emphasis Filter
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.7
Error Status Reporting (
ERR
pin)
24
. . . . . . . . . . . . . . . . . . . . . .
2.8
Serial Interface Formats
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
MSB First Right Justified (for 16-, 20-, 24-bits)
25
. . . . . . . . . .
2.8.2
IIS Compatible Serial Format (for 16-, 20-, 24-bits)
25
. . . . . .
2.8.3
MSB Left Justified Serial Interface Format (for 16 bits)
26
. . .
2.8.4
DSP Compatible Serial Interface Format (for 16 bits)
26
. . . .
2.9
PWM Outputs
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Electrical Specifications
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Recommended Operating Conditions
31
. . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Electrical Characteristics
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Static Digital Specifications
32
. . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Digital Interpolation Filter and PWM Modulator
32
. . . . . . . . . .
3.3.3
TAS5000/TAS5100 System Performance Measured at the
Speaker Terminals
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Switching Characteristics
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
3.4.1
Serial Audio Ports Slave Mode
32
. . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Serial Audio Ports Master Mode
33
. . . . . . . . . . . . . . . . . . . . . .
3.4.3
DSP Serial Interface Switching Characteristics
33
. . . . . . . . .
4
Parameter Measurement Information
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Application Information
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Figure
Title
Page
11 System #1: Stereo Configuration Using Two TAS5100 Amplifiers
13
. . . . . . . .
12 System #2: Stereo Configuration With DSP
13
. . . . . . . . . . . . . . . . . . . . . . . . . .
13 System #3: 6-Channel Audio Playback
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 Power-Up Timing (
RESET
preceding
PDN
)
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 Power-Up Timing (
PDN
preceding (
RESET
)
23
. . . . . . . . . . . . . . . . . . . . . . . . . . .
23 Reset Timing
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 Power-Down Timing
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 De-Emphasis Filter Characteristics
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 MSB First Right Justified
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 IIS Compatible Serial Format
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 MSB Left Justified Serial Interface Format
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 DSP Compatible Serial Interface Format
26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 Right Justified, IIS, Left Justified Serial Protocol Timing
41
. . . . . . . . . . . . . . . .
42 Right, Left, and IIS Serial Mode Timing Requirement
41
. . . . . . . . . . . . . . . . . .
43 Serial Audio Ports Master Mode Timing
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44 DSP Serial Port Timing
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45 DSP Serial Port Expanded Timing
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46 DSP Absolute Timing Requirement
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51 Connection Diagram, Slave Mode (typical)
51
. . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table
Title
Page
21 Oscillator, External Clock, and PLL Functions
22
. . . . . . . . . . . . . . . . . . . . . . . . .
22 Mute Description
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 De-Emphasis Selection
24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 Hardware Selection of Serial Audio Modes
25
. . . . . . . . . . . . . . . . . . . . . . . . . . .
11
1 Introduction
The TAS5000 is an innovative, cost-effective, high-performance 24-bit stereo digital modulator based on Equibit
technology. This product converts input PCM serial digital audio data to an output PWM audio data stream. The
TAS5000 is designed to be connected to two TAS5100 mono true digital amplifiers for driving loudspeakers. This
all-digital audio system contains only two analog components in the signal chain--an L-C low-pass filter at the
speaker terminals. It can provide up to 90 dB SNR at the speaker terminals. It has a wide variety of serial input options
including right justified (16, 20, or 24-bit), IIS (16, 20, or 24-bit), left justified (16-bit), or DSP (16-bit) data formats. It
is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz including providing
de-emphasis for 44.1 kHz, and 48 kHz sample rates. The TAS5000 and TAS5100 system can be used in a range of
products such as microcomponent systems, PC speakers, home theater in a box, convergence products, A/V
receivers, or TV sets.
1.1
Features
True Digital Audio Amplifier
High Quality Audio
16-, 20-, or 24 Bit Input Data
Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz
Supports Master and Slave Modes
90 dB SNR (EIAJ) and Dynamic Range at the Speaker Terminals
3.3 V Power Supply Operation
Economical 48-Pin TQFP Package
Digital De-Emphasis: 44.1 kHz and 48 kHz
High Power Efficiency
Clock Oscillator Circuit for Master Modes
Low Jitter Internal PLL
Mute
Good Phase Characteristics
Excellent PSRR
Equibit is the trademark of Texas Instruments.
12
1.2
Functional Block Diagram
PLL/Clock
Generator
OSC
Serial
Audio
Port
Digital
Interpolation
Filter
Equibit
Modulator
Buffer
Audio Port
Configuration
Control Section
LRCLK
SCLK
SDIN
PWM_P_L
PWM_M_L
PWM_P_R
PWM_M_R
PLL_FL
T_RET
PLL_FL
T_OUT
MCLK_IN
ERR
MCLK_OUT
XTL_IN
XTL_OUT
OSC_CAP
MOD0
MOD1
MOD2
DEM_SEL
DEM_EN
MUTE
RESET
PDN
FTEST
STEST
DBSPD
M_S
DVDD1
DVSS1
DVDD2
DVSS2
DVDD3_L
DVSS3_L
DVDD3_R
DVSS3_R
A
VDD1
A
VSS1
A
VDD2
A
VSS2
PTEST
13
1.3
Suggested System Block Diagrams
See application notes for more details.
USB
IEEE 1394
SPDIF
ADC
Automotive
MOST
Network
Digital Audio
TAS3001
IIC
Audio
Control
TAS5000
TAS5100
Left
Right
Digital Parametric EQ
Volume
DRC
Bass
Treble
Serial Audio Input Port
Internal PLL
2 Mono H-Bridges
TAS5100
Figure 11. System #1: Stereo Configuration Using Two TAS5100 Amplifiers
TAS5000
TAS5100
Left
Right
Volume
EQ
DRC
Bass
Treble
Surround Processing
AC-3 DTS Decode
Serial Audio Input Port
Internal PLL
DSP
Digital Audio
TAS5100
2 Mono H-Bridges
Figure 12. System #2: Stereo Configuration With DSP
14
DSP 6-Channel
Decode
Dolby AC-3
DTS
Volume
EQ
DRC
Bass
Treble
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
TAS5000
TAS5100
CH1
CH2
TAS5000
CH3
CH4
TAS5000
CH5
CH6
6
TAS5100
TAS5100
TAS5100
TAS5100
TAS5100
Figure 13. System #3: 6-Channel Audio Playback
15
1.4
Terminal Assignments
14 15
DVDD3_L
PWM_P_L
PWM_M_L
NC
NC
DVDD2
DVSS2
PWM_P_R
PWM_M_R
NC
NC
DVDD3_R
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
MCLK_IN
AVDD2
PLL_FLT_OUT
PLL_FLT_RET
AVSS2
NC
RESET
PDN
PTEST
M_S
NC
DVDD1
17 18 19 20
FTEST
STEST
DBSPD
MUTE
47 46 45 44 43
48
42
A
VDD1
XTL_IN
XTL_OUT
OSC_CAP
A
VSS1
MOD0
ERR
DVSS3_R
DVSS1
SCLK
LRCLK
SDIN
MOD2
MOD1
40 39 38
41
21 22 23 24
37
13
DVSS3_L
DEM_EN
DEM_SEL
DVDD1
MCLK_OUT
48-Pin TQFP PACKAGE
(TOP VIEW)
NC No internal connection
DVSS1
1.5
Ordering Information
TA
PACKAGE
0
C to 70
C
TAS5000PFB
16
1.6
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD1
48
I
Analog supply for oscillator
AVDD2
2
I
Analog supply for PLL
AVSS1
44
I
Analog ground for oscillator
AVSS2
5
I
Analog ground for PLL
DBSPD
39
I
Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_EN
43
I
De-emphasis enable, active high
DEM_SEL
42
I
De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
DVDD1
12, 14
I
Digital voltage supply for logic
DVDD2
31
I
Digital voltage supply for PWM reclocking
DVDD3_L
36
I
Digital voltage supply for PWM output (left)
DVDD3_R
25
I
Digital voltage supply for PWM output (right)
DVSS1
13, 15
I
Digital ground for Logic
DVSS2
30
I
Digital ground for PWM reclocking
DVSS3_L
37
I
Digital ground for PWM output (left)
DVSS3_R
24
I
Digital ground for PWM output (right)
ERR
23
O
System error flag, active low
FTEST
41
I
Tied to DVSS1 for normal operation
LRCLK
18
I/O
Left/right clock (input when M_S = 0; output when M_S = 1)
MCLK_IN
1
I
MCLK input
MCLK_OUT
16
O
Buffered system clock output if M_S = 1; otherwise set to 0
MOD0
22
I
Serial interface selection pin, bit 0
MOD1
21
I
Serial interface selection pin, bit 1
MOD2
20
I
Serial interface selection pin, bit 2 (MSB)
M_S
10
I
Master/slave, Master=1, Slave=0
MUTE
38
I
Muted signal = 0, Normal mode = 1
NC
6, 11, 26, 27,
32, 33
No connection
OSC_CAP
45
I
Oscillator cap return
PDN
8
I
Power down, active low
PTEST
9
I
Tied to DVSS1 for normal operation
PLL_FLT_OUT
3
O
Output terminal for external PLL filter
PLL_FLT_RET
4
I
Return for external PLL filter
PWM_M_L
34
O
PWM left output (differential ) Positive H-bridge side
PWM_M_R
28
O
PWM right output (differential ) Positive H-bridge side
PWM_P_L
35
O
PWM left output (differential +) Positive H-bridge side
PWM_P_R
29
O
PWM right output (differential +) Positive H-bridge side
RESET
7
I
Reset (active low)
SCLK
17
I/O
Shift clock (input when M_S = 0, output when M_S = 1)
SDIN
19
I
Stereo serial audio data input
STEST
40
I
Tied to DVSS1 for normal operation
XTL_IN
47
I
Crystal or clock input (MCLK input)
XTL_OUT
46
O
Crystal output (not for external usage) NC when XTL_IN is MCLK input
21
2 Functional Description
2.1
Serial Audio Port
The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and
a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz, 88.2 kHz,
or 96 kHz) stereo. See section 2.8 for Serial Interface Formats.
2.2
System Clocks Master Mode and Slave Mode
The TAS5000 allows multiple system clocking schemes. In this document, master mode indicates that the TAS5000
provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256Fs MCLK_OUT,
64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates
that a system master other than the TAS5000 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5000
(M_S = 0). The TAS5000 operates with LRCLK and SCLK synchronized to MCLK. TAS5000 does not require any
specific phase relationship between LRCLK and MCLK, but there must be synchronization. If the synchronization
between MCLK and LRCLK changes more than 10 MCLK periods during one sample period (LRCLK), the TAS5000
will initiate an internal reset. In the slave mode MCLK_OUT is driven low. Table 21 shows all the possible master
and slave modes.
2.3
Oscillator/Sampling Frequency
The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which should
be either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling frequency can be
selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave
mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz
(Fs = 96 kHz). Table 21 explains the proper clock selection.
2.4
Phase Locked Loop (PLL)/Clock Generation
A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FLT_RET and PLL_FLT_OUT. See Figure 51 for a suggested external loop filter. If the PLL loses lock, the error
status pin (ERR) will go low. Note that ERR can go low for other conditions as well. See section 2.7.7 Error Status
Reporting.
22
Table 21. Oscillator, External Clock, and PLL Functions
DESCRIPTION
M_S
DBSPD
XTL_IN
(MHz)
MCLK_IN
(MHz)
SCLK
(MHz)
LRCLK
(kHz)
MCLK_OUT
(MHz)#
Master, normal speed
1
0
11.2896
--
2.8224
44.1
11.2896
Master, normal speed
1
0
12.288
--
3.072
48
12.288
Master, double speed
1
1
--
22.5792
5.6448
88.2
22.5792
Master, double speed
1
1
--
24.576
6.144
96
24.576
Slave, normal speed
0
0
--
11.2896
2.8224
44.1
Digital GND
Slave, normal speed
0
0
--
12.288
3.072
48
Digital GND
Slave, double speed
0
1
--
22.5792
5.6448
88.2
Digital GND
Slave, double speed
0
1
--
24.576
6.144
96
Digital GND
Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.
External MCLK connected to MCLK_IN input
SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.
# MCLK_OUT is driven low when M_S=0.
2.5
Digital Interpolation Filter
The 24-bit high performance linear phase FIR interpolation filter up-samples the input digital data at a rate of 4 times
(double speed mode = 88.2 kHz or 96 kHz) or 8 times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate.
This filter provides very low pass-band ripple and optimized time domain transient response for accurate music
reproduction.
2.6
Digital PWM Modulator
The interpolation filter output is sent to the modulator. This modulator consists of a high performance 4
th
order digital
noise shaper and a PCM to PWM converter. Following the noise shaper, the PCM signal is fed into a very low distortion
PCM to PWM conversion block, buffered and output from the chip. The modulation scheme is based on a 2-state
control of the H-bridge output.
2.7
Control, Status, and Operational Modes
The TAS5000 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and
MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0,
MOD1, or MOD2 pins changes state, a reset sequence is initiated (see paragraph 2.7.2). Also provided are separate
power-down (PDN), reset (RESET), and mute (MUTE) pins. The ERR pin indicates that an error has occurred.
2.7.1
Power Up
At power up the ERR pin is asserted low and the PWM outputs go to the hard mute state in which the P outputs are
held low and the M outputs are held high. Following initialization, the TAS5000 will come up in the operational state.
There are two cases of power-up timing. The first case is shown in Figure 21 with RESET preceding PDN. The
second case is shown in Figure 22 with PDN preceding RESET.
Initialization Time = 4224 LRCLK Periods
RESET
ERR
PDN
Figure 21. Power-Up Timing (RESET preceding PDN)
23
Initialization Time = 256 LRCLK Periods
RESET
ERR
PDN
Greater Than 16 MCLK Periods
Figure 22. Power-Up Timing (PDN preceding RESET)
2.7.2
Reset
The reset signal for the TAS5000 should be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 23 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As long
as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted (P-outputs
held low and M-outputs held high) and the ERR status pin is held low. Assuming PDN is high, the rising edge of the
reset pulse begins chip initialization. After 256 LRCLK periods the TAS5000 will begin normal operation.
Initialization
Normal
Operation
RESET
ERR
PDN
Normal Operation
Figure 23. Reset Timing
2.7.3
Power Down
When PDN is low (see Figure 24. Power-Down Timing) both the PLL and the oscillator are shut down. Note that
power down is an asynchronous operation. To place the device in total power-down mode, both RESET and PDN
must be held low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are
hard muted with the P outputs held low and the M outputs held high. To place the device back into normal mode, see
section 2.7.1 for power-up timing.
NOTE: In order for the dynamic logic to be properly powered down, the clocks should not be stopped before
the PDN pin goes low. Otherwise, the device may drain additional supply current.
Initialization
Chip
Power-Down
ERR
PDN and
RESET
Normal Operation
Normal
Operation
Figure 24. Power-Down Timing
2.7.4
Mute
The TAS5000 provides a mute function that is used when the MUTE pin is asserted low. See Table 22 for Mute
Description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform in which
both sides of the differential PWM outputs have a 50% duty cycle.
24
Table 22. Mute Description
MUTE
PWM_P
PWM_M
DESCRIPTION
0
50% Duty cycle
50% Duty cycle
Mute
1
DATA
DATA
Normal operation
2.7.5
Double Speed
Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the TAS5000 in
double-speed mode with the device in normal operating conditions, the RESET pin must be held low while switching
the DBSPD pin high. After RESET pin is brought high again, a reset sequence takes place (see paragraph 2.7.2).
If the change is at power up, a power up sequence is originated (see paragraph 2.7.1).
2.7.6
De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50
s/15
s de-emphasis filter is provided to support
the sampling rates of 44.1 kHz and 48 kHz. Pins DEM_SEL and DEM_EN select the de-emphasis functions. See
Figure 25 for a graph showing the de-emphasis filtering characteristics. See Table 23 for de-emphasis selection.
When the DEM_EN pin or the DEM_SEL pin change state, the PWM outputs go into the quiet mute state. After 128
LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
0
10
Response
dB
3.18 (50
s)
10.6 (15
s)
f Frequency kHz
Deemphasis
Figure 25. De-Emphasis Filter Characteristics
2.7.6.1 De-Emphasis Selection
De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 23 for de-emphasis
selection description.
Table 23. De-Emphasis Selection
DEM_SEL
DEM_EN
DESCRIPTION
X
0
De-emphasis disabled
0
1
De-emphasis enabled for Fs = 44.1 kHz
1
1
De-emphasis enabled for Fs = 48 kHz
2.7.7
Error Status Reporting (ERR pin)
The following is a list of the error conditions that will cause the ERR status pin to be asserted low:
No clocks
Clock phase errors
When any of the above conditions is met, the ERR will go low and the PWM outputs will go to the hard mute state.
If the error condition is removed, the TAS5000 is reinitialized and the ERR pin will be asserted high.
2.8
Serial Interface Formats
The TAS5000 is compatible with eight different serial interfaces. Available interface options are IIS, right justified, left
justified, and DSP Frame. Table 24 indicates how these options are selected using the MOD0, MOD1, and MOD2
pins.
25
Table 24. Hardware Selection of Serial Audio Modes
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
SERIAL INTERFACE
SDIN
0
0
0
0
16 bit, MSB first; right justified
1
0
0
1
20 bit, MSB first; right justified
2
0
1
0
24 bit, MSB first; right justified
3
0
1
1
16 bit IIS
4
1
0
0
20 bit IIS
5
1
0
1
24 bit IIS
6
1
1
0
16 bit MSB first, left justified
7
1
1
1
16 bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different
interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0.
2.8.1
MSB First Right Justified (for 16-, 20-, 24-bits)
X
MSB
LSB
X
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 26. MSB First Right Justified
Note the following characteristics of this protocol.
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
The SDIN data is justified to the trailing edge of the LRCLK
SDIN is sampled at the rising edge of SCLK.
If LRCLK phase changes by more than 10 MCLKs, then the chip automatically resets.
2.8.2
IIS Compatible Serial Format ( for 16-, 20-, 24-bits)
X
MSB
LSB
X
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 27. IIS Compatible Serial Format
Note the following characteristics of this protocol.
26
Left channel is received when LRCLK is low.
Right channel is received when LRCLK is high.
SDIN is sampled with the rising edge of SCLK.
2.8.3
MSB Left Justified Serial Interface Format (for 16 bits)
MSB
LSB
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 28. MSB Left Justified Serial Interface Format
Note the following characteristics of this protocol.
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
The SDIN data is justified to the leading edge of the LRCLK.
SDIN is sampled with the rising edge of SCLK.
2.8.4
DSP Compatible Serial Interface Format (for 16 bits)
SCLK
LRCLK = Fs
SDIN
Left Channel
(MSB = 15)
Right Channel
(MSB = 15)
15
14
13
0
15
14
13
0
Figure 29. DSP Compatible Serial Interface Format
Note the following characteristics of this protocol.
Serial data is sampled with the falling edge of SCLK.
2.9
PWM Outputs
Designed to be used with TAS5100.
31
3 Electrical Specifications
3.1
Absolute Maximum Ratings
Analog supply voltage range, AV
DD1,
AV
DD2
)
0.3 V to 4.2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital power supply voltage, DV
DD1,
DV
DD2,
DV
DD3_L,
DV
DD3_R
0.3 V to 4.2 V
. . . . . . . . . . . . . . . . . . . . .
Digital input voltage, V
I
(see Note 1)
0.3 V to DV
DDX
+0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, T
A
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD
2000 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. DVDD1, DVDD2, DVDD3_L, DVDD3_R
3.2
Recommended Operating Conditions
(T
A
= 25
C; DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= 3.3 V
10%, AV
DD1
= AV
DD2
= 3.3 V
10%, Fs = 44.1 kHz)
Voltages at analog inputs and outputs are with respect to ground
MIN
TYP
MAX
UNIT
Supply voltage
Digital
DVDDX
3
3.3
3.6
V
Supply current
Digital
Operating
18
mA
Supply current
Digital
Power down
2
20
A
Power dissipation
Digital
Operating
59.4
mW
Power dissipation
Digital
Power down
6.6
72
W
Supply voltage
Analog
AVDDX
3
3.3
3.6
V
Supply current
Analog
Operating
8
mA
Supply current
Analog
Power down
10
100
A
Power dissipation
Analog
Operating
26.4
mW
Power dissipation
Analog
Power down
33
360
W
DVDD1, DVDD2, DVDD3_L, DVDD3_R
If the clocks are turned off
AVDD1, AVDD2
32
3.3
Electrical Characteristics
3.3.1
Static Digital Specifications
(T
A
= 25
C; DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= 3.3 V
10%, AV
DD1
= AV
DD2
= 3.3 V
10%)
MIN
MAX
UNIT
VIH
High-level input voltage
2
DVDD1
V
VIL
Low-level input voltage
0
0.8
V
VOH
High-level output voltage, (IO = 1 mA)
2.4
V
VOL
Low-level output voltage, (IO = 4 mA)
0.4
V
Input leakage current
10
10
A
3.3.2
Digital Interpolation Filter and PWM Modulator
(T
A
= 25
C; DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= 3.3 V
10%, AV
DD1
= AV
DD2
= 3.3 V
10%, Fs = 44.1 kHz)
All the terms characterized by frequency will scale with the normal mode sampling frequency, Fs.
MIN
TYP
MAX
UNIT
Pass band
0
20
kHz
Pass band ripple
0.012
dB
Stop band
24.1
kHz
Stop band attenuation (24.1 kHz to 152.3 kHz)
50
dB
Group delay
700
S
PWM modulation index (gain)
0.93
3.3.3
TAS5000/TAS5100 System Performance Measured at the Speaker Terminals
Reference section 4.4 in the TAS5100 Data Manual
3.4
Switching Characteristics
3.4.1
Serial Audio Ports Slave Mode
(T
A
= 25
C, DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= AV
DD1
= AV
DD2
= 3.3 V
10%)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
6.144
MHz
tsu(SDIN)
SDIN setup time before SCLK rising edge
20
ns
th(SDIN)
SDIN hold time from SCLK rising edge
10
ns
F(LRCLK)
LRCLK frequency
44.1
48
96
kHz
MCLK duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
tsu(LRCLK)
LRCLK edge setup before SCLK rising edge
20
ns
33
3.4.2
Serial Audio Ports Master Mode
Load conditions: 50pF
(T
A
= 25
C, DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= AV
DD1
= AV
DD2
= 3.3 V
10%)
PARAMETER
MIN
TYP
MAX
UNIT
t(MSD)
MCLK to SCLK
0
5
ns
t(MLRD)
MLCK to LRCLK
0
5
ns
SCLK, LRCLK duty cycle
50%
3.4.3
DSP Serial Interface Mode
(T
A
= 25
C, DV
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= AV
DD1
= AV
DD2
= 3.3 V
10%)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
6.144
MHz
tW(FSHIGH)
Pulse duration, sync
1/(64
fs)
ns
tsu(SDIN),
tsu(LRCLK)
SDIN and LRCLK setup time before SCLK falling edge
20
ns
th(SDIN),
th(LRCLK)
SDIN and LRCLK hold time from SCLK falling edge
10
ns
SCLK duty cycle
50%
34
41
4 Parameter Measurement Information
th(SDIN)
tsu(SDIN)
SCLK
SDIN
Figure 41. Right Justified, IIS, Left Justified Serial Protocol Timing
tsu(LRCLK)
SCLK
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 42. Right, Left, and IIS Serial Mode Timing Requirement
t(MSD)
t(MLRD)
SCLK
LRCLK
(Output)
MCLK
(Output)
Figure 43. Serial Audio Ports Master Mode Timing
th(SDIN)
tsu(SDIN)
SCLK
LRCLK
SDIN
tsu(LRCLK)
tw(FSHIGH)
th(LRCLK)
Figure 44. DSP Serial Port Timing
42
tw(FSHIGH)
64 fs
16-Bit Left Channel Data
16-Bit Left Channel Data
16-Bit Left Channel Data
32-Bit Ignore
SCLK
LRCLK
SDIN
Figure 45. DSP Serial Port Expanded Timing
tsu(SDIN) = 20 ns
th(SDIN) = 10 ns
SCLK
SDIN
NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 46. DSP Absolute Timing Requirement
51
5 Application Information
Audio
Source
Clock
Generator
PLL_FLT_RET
PLL_FLT_OUT
DEM_SEL
DEM_EN
DBSPD
SDIN
LRCLK
SCLK
MCLK_IN
MOD0
MOD1
MOD2
M_S
TAS5100
H-Bridge
PWM_P_L
PWM_M_L
ERR
RESET
TAS5100
H-Bridge
PWM_P_R
PWM_M_R
Micro-
Controller
MUTE
PDN
3.3 V DIG
XTL_IN
C2
R1
C1
See application note for values
Figure 51. Connection Diagram, Slave Mode (typical)
52
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