TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
DIGITAL AMPLIFIER POWER STAGE
TM
FEATURES
D
70-W RMS Power (BTL) Into 4
With Less
Than 0.2% THD+N
D
95-dB Dynamic Range (TDAA System With
TAS5026)
D
Power Efficiency Greater Than 90% Into 4-
and 8-
Loads
- Smaller Power Supplies
D
Self-Protecting Design With Autorecovery
D
32-Pin TSSOP (DAD) PowerPAD
Package
D
3.3-V Digital Interface
D
EMI-Compliant When Used With
Recommended System Design
APPLICATIONS
D
DVD Receiver
D
Home Theatre
D
Mini/Micro Component Systems
D
Internet Music Appliance
DESCRIPTION
The TAS5111 is a high-performance digital amplifier power
stage designed to drive a 4-
speaker up to 70 W with
0.2% distortion plus noise. The device incorporates TI's
PurePath Digital
technology and is used with a digital
audio PWM processor (TAS50XX) and a simple passive
demodulation filter to deliver high-quality, high-efficiency
digital audio amplification.
The efficiency of this digital amplifier can be greater than
90%, depending on the system design. Overcurrent
protection, overtemperature protection, and undervoltage
protection are built into the TAS5111, safeguarding the
device and speakers against fault conditions that could
damage the system.
PO - Output Power - W
100m
RL = 4
TC = 75
C
1
10
100
0.01
0.1
1
THD+N - T
otal Harmonic Distortion + Noise - %
THD + NOISE vs OUTPUT POWER
f - Frequency - Hz
20
100
1k
10k
THD+N - T
otal Harmonic Distortion + Noise - %
0.001
0.1
1
20k
RL = 4
TC = 75
C
0.01
PO = 70 W
PO = 1 W
PO = 10 W
THD + NOISE vs FREQUENCY
PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2004, Texas Instruments Incorporated
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5111 is offered in a thermally enhanced 32-pin
TSSOP surface-mount package (DAD), which has the
thermal pad on top.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PWM_BP
GND
RESET
DREG_RTN
GREG
M3
DREG
DGND
M1
M2
DVDD
SD
DGND
OTW
GND
PWM_AP
GVDD
GND
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GND
GVDD
DAD PACKAGE
(TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TAS5111
UNITS
DVDD TO DGND
0.3 V to 4.2 V
GVDD TO GND
33.5 V
PVDD_X TO GND (dc voltage)
33.5 V
PVDD_X TO GND (spike voltage(2))
48 V
OUT_X TO GND (dc voltage)
33.5 V
OUT_X TO GND (spike voltage(2))
48 V
BST_X TO GND (dc voltage)
48 V
BST_X TO GND (spike voltage(2))
53 V
GREG TO GND (3)
14.2 V
PWM_XP, RESET, M1, M2, M3, SD,
OTW
0.3 V to DVDD + 0.3 V
Maximum operating junction
temperature, TJ
40
C to 150
C
Storage temperature
40
C to 125
C
(1) Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device
reliability.
(2) The duration of a voltage spike should be less than 100 ns.
(3) GREG is treated as an input when the GREG pin is overdriven by
a GVDD voltage of 12 V.
PACKAGE DISSIPATION RATINGS
PACKAGE
R
JC
(
C/W)
R
JA
(
C/W)
32-Pin DAD TSSOP
1.69
See Note 1
(1) The TAS5111 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only means for
heat dissipation.
For this reason, R
JA, a system parameter that characterizes the
thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
R
JA values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed. Also, for additional general information on
PowerPad packages, see TI document SLMA002.
ORDERING INFORMATION
TA
PACKAGE
DESCRIPTION
0
C to 70
C
TAS5111DAD
32-pin small TSSOP
For the most current specification and package
information, refer to the TI Web site at www.ti.com.
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
3
Terminal Functions
TERMINAL
FUNCTION(1)
DESCRIPTION
NAME
NO.
FUNCTION(1)
DESCRIPTION
BST_A
19
P
High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B
30
P
High side bootstrap supply (BST), external capacitor to OUT_B required
DGND
8, 13
P
I/O reference ground
DREG
7
P
Digital supply voltage regulator decoupling pin, capacitor connected to DREG_RTN
DREG_RTN
4
P
Decoupling return pin
DVDD
11
P
I/O reference supply input (3.3 V): 100
to DREG
GND
2,15, 18,
24, 25,
31
P
Power ground
GREG
5
P
Gate drive voltage regulator decoupling pin, capacitor to GND
GVDD
17, 32
P
Voltage supply to on-chip gate drive and digital supply voltage regulators
M1
9
I
Mode selection pin
M2
10
I
Mode selection pin
M3
6
I
Mode selection pin
OTW
14
O
Overtemperature warning output, open drain with internal pullup resistor
OUT_A
22, 23
O
Output, half-bridge A
OUT_B
26, 27
O
Output, half-bridge B
PVDD_A
20, 21
P
Power supply input for half-bridge A
PVDD_B
28, 29
P
Power supply input for half-bridge B
PWM_AP
16
I
Input signal, half-bridge A
PWM_BP
1
I
Input signal, half-bridge B
RESET
3
I
Reset signal, active low
SD
12
O
Shutdown signal for half-bridges A and B
(1) I = input, O = Output, P = Power
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
4
FUNCTIONAL BLOCK DIAGRAM
GREG
GVDD
GREG
DREG_RTN
Timing
Control
Gate
Drive
PWM_AP
OUT_A
GND
PVDD_A
BST_A
PWM
Receiver
OUT_B
GND
PVDD_B
GREG
Protection A
Protection B
PWM_BP
RESET
GREG
BST_B
DREG
To Protection
Blocks
OTW
SD
DREG
DREG_RTN
GREG
DREG
Gate
Drive
Gate
Drive
Gate
Drive
GREG
OT
Protection
UVP
PWM
Receiver
Timing
Control
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
5
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
DVDD
Digital supply (1)
Relative to DGND
3
3.3
3.6
V
GVDD
Supply for internal gate drive and logic
regulators
Relative to GND
16
29.5
30.5
V
PVDD_x
Half-bridge supply
Relative to GND, RL= 4
to 8
0
29.5
30.5
V
TJ
Junction temperature
0
125
_
C
(1) It is recommended for DVDD to be connected to DREG via a 100-
resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-
resistor, RL = 4
, 8X fs = 384 kHz, unless otherwise noted
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
TA = 25
C
TA = 25
C
TC = 75
C
TA = 40
C
to 85
C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE, BTL Mode, 1 kHz
RL = 8
, THD = 0.2%,
AES17 filter
40
W
Typ
RL = 8
, THD = 10%, AES17
filter
53
W
Typ
Po
Output power
RL = 6
, THD = 0.2%,
AES17 filter
53
W
Typ
Po
Output power
RL = 6
, THD = 10%, AES17
filter
68
W
Typ
RL = 4
, THD = 0.2%,
AES17 filter
74
W
Typ
RL = 4
, THD = 10%, AES17
filter
93
W
Typ
Po = 1 W/ channel, RL = 4
,
AES17 filter
0.05%
Typ
THD+N
Total harmonic
distortion + noise
Po = 10 W/channel, RL = 4
,
AES17 filter
0.03%
Typ
distortion + noise
Po = 70 W/channel, RL = 4
,
AES17 filter
0.2%
Typ
Vn
Output integrated
voltage noise
A-weighted, mute, RL = 4
,
20 Hz to 20 kHz, AES17 filter
295
V
Max
SNR
Signal-to-noise ratio
A-weighted, AES17 filter
95
dB
Typ
DR
Dynamic range
f = 1 kHz, A-weighted,
AES17 filter
95
dB
Typ
INTERNAL VOLTAGE REGULATOR
DREG
Voltage regulator
Io = 1 mA,
3.1
V
Min
DREG
Voltage regulator
Io = 1 mA,
PVDD = 18 V-30.5 V
3.1
V
Max
GREG
Voltage regulator
Io = 1.2 mA,
13.4
V
Min
GREG
Voltage regulator
Io = 1.2 mA,
PVDD = 18 V-30.5 V
13.4
V
Max
IVGDD
GVDD supply current,
operating
fS = 384 kHz, no load,
50% duty cycle
27
mA
Max
IDVDD
DVDD supply current,
operating
fS = 384 kHz, no load
1
5
mA
Max
OUTPUT STAGE MOSFETs
Ron,LS
Forward on-resistance,
low side
TJ = 25
C
120
132
m
Max
Ron,HS
Forward on-resistance,
high side
TJ = 25
C
120
132
m
Max
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
6
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, connected to DREG via a 100-
resistor, RL = 4
, 8X fs = 384 kHz, unless otherwise noted
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
TA = 25
C
TA = 25
C
TC = 75
C
TA = 40
C
to 85
C
UNITS
MIN/TYP/
MAX
INPUT/OUTPUT PROTECTION
Vuvp,G
Undervoltage protection
Set the DUT in normal
operation mode with all the
protections enabled. Sweep
GVDD up and down. Monitor
7.4
6.9
V
Min
Vuvp,G
Undervoltage protection
limit, GVDD
GVDD up and down. Monitor
SD output. Record the
GREG reading when SD is
triggered.
7.4
7.9
V
Max
OTW
Overtemperature
warning
125
C
Typ
OTE
Overtemperature error
150
C
Typ
OC
Overcurrent protection
See Note 1.
8
A
Typ
STATIC DIGITAL SPECIFICATION
PWM_AP, PWM_BP,
M1, M2, M3, SD, OTW
VIH
High-level input voltage
2
V
Min
VIH
High-level input voltage
DVDD
V
Max
VIL
Low-level input voltage
0.8
V
Max
Leakage
Input leakage current
-10
A
Min
Leakage
Input leakage current
10
A
Max
OTW/SHUTDOWN (SD)
Internally pull up R from
OTW/SD to DVDD
28
22
k
Min
VOL
Low-level output voltage
IO = 4 mA
0.4
V
Max
(1) To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See
Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for
optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5111. It is recommended to follow
the TAS5026-5111KEVM (S/N 001) design and layout guidelines for best performance.
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
7
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
TAS5111DAD
VALID_1
18
17
4
13
11
10
9
8
7
PWM PROCESSOR
TAS5026
GVDD
OUT_A
GND
PVDD_A
GND
PVDD_B
PVDD_B
PVDD_A
OUT_B
28
29
31
BST_B
OUT_B
30
GND
OUT_A
32
27
25
23
26
24
BST_A
GND
GVDD
20
22
19
21
6
14
15
16
12
5
1
2
3
ERR_RCVY
10
H
10
H
470 nF
4.7 k
1000
F
100 nF
PWM_AP_1
PWM_AM_1
LPCB
LPCB : TRACK IN THE PCB (1,0 mm wide and 50 mm long)
{
Voltage suppressor diodes: 1SMA33CAT
100 nF
100 nF
100 nF
100 nF
100
1.5
1.5
100 nF
33 nF
100 nF
33 nF
100 nF
100 nF
H-Bridge
Power Supply
Gate-Drive
Power Supply
External Power Supply
4.7 k
LPCB
PWM_AP
GREG
GND
M2
M1
DREG
M3
DGND
RESET
OTW
DGND
SD
DVDD
DREG_RTN
GND
PWM_BP
1.5
10 k
1.5
10 k
{
{
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
8
TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE
OF TAS5111 EVM WITH TAS5026 PROCESSOR
Figure 1
f - Frequency - Hz
20
100
1k
10k
THD+N - T
otal Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
0.001
0.1
1
20k
RL = 4
TC = 75
C
0.01
PO = 70 W
PO = 1 W
PO = 10 W
Figure 2
f - Frequency - kHz
-160
-140
-120
-100
-80
-60
-40
-20
0
0
2
4
6
8
10
12
14
16
18
20
22
-60 dB Input
TC = 75
C
TAS5026 Front End Device
Noise Amplitude - dBr
NOISE AMPLITUDE
vs
FREQUENCY
Figure 3
PO - Output Power - W
100m
RL = 4
TC = 75
C
1
10
100
0.01
0.1
1
THD+N - T
otal Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
Figure 4
VDD - Supply Voltage - V
0
10
20
30
40
50
60
70
80
90
0
4
8
12
16
20
24
28
32
TA = 75
C
P
O
- Output Power - W
OUTPUT POWER
vs
H-BRIDGE VOLTAGE
RL = 6
RL = 4
RL = 8
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
9
Figure 5
PO - Output Power - W
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
f = 1 kHz
RL = 4
TC = 75
C
- System Output Stage Efficiency - %
SYSTEM OUTPUT STAGE EFFICIENCY
vs
OUTPUT POWER
Figure 6
PO - Output Power - W
0
2
4
6
8
10
12
14
0
10
20
30
40
50
60
70
80
P
to
t - Power Loss - W
POWER LOSS
vs
OUTPUT POWER
f = 1 kHz
RL = 4
TC = 75
C
Figure 7
TC - Case Temperature -
C
60
65
70
75
80
85
90
0
20
40
60
80
100
120
140
PVDD = 29.5 V
RL = 4
P
O
- Output Power - W
OUTPUT POWER
vs
CASE TEMPERATURE
Figure 8
TJ - Junction Temperature -
C
100
110
120
130
140
150
160
170
180
190
200
0
25
50
75
100
125
r on
- On-State Resistance - m
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
10
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages,
GVDD and PVDD_X.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turnon
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal LDRs to 3.3 V.
The gate-driver LDR can be bypassed for reducing idle
loss in the device by shorting GREG to GVDD and directly
feeding in 12 V. This can be useful in an application where
thermal conduction of heat from the device is difficult.
Bypassing the LDR reduces dissipation by approximately
1 W at 30-V GVDD input.
PVDD_X is the H-bridge power supply pin. Two power
pins exist for each half-bridge to handle the current density.
It is important that the circuitry recommendations around
the PVDD_X pins are followed carefully both topology-
and layout-wise. For topology recommendations, see the
Typical System Configuration section. For layout
recommendations, see the reference design layout for the
TAS5111. Following these recommendations is important
for parameters like EMI, reliability, and performance.
POWERING UP
RESET
GVDD
PVDD_x
PWM_xP
> 1 ms
> 1 ms
NOTE: PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are at this point
not charged. To comply with the click and pop scheme and
use of non-TI TDAA modulators, it is recommended to use
a 4-k
pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor (see the Typical
TAS5111 Application Configuration section).
After GVDD has been applied, it takes approximately 800
s to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
back-end bootstrap capacitor is charged.
RESET can now be released if the modulator is powered
up and streaming valid PWM signals to the back-end
PWM_xP. Valid means a switching PWM signal which
complies with the frequency and duty cycle ranges stated
in the Recommended Operating Conditions.
A constant HIGH dc level on the PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually runs out of BST capacitor energy and might
damage the device.
An unknown state of the PWM output signals from the
modulator is not permitted, which in practice means that
the PWM processor must be powered up and initialized
before RESET is de-asserted HIGH to the back end.
POWERING DOWN
For power down of the back end, an opposite approach is
necessary. The RESET must be asserted LOW before the
valid PWM signal is removed.
When TI TDAA modulators are used with TI TDAA back
ends, the correct timing control of RESET and PWM_xP
is performed by the modulator.
PRECAUTION
The TAS5111 must always start up in the high-impedance
(Hi-Z) state. In this state, the bootstrap (BST) capacitor is
precharged by a resistor on each PWM output node to
ground. See the system configuration. This ensures that
the back end is ready for receiving PWM pulses, indicating
either HIGH- or LOW-side turnon after RESET is
de-asserted to the back end.
With the following pulldown resistor and BST capacitor
size, the charge time is:
C = 33 nF, R = 4.7
k
R
C
5 = 775.5
s
After GVDD has been applied, it takes approximately 800
s to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the
back-end BST is charged and ready. RESET can now be
released if the PWM modulator is ready and is streaming
valid PWM signals to the back end. Valid PWM signals are
switching PWM signals with a frequency between
350-400 kHz. A constant HIGH level on the PWM+ would
force the high side MOSFET ON until it eventually ran out
of BST capacitor energy. Putting the device in this
condition should be avoided.
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
11
In practice, this means that the DVDD-to-PWM processor
(front-end) should be stable and initialization should be
completed before RESET is de-asserted to the back end.
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other front-end device. The pin is open-drain with an
internal pullup to DVDD.
The logic output is, as shown in the following table, a
combination of the device state and RESET input:
SD
RESET
DESCRIPTION
0
0
Not used
0
1
Device in protection mode, i.e., UVP and/or OC
and/or OT error
1(1)
0
Device set high-impedance (Hi-Z), SD forced high
1
1
Normal operation
(1) SD is pulled high when RESET is asserted low independent of chip
state (i.e., protection mode). This is desirable to maintain
compatibility with some TI PWM front ends.
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup to DVDD.
OTW
DESCRIPTION
0
Junction temperature higher than 125
C
1
Junction temperature lower than 125
C
Overall Reporting
The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.
Table 1. Error Signal Decoding
OTW
SD
DESCRIPTION
0
0
Overtemperature error (OTE)
0
1
Overtemperature warning (OTW)
1
0
Overcurrent (OC) or undervoltage (UVP) error
1
1
Normal operation, no errors/warnings
Chip Protection
The TAS5111 protection function is implemented in a
closed loop with, for example, a system controller or other
TI PWM processor (front-end) device. The TAS5111
contains three individual systems protecting the device
against misuse. All of the error events covered result in the
output stage being set in a high-impedance state (Hi-Z) for
maximum protection of the device and connected
equipment.
The device can be recovered by toggling RESET low and
then high, after all errors are cleared.
Overcurrent (OC) Protection
The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Filter Demodulation Design in the
Application Information section of the data sheet for design
constraints.
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125
C. The OT protection circuit is shared by all
half-bridges.
Undervoltage (UV) Protection
Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.
Reset Function
The function of the reset input is twofold:
D
Reset is used for re-enabling operation after a
latching error event.
D
Reset is used for disabling output stage
switching (mute function).
In PMODEs where the reset input functions as the means
to re-enable operation after an error event, the error latch
is cleared on the falling edge of reset and normal operation
is resumed when reset goes high.
PROTECTION MODE
Autorecovery (AR) After Errors (PMODE0)
In autorecovery mode (PMODE0) the TAS5111 is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time the
device autorecovers, i.e., operation is automatically
resumed provided that the system is fully operational.
The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.
The AR system is common to both half-bridges.
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
12
Timing and Function
The function of the autorecovery circuit is as follows:
1.
An error event occurs and sets the
protection latch (output stage goes Hi-Z).
2.
The counter is started.
3.
After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).
4.
After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).
Error
Protection
Latch
Shutdown
Autorecovery
SD
PWM
Counter
AR-RESET
Figure 9. Autorecovery Function
Latching Shutdown on All Errors (PMODE1)
In latching shutdown mode, all error situations result in a
power down (output stage Hi-Z). Re-enabling can be done
by toggling the RESET pin.
All Protection Systems Disabled (PMODE2)
In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.
Table 2. Protection Mode Selection
M1
M2
PROTECTION MODE
0
0
Autorecovery after errors (PMODE 0)
0
1
Latching shutdown on all errors (PMODE 1)
1
0
All protection systems disabled (PMODE 2)
1
1
Reserved
The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.
Table 3. Output Mode Selection
M3
OUTPUT MODE
0
Bridge-tied load output stage (BTL)
1
Reserved
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS
The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application note
SLEA025.
The TDAA amplifier outputs are driven by heavy-duty
DMOS transistors in an H-bridge configuration. These
transistors are either off or fully on, which reduces the
DMOS transistor on-state resistance, R(DMOSon), and
the power dissipated in the device, thereby increasing
efficiency.
The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 10.
Output A
C1A
TAS51xx
L
Output B
L
C1B
C2
R(Load)
Figure 10. Demodulation Filter
The main purpose of the output filter is to attenuate the
high-frequency switching component of the TDAA
amplifier while preserving the signals in the audio band.
Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance
should remain stable within the range of peak current seen
at maximum output power and deliver at least 5
H of
inductance at 15 A.
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
13
If this rule is observed, the TAS5111 does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.
Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.
In general, 10-
H inductors suffice for most applications.
The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10
H.
The graph in Figure 11 displays the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5111.
Figure 11. Inductance Saturation
I - Current - A
4
5
6
7
8
9
10
11
0
5
10
15
L - Inductance -
H
INDUCTANCE
vs
CURRENT
DBF1310A
DASL983XX-1023
The selection of the capacitor that is placed across the
output of each inductor (C2
in Figure 10) is simple. To
complete the output filter, use a 0.47-
F capacitor with a
voltage rating at least twice the voltage applied to the
output stage (PVDD).
This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.
In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-
F, 50-V, SMD capacitors (X7R
or better) (C1A and C1B in Figure 10) should be added
from the output of each inductor to ground.
THERMAL INFORMATION
The thermally augmented package provided with the
TAS5111 is designed to be interfaced directly to a heatsink
using a thermal interface compound (for example,
Wakefield Engineering type 126 thermal grease.) The
heatsink then absorbs heat from the ICs and couples it to
the local air. If the heatsink is carefully designed, this
process can reach equilibrium and heat can be continually
removed from the ICs. Because of the efficiency of the
TAS5111, heatsinks are smaller than those required for
linear amplifiers of equivalent performance.
R
JA
is a system thermal resistance from junction to
ambient air. As such, it is a system parameter with roughly
the following components:
D
R
JC
(the thermal resistance from junction to
case, or in this case the metal pad)
D
Thermal grease thermal resistance
D
Heatsink thermal resistance
R
JC
has been provided in the General Information
section.
The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer's area thermal resistance (expressed in
C-in
2
/W). The area thermal resistance of the example
thermal grease with a 0.001-inch thick layer is about
0.054
C-in
2
/W. The approximate exposed pad area is
0.0164 in
2
.
Dividing the example thermal grease area resistance by
the area of the pad gives the actual resistance through the
thermal grease, 3.3
C/W.
Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Thus, for a single monaural IC, the system R
JA
= R
JC
+
thermal grease resistance + heatsink resistance.
The following table indicates modeled parameters for one
TAS5111 IC on a heatsink. The junction temperature is set
at 110
C in both cases while delivering 70 W RMS into 4-
loads with no clipping. It is assumed that the thermal
grease is about 0.001 inch thick (this is critical).
32-Pin TSSOP
Ambient temperature
25
C
Power to load
70 W
Delta T inside package
12.3
C
Delta T through thermal grease
21.1
C
Required heatsink thermal resistance
8.2
C/W
Junction temperature
110
C
System R
JA
13.2
C/W
R
JA
power dissipation
85
C
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
14
As an indication of the importance of keeping the thermal
grease layer thin, if the thermal grease layer increases to
0.002 inches thick, the required heatsink thermal
resistance changes to 2.4
C/W.
Thermal
Pad
3,91 mm
3,31 mm
4,11 mm
3,35 mm
CLICK AND POP REDUCTION
Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.
To make this system work properly, the following design
rules must be followed when using the TAS5111 back end:
D
The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.
D
The output stage must start switching from a
fully discharged output filter capacitor. Because
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
output to GND (see Typical System
Configuration).
Other things that can affect the audible click level:
D
The spectrum of the click seems to follow the
speaker impedance vs. frequency curve--the
higher the impedance, the higher the click
energy.
D
Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.
Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click is.
The following mode transitions feature click and pop
reduction.
STATE
CLICK AND
POP REDUCED
Normal(1)
Mute
Yes
Mute
Normal(1)
Yes
Normal(1)
Error recovery
(ERRCVY)
Yes
Error recovery
Normal(1)
Yes
Normal(1)
Hard Reset
No
Hard Reset
Normal(1)
Yes
(1) Normal = switching
REFERENCES
1.
TAS5000 Digital Audio PWM Processor data
manual--TI (SLAS270)
2.
True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet--TI (SLES009)
3.
True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet--TI (SLAS328)
4.
True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet--TI (SLES006)
5.
TAS5026 Six-Channel Digital Audio PWM
Processor data manual--TI (SLES041)
6.
TAS5036A Six-Channel Digital Audio PWM
Processor data manual--TI (SLES061)
7.
TAS3103 Digital Audio Processor With 3D Effects
data manual--TI (SLES038)
8.
Digital Audio Measurements application report--TI
(SLAA114)
9.
PowerPAD
Thermally Enhanced Package
technical brief--TI (SLMA002)
10. System Design Considerations for True Digital
Audio Power Amplifiers application report--TI
(SLAA117)
TAS5111
SLES049D - JULY 2003 - REVISED MARCH 2004
www.ti.com
15
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2004, Texas Instruments Incorporated
PDF 
ZIP