TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

DIGITAL AMPLIFIER POWER STAGE

FEATURES

50 W per Channel (BTL) Into 6

(Stereo)

95-dB Dynamic Range With TAS5026

Less Than 0.1% THD+N (1 W RMS Into 6

)

Less Than 0.2% THD+N (50 W RMS into 6

)

Power Efficiency Typically 90% Into 6-

Load

Self-Protecting Design (Undervoltage,
Overtemperature and Short Conditions) With
Error Reporting

Internal Gate Drive Supply Voltage Regulator

EMI Compliant When Used With
Recommended System Design

APPLICATIONS

DVD Receiver

Home Theatre

Mini/Micro Component Systems

Internet Music Appliance

DESCRIPTION

The TAS5112A is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-

speakers at up to 50 W per channel. The device
incorporates TI's PurePath Digital

technology and is

used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically 90%,
reducing the size of both the power supplies and heatsinks
needed. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5112A, safeguarding the device and speakers against
fault conditions that could damage the system.

PO - Output Power - W

100m

RL = 6

TC = 75

100

0.01

0.1

THD+N - T

otal Harmonic Distortion + Noise - %

THD + NOISE vs OUTPUT POWER

f - Frequency - Hz

100

10k

THD+N - T

otal Harmonic Distortion + Noise - %

0.001

0.1

20k

RL = 6

TC = 75

0.01

THD + NOISE vs FREQUENCY

PO = 50 W

PO = 1 W

PO = 10 W

PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

2004, Texas Instruments Incorporated

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5112A is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top), shown as follows.

GND
GND

GREG

OTW

SD_CD

SD_AB

PWM_DP

PWM_DM

RESET_CD

PWM_CM

PWM_CP

DREG_RTN

M3
M2
M1

DREG

PWM_BP

PWM_BM

RESET_AB

PWM_AM

PWM_AP

GND

DGND

GND

DVDD

GREG

GND
GND

GND
GVDD
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND
GND
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
GND

DFD PACKAGE

(TOP VIEW)

Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted(1)

TAS5112A

UNITS

DVDD TO DGND

0.3 V to 4.2 V

GVDD TO GND

33.5 V

PVDD_X TO GND (dc voltage)

33.5 V

PVDD_X TO GND (spike voltage(2))

48 V

OUT_X TO GND (dc voltage)

33.5 V

OUT_X TO GND (spike voltage(2))

48 V

BST_X TO GND (dc voltage)

48 V

BST_X TO GND (spike voltage(2))

53 V

GREG TO GND (3)

14.2 V

PWM_XP, RESET, M1, M2, M3, SD,
OTW

0.3 V to DVDD + 0.3 V

Maximum operating junction
temperature, TJ

C to 150

Storage temperature

C to 125

(1) Stresses beyond those listed under "absolute maximum ratings"

may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device
reliability.

(2) The duration of voltage spike should be less than 100 ns; see

application note SLEA025.

(3) GREG is treated as an input when the GREG pin is overdriven by

GVDD of 12 V.

Package Dissipation Ratings

PACKAGE

(

C/W)

(

C/W)

56-pin DFD TSSOP

1.14

See Note 4

(4) The TAS5112A package is thermally enhanced for conductive

cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, R

JA, a system parameter that characterizes the

thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
R

JA values are provided in the Thermal Information section. This

example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.

Ordering Information

PACKAGE

DESCRIPTION

C to 70

TAS5112ADFD

56-pin small TSSOP

For the most current specification and package
information, refer to our Web site at www.ti.com.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

Terminal Functions

TERMINAL

FUNCTION(1)

DESCRIPTION

NAME

NO.

FUNCTION(1)

DESCRIPTION

BST_A

High-side bootstrap supply (BST), external capacitor to OUT_A required

BST_B

High-side bootstrap supply (BST), external capacitor to OUT_B required

BST_C

HS bootstrap supply (BST), external capacitor to OUT_C required

BST_D

HS bootstrap supply (BST), external capacitor to OUT_D required

DGND

Digital I/O reference ground

DREG

Digital supply voltage regulator decoupling pin, capacitor connected to GND

DREG_RTN

Digital supply voltage regulator decoupling return pin

DVDD

I/O reference supply input (3.3 V)

GND

1, 2, 22, 24,

27, 28, 29, 36,

37, 48, 49, 56

Power ground

GREG

3, 26

Gate drive voltage regulator decoupling pin, capacitor to REG_GND

GVDD

30, 55

Voltage supply to on-chip gate drive and digital supply voltage regulators

M1 (TST0)

Mode selection pin

OTW

Overtemperature warning output, open drain with internal pullup resistor

OUT_A

34, 35

Output, half-bridge A

OUT_B

38, 39

Output, half-bridge B

OUT_C

46, 47

Output, half-bridge C

OUT_D

50, 51

Output, half-bridge D

PVDD_A

32, 33

Power supply input for half-bridge A

PVDD_B

40, 41

Power supply input for half-bridge B

PVDD_C

44, 45

Power supply input for half-bridge C

PVDD_D

52, 53

Power supply input for half-bridge D

PWM_AM

Input signal (negative), half-bridge A

PWM_AP

Input signal (positive), half-bridge A

PWM_BM

Input signal (negative), half-bridge B

PWM_BP

Input signal (positive), half-bridge B

PWM_CM

Input signal (negative), half-bridge C

PWM_CP

Input signal (positive), half-bridge C

PWM_DM

Input signal (negative), half-bridge D

PWM_DP

Input signal (positive), half-bridge D

RESET_AB

Reset signal, active low

RESET_CD

Reset signal, active low

SD_AB

Shutdown signal for half-bridges A and B, active-low

SD_CD

Shutdown signal for half-bridges C and D, active-low

(1) I = input, O = Output, P = Power

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

DVDD

Digital supply (1)

Relative to DGND

3.3

3.6

GVDD

Supply for internal gate drive and logic

regulators

Relative to GND

29.5

30.5

PVDD_x

Half-bridge supply

Relative to GND, RL= 6

to 8

29.5

30.5

Junction temperature

125

(1) It is recommended for DVDD to be connected to DREG via a 100-

resistor.

ELECTRICAL CHARACTERISTICS

PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-

resistor, RL = 6

, 8X fs = 384 kHz, unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

TA=25

TCase=

TA=40

TO 85

UNITS

MIN/TYP/

MAX

AC PERFORMANCE, BTL Mode, 1 kHz

RL = 8

, THD = 0.2%,

AES17 filter, 1 kHz

Typ

Output power

RL = 8

, THD = 10%, AES17

filter, 1 kHz

Typ

Output power

RL = 6

, THD = 0.2%,

AES17 filter, 1 kHz

Typ

RL = 6

, THD = 10%, AES17

filter, 1 kHz

Typ

Po = 1 W/ channel, RL = 6

AES17 filter

0.03%

Typ

THD+N

Total harmonic distortion
+ noise

Po = 10 W/channel, RL = 6

AES17 filter

0.04%

Typ

+ noise

Po = 50 W/channel, RL = 6

AES17 filter

0.2%

Typ

Output integrated voltage
noise

A-weighted, mute, RL = 6

20 Hz to 20 kHz, AES17 filter

260

Max

SNR

Signal-to-noise ratio

A-weighted, AES17 filter

Typ

Dynamic range

f = 1 kHz, A-weighted,
AES17 filter

Typ

INTERNAL VOLTAGE REGULATOR

DREG

Voltage regulator

Io = 1 mA,
PVDD = 18 V-30.5 V

3.1

Typ

GREG

Voltage regulator

Io = 1.2 mA,
PVDD = 18 V-30.5 V

13.4

Typ

IVGDD

GVDD supply current,
operating

fS = 384 kHz, no load, 50%
duty cycle

Max

IDVDD

DVDD supply current,
operating

fS = 384 kHz, no load

Max

OUTPUT STAGE MOSFETs

RDSon,LS

Forward on-resistance,
low side

TJ = 25

155

Typ

RDSon,HS

Forward on-resistance,
high side

TJ = 25

155

Typ

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

ELECTRICAL CHARACTERISTICS

PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-

resistor, RL = 6

, 8X fs = 384 kHz, unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

TA=25

TCase=

TA=40

TO 85

UNITS

MIN/TYP/

MAX

INPUT/OUTPUT PROTECTION

Vuvp,G

Undervoltage protection

Set the DUT in normal
operation mode with all the
protections enabled. Sweep
GVDD up and down. Monitor

7.4

6.9

Min

Vuvp,G

Undervoltage protection
limit, GVDD

GVDD up and down. Monitor
SD output. Record the
GREG reading when SD is
triggered.

7.4

7.9

Max

OTW

Overtemperature warning,
junction temperature

125

Typ

OTE

Overtemperature error,
junction temperature

150

Typ

Overcurrent protection

See Note 1.

6.7

Typ

STATIC DIGITAL SPECIFICATION

PWM_AP, PWM_BP, M1,
M2, M3, SD, OTW

VIH

High-level input voltage

Min

VIH

High-level input voltage

DVDD

Max

VIL

Low-level input voltage

0.8

Max

Leakage

Input leakage current

-10

Min

Leakage

Input leakage current

Max

OTW/SHUTDOWN (SD)

Internally pull up R from
OTW/SD to DVDD

22.5

Min

VOL

Low-level output voltage

IO = 4 mA

0.4

Max

(1) To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care.

See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors
for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended
to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

SYSTEM CONFIGURATION USED FOR CHARACTERIZATION

TAS5112ADFD

VALID_1

PWM PROCESSOR

TAS5026

GVDD

OUT_C

BST_D

PVDD_C

GND

PVDD_D

PVDD_C

OUT_D

GND

OUT_C

BST_C

BST_B

PVDD_B

470 nF

4.7 k

1000

100 nF

PWM_AP_1

PWM_AM_1

100 nF

1.5

100 nF

33 nF

H-Bridge

Power Supply

Gate-Drive

Power Supply

External Power Supply

4.7 k

LPCB

DREG

SD_CD

PWM_CM

RESET_CD

PWM_DP

SD_AB

PWM_DM

GREG

DREG_RTN

PWM_CP

OTW

GND

LPCB

33 nF

100 nF

1.5

PVDD_B

PVDD_A

OUT_B

GND

OUT_A

GND

OUT_B

GVDD

OUT_A

GND

PVDD_A

BST_A

470 nF

4.7 k

1000

100 nF

1.5

100 nF

33 nF

4.7 k

LPCB

33 nF

100 nF

1.5

100 nF

GND

PWM_BP

GND

PWM_AP

RESET_AB

PWM_BM

PWM_AM

GREG

DVDD

GND

DGND

ERR_RCVY

100 nF

VALID_2

PWM_AP_2

PWM_AM_2

100

100 nF

1.5

Voltage suppressor diodes: 1SMA33CAT
LPCB : Track in the PCB (1,0 mm wide and 50 mm long)

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE

OF TAS5112A EVM WITH TAS5026 PWM PROCESSOR

Figure 1

f - Frequency - Hz

100

10k

THD+N - T

otal Harmonic Distortion + Noise - %

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

0.001

0.1

20k

RL = 6

TC = 75

0.01

PO = 50 W

PO = 1 W

PO = 10 W

Figure 2

f - Frequency - kHz

-160

-140

-120

-100

-80

-60

-40

-20

RL = 6

FFT = -60 dB
TC = 75

TAS5026 Front End Device

Noise Amplitude - dBr

NOISE AMPLITUDE

FREQUENCY

Figure 3

PO - Output Power - W

100m

RL = 6

TC = 75

100

THD+N - T

otal Harmonic Distortion + Noise - %

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

0.01

0.1

Figure 4

VDD - Supply Voltage - V

TA = 75

- Output Power - W

OUTPUT POWER

H-BRIDGE VOLTAGE

RL = 6

RL = 8

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

Figure 5

PO - Output Power - W

100

10 15 20 25 30 35 40 45 50 55 60 65

f = 1 kHz
RL = 6

TC = 75

- System Output Stage Efficiency - %

SYSTEM OUTPUT STAGE EFFICIENCY

OUTPUT POWER

Figure 6

PO - Output Power - W

10 15 20 25 30 35 40 45 50 55 60 65

f = 1 kHz
RL = 6

TC = 75

t - Power Loss - W

POWER LOSS

OUTPUT POWER

Figure 7

TC - Case Temperature -

100

120

140

PVDD = 29.5 V
RL = 6

- Output Power - W

OUTPUT POWER

CASE TEMPERATURE

Channel 1

Channel 2

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

f - Frequency - Hz

Amplitude - dBr

100

50k

10k

Figure 8

RL = 6

AMPLITUDE

FREQUENCY

RL = 8

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

THEORY OF OPERATION

POWER SUPPLIES

The power device only requires two supply voltages,
GVDD and PVDD_X.

GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turn-on
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal circuitry to
3.3 V.

The gate-driver regulator can be bypassed for reducing
idle loss in the device by shorting GREG to GVDD and
directly feeding in 12.0 V. This can be useful in an
application where thermal conduction of heat from the
device is difficult.

PVDD_X is the H-bridge power supply pin. Two power pins
exists for each half-bridge to handle the current density. It
is important that the circuitry recommendations around the
PVDD_X pins are followed carefully both topology- and
layout-wise. For topology recommendations, see the
System Configuration Used for Characterization section.
Following these recommendations is important for
parameters like EMI, reliability, and performance.

POWERING UP

RESET

GVDD

PVDD_X

PWM_xP

> 1 ms

NOTE: PVDD should not be powered up before GVDD.

During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are not charged
at this point. To comply with the click and pop scheme and
use of non-TI modulators, it is recommended to use a

4.7-k

pulldown resistor on each PWM output node to

ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor.

After GVDD has been applied, it takes approximately 800

s to fully charge the BST capacitor. Within this time,

RESET must be kept low. After approximately 1 ms, the
back-end bootstrap capacitor is charged.

RESET can now be released if the modulator is powered
up and streaming valid PWM signals to the back-end
PWM_xP. Valid means a switching PWM signal which
complies with the frequency and duty cycle ranges stated
in the Recommended Operating Conditions.

A constant HIGH dc level on the PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.

An unknown state of the PWM output signals from the
modulator is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is de-asserted HIGH to
the back end.

POWERING DOWN

For power down of the back end, an opposite approach is
necessary. The RESET must be asserted LOW before the
valid PWM signal is removed.

When PWM processors are used with TI PurePath Digital
amplifiers, the correct timing control of RESET and
PWM_xP is performed by the modulator.

PRECAUTION

The TAS5112A must always start up in the
high-impedance (Hi-Z) state. In this state, the bootstrap
(BST) capacitor is precharged by a resistor on each PWM
output node to ground. See the system configuration. This
ensures that the back end is ready for receiving PWM
pulses, indicating either HIGH- or LOW-side turnon after
RESET is de-asserted to the back end.

With the following pulldown resistor and BST capacitor
size, the charge time is:

C = 33 nF, R = 4.7

5 = 775.5

After GVDD has been applied, it takes approximately 800

s to fully charge the BST capacitor. During this time,

RESET must be kept low. After approximately 1 ms the
back end BST is charged and ready. RESET can now be
released if the PWM modulator is ready and is streaming
valid PWM signals to the back end. Valid PWM signals are
switching PWM signals with a frequency between 350-400
kHz. A constant HIGH level on the PWM+ would force the
high-side MOSFET ON until it eventually ran out of BST
capacitor energy. Putting the device in this condition
should be avoided.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

In practice this means that the DVDD-to-PWM processor
(front-end) should be stable and initialization should be
completed before RESET is de-asserted to the back end.

CONTROL I/O

Shutdown Pin: SD

The SD pin functions as an output pin and is intended for
protection-mode signaling to, for example, a controller or
other front-end device. The pin is open-drain with an
internal pullup resistor to DVDD.

The logic output is, as shown in the following table, a
combination of the device state and RESET input:

RESET

DESCRIPTION

Reserved

Device in protection mode, i.e., UVP and/or OC
and/or OT error

1(2)

Device set high-impedance (Hi-Z), SD forced high

Normal operation

(2) SD is pulled high when RESET is asserted low independent

of chip state (i.e., protection mode). This is desirable to
maintain compatibility with some TI PWM front ends.

Temperature Warning Pin: OTW

The OTW pin gives a temperature warning signal when
temperature exceeds the set limit. The pin is of the
open-drain type with an internal pullup resistor to DVDD.

OTW

DESCRIPTION

Junction temperature higher than 125

Junction temperature lower than 125

Overall Reporting

The SD pin, together with the OTW pin, gives chip state
information as described in Table 1.

Table 1. Error Signal Decoding

OTW

DESCRIPTION

Overtemperature error (OTE)

Overtemperature warning (OTW)

Overcurrent (OC) or undervoltage (UVP) error

Normal operation, no errors/warnings

Chip Protection

The TAS5112A protection function is implemented in a
closed loop with, for example, a system controller and TI
PWM processor. The TAS5112A contains three individual
systems protecting the device against error conditions. All
of the error events covered result in the output stage being
set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.

The device can be recovered by toggling RESET low and
then high, after all errors are cleared.

Overcurrent (OC) Protection

The device has individual forward current protection on
both high-side and low-side power stage FETs. The OC
protection works only with the demodulation filter present
at the output. See Demodulation Filter Design in the
Application Information section of the data sheet for design
constraints.

Overtemperature (OT) Protection

A dual temperature protection system asserts a warning
signal when the device junction temperature exceeds
125

C. The OT protection circuit is shared by all

half-bridges.

Undervoltage (UV) Protection

Undervoltage lockout occurs when GVDD is insufficient
for proper device operation. The UV protection system
protects the device under power-up and power-down
situations. The UV protection circuits are shared by all
half-bridges.

Reset Function

The reset has two functions:

Reset is used for re-enabling operation after a
latching error event.

Reset is used for disabling output stage
switching (mute function).

The error latch is cleared on the falling edge of reset and
normal operation is resumed when reset goes high.

PROTECTION MODE

Autorecovery (AR) After Errors (PMODE0)

In autorecovery mode (PMODE0) the TAS5112A is
self-supported in handling of error situations. All protection
systems are active, setting the output stage in the
high-impedance state to protect the output stage and
connected equipment. However, after a short time period
the device autorecovers, i.e., operation is automatically
resumed provided that the system is fully operational.

The autorecovery timing is set by counting PWM input
cycles, i.e., the timing is relative to the switching frequency.

The AR system is common to both half-bridges.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

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Timing and Function

The function of the autorecovery circuit is as follows:

An error event occurs and sets the
protection latch (output stage goes Hi-Z).

The counter is started.

After n/2 cycles, the protection latch is
cleared but the output stage remains Hi-Z
(identical to pulling RESET low).

After n cycles, operation is resumed
(identical to pulling RESET high) (n = 512).

Error

Protection

Latch

Shutdown

Autorecovery

PWM

Counter

AR-RESET

Figure 10. Autorecovery Function

Latching Shutdown on All Errors (PMODE1)

In latching shutdown mode, all error situations result in a
power down (output stage Hi-Z). Re-enabling can be done
by toggling the RESET pin.

All Protection Systems Disabled (PMODE2)

In PMODE2, all protection systems are disabled. This
mode is purely intended for testing and characterization
purposes and thus not recommended for normal device
operation.

MODE Pins Selection

The protection mode is selected by shorting M1/M2 to
DREG or DGND according to Table 2.

Table 2. Protection Mode Selection

PROTECTION MODE

Autorecovery after errors (PMODE 0)

Latching shutdown on all errors (PMODE 1)

All protection systems disabled (PMODE 2)

Reserved

The output configuration mode is selected by shorting the
M3 pin to DREG or DGND according to Table 3.

Table 3. Output Mode Selection

OUTPUT MODE

Bridge-tied load output stage (BTL)

Reserved

APPLICATION INFORMATION

DEMODULATION FILTER DESIGN AND
SPIKE CONSIDERATIONS

The output square wave is susceptible to overshoots
(voltage spikes). The spike characteristics depend on
many elements, including silicon design and application
design and layout. The device should be able to handle
narrow spike pulses, less than 65 ns, up to 65 volts peak.
For more detailed information, see TI application note
SLEA025.

The PurePath Digital amplifier outputs are driven by
heavy-duty DMOS transistors in an H-bridge
configuration. These transistors are either off or fully on,
which reduces the DMOS transistor on-state resistance,
R

DSon

, and the power dissipated in the device, thereby

increasing efficiency.

The result is a square-wave output signal with a duty cycle
that is proportional to the amplitude of the audio signal. It
is recommended that a second-order LC filter be used to
recover the audio signal. For this application, EMI is
considered important; therefore, the selected filter is the
full-output type shown in Figure 11.

Output A

C1A

TAS51xx

Output B

C1B

R(Load)

Figure 11. Demodulation Filter

The main purpose of the output filter is to attenuate the
high-frequency switching component of the PurePath
Digital amplifier while preserving the signals in the audio
band.

Design of the demodulation filter affects the performance
of the power amplifier significantly. As a result, to ensure
proper operation of the overcurrent (OC) protection circuit
and meet the device THD+N specifications, the selection
of the inductors used in the output filter must be considered
according to the following. The rule is that the inductance

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

should remain stable within the range of peak current seen
at maximum output power and deliver at least 5

H of

inductance at 15 A.

If this rule is observed, the TAS5112A does not have
distortion issues due to the output inductors, and
overcurrent conditions do not occur due to inductor
saturation in the output filter.

Another parameter to be considered is the idle current loss
in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for
dissipation is less than 0.05.

In general, 10-

H inductors suffice for most applications.

The frequency response of the amplifier is slightly altered
by the change in output load resistance; however, unless
tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10

The graphs in Figure 12 display the inductance vs current
characteristics of two inductors that are recommended for
use with the TAS5112A.

Figure 12. Inductance Saturation

I - Current - A

L - Inductance -

INDUCTANCE

CURRENT

DFB1310A

DASL983XX-1023

The selection of the capacitor that is placed across the
output of each inductor (C2

in Figure 11) is simple. To

complete the output filter, use a 0.47-

F capacitor with a

voltage rating at least twice the voltage applied to the
output stage (PVDD).

This capacitor should be a good quality polyester dielectric
such as a Wima MKS2-047ufd/100/10 or equivalent.

In order to minimize the EMI effect of unbalanced ripple
loss in the inductors, 0.1-

F 50-V SMD capacitors (X7R or

better) (C1A and C1B in Figure 11) should be added from
the output of each inductor to ground.

THERMAL INFORMATION

The thermally augmented package provided with the
TAS5112A is designed to be interfaced directly to
heatsinks using a thermal interface compound (for
example, Wakefield Engineering type 126 thermal
grease.) The heatsink then absorbs heat from the ICs and
couples it to the local air. If the heatsink is carefully
designed, this process can reach equilibrium and heat can
be continually removed from the ICs. Because of the
efficiency of the TAS5112A, heatsinks can be smaller than
those required for linear amplifiers of equivalent
performance.

is a system thermal resistance from junction to

ambient air. As such, it is a system parameter with roughly
the following components:

(the thermal resistance from junction to

case, or in this case the metal pad)

Thermal grease thermal resistance

Heatsink thermal resistance

has been provided in the General Information

section.

The thermal grease thermal resistance can be calculated
from the exposed pad area and the thermal grease
manufacturer's area thermal resistance (expressed in

C-in

/W). The area thermal resistance of the example

thermal grease with a 0.002-inch thick layer is about 0.1

C-in

/W. The approximate exposed pad area is as

follows:

56-pin HTSSOP

0.045 in

Dividing the example thermal grease area resistance by
the surface area gives the actual resistance through the
thermal grease for both ICs inside the package:

56-pin HTSSOP

2.27

C/W

The thermal resistance of thermal pads is generally
considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance.
Neither pads nor tape should be used with either of these
two packages. A thin layer of thermal grease with careful
clamping of the heatsink is recommended. It may be
difficult to achieve a layer 0.001-inch thick or less, so the
modeling below is done with a 0.002-inch thick layer,
which may be more representative of production thermal
grease thickness.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

Heatsink thermal resistance is generally predicted by the
heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.

Thus, for a single monaural IC, the system R

= R

thermal grease resistance + heatsink resistance.

Table

4, Table 5, and Table 6 indicate modeled

parameters for one or two TAS5112A ICs on a single
heatsink. The final junction temperature is set at 110

C in

all cases. It is assumed that the thermal grease is 0.002
inch thick and that it is similar in performance to Wakefield
Type 126 thermal grease. It is important that the thermal
grease layer is

0.002 inches thick and that thermal pads

or tape are not used in the pad-to-heatsink interface due
to the high power density that results in these extreme
power cases.

Table 4. Case 1 (2

50 W Unclipped Into 6

Both Channels in Same IC)

(1)

56-Pin HTSSOP

Ambient temperature

Power to load (per channel)

50 W (unclipped)

Power dissipation

4.5 W

Delta T inside package

10.2

C, note 2

channel dissipation

Delta T through thermal grease

37.1

C, note 2

channel dissipation

Required heatsink thermal resistance

4.2

C/W

Junction temperature

110

System R

C/W

JA * power dissipation

Junction temperature

C + 25

C = 110

(1) This case represents a stereo system with only one package. See

Case 2 and Case 2A if doing a full-power, 2-channel test in a
multichannel system.

Table 5. Case 2 (2

50 W Unclipped Into 6

Channels in Separate Packages)

(1)

56-Pin HTSSOP

Ambient temperature

Power to load (per channel)

50 W (unclipped)

Power dissipation

4.5 W

Delta T inside package

5.1

Delta T through thermal grease

18.6

Required heatsink thermal resistance

6.9

C/W

Junction temperature

110

System R

C/W

JA * power dissipation

Junction temperature

C + 25

C = 110

(1) In this case, the power is separated into two packages. Note that

this allows a considerably smaller heatsink because twice as much
area is available for heat transfer through the thermal grease. For
this reason, separating the stereo channels into two ICs is
recommended in full-power stereo tests made on multichannel
systems.

Table 6. Case 2A (2

60 W Into 6

, Channels in

Separate IC Packages)

(1)

56-Pin HTSSOP

Ambient temperature

Power to load (per channel)

60 W (10% THD)

Power dissipation per channel

5.4 W

Delta T inside package

6.1

C, note 2

channel dissipation

Delta T through thermal grease

22.3

C, note 2

channel dissipation

Required heatsink thermal resistance

5.3

C/W

Junction temperature

110

System R

15.9

C/W

JA * power dissipation

Junction temperature

C + 25

C = 110

(1) In this case, the power is also separated into two packages, but

overdriving causes clipping to 10% THD. In this case, the high
power requires extreme care in attachment of the heatsink to
ensure that the thermal grease layer is

0.002 inches thick. Note

that this power level should not be attempted with both channels in
a single IC because of the high power density through the thermal
grease layer.

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

Thermal

Pad

8,20 mm
7,20 mm

3,90 mm
2,98 mm

CLICK AND POP REDUCTION

TI modulators feature a pop and click reduction system
that controls the timing when switching starts and stops.

Going from nonswitching to switching operation causes a
spectral energy burst to occur within the audio bandwidth,
which is heard in the speaker as an audible click, for
instance, after having asserted RESET LH during a
system start-up.

To make this system work properly, the following design
rules must be followed when using the TAS5112A back
end:

The relative timing between the PWM_AP/M_x
signals and their corresponding VALID_x signal
should not be skewed by inserting delays,
because this increases the audible amplitude
level of the click.

The output stage must start switching from a
fully discharged output filter capacitor. Because
the output stage prior to operation is in the
high-impedance state, this is done by having a
passive pulldown resistor on each speaker
output to GND (see System Configuration Used
for Characterization).

Other things that can affect the audible click level:

The spectrum of the click seems to follow the
speaker impedance vs. frequency curve--the
higher the impedance, the higher the click
energy.

Crossover filters used between woofer and
tweeter in a speaker can have high impedance
in the audio band, which should be avoided if
possible.

Another way to look at it is that the speaker impulse
response is a major contributor to how the click energy is
shaped in the audio band and how audible the click will be.

The following mode transitions feature click and pop
reduction.

STATE

CLICK AND

POP REDUCED

Normal(1)

Mute

Yes

Mute

Normal(1)

Yes

Normal(1)

Error recovery
(ERRCVY)

Yes

Error recovery

Normal(1)

Yes

Normal(1)

Hard Reset

Normal(1)

Yes

(1) Normal = switching

REFERENCES

TAS5000 Digital Audio PWM Processor data
manual--TI (SLAS270)

True Digital Audio Amplifier TAS5001 Digital Audio
PWM Processor data sheet--TI (SLES009)

True Digital Audio Amplifier TAS5010 Digital Audio
PWM Processor data sheet--TI (SLAS328)

True Digital Audio Amplifier TAS5012 Digital Audio
PWM Processor data sheet--TI (SLES006)

TAS5026 Six-Channel Digital Audio PWM
Processor data manual--TI (SLES041)

TAS5036A Six-Channel Digital Audio PWM
Processor data manual--TI (SLES061)

TAS3103 Digital Audio Processor With 3D Effects
data manual--TI (SLES038)

Digital Audio Measurements application report--TI
(SLAA114)

PowerPAD

Thermally Enhanced Package

technical brief--TI (SLMA002)

10. System Design Considerations for True Digital

Audio Power Amplifiers application report--TI
(SLAA117)

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

TAS5112ADCA

ACTIVE

HTSSOP

DCA

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADCAG4

ACTIVE

HTSSOP

DCA

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADCAR

ACTIVE

HTSSOP

DCA

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADCARG4

ACTIVE

HTSSOP

DCA

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADFD

ACTIVE

HTSSOP

DFD

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADFDR

ACTIVE

HTSSOP

DFD

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5112ADFDRG4

ACTIVE

HTSSOP

DFD

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

16-May-2005

Addendum-Page 1

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