TAS5112
SLES048C - JULY 2003 - REVISED MARCH 2004
DIGITAL AMPLIFIER POWER STAGE
TM
FEATURES
D
50 W per Channel (BTL) Into 6
(Stereo)
D
95-dB Dynamic Range With TAS5026
D
Less Than 0.1% THD+N (1 W RMS Into 6
)
D
Less Than 0.2% THD+N (50 W RMS into 6
)
D
Power Efficiency Typically 90% Into 6-
Load
D
Self-Protecting Design (Undervoltage,
Overtemperature and Short Conditions) With
Error Reporting
D
Internal Gate Drive Supply Voltage Regulator
D
EMI Compliant When Used With
Recommended System Design
APPLICATIONS
D
DVD Receiver
D
Home Theatre
D
Mini/Micro Component Systems
D
Internet Music Appliance
DESCRIPTION
The TAS5112 is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-
speakers at up to 50 W per channel. The device
incorporates TI's PurePath Digital
t
technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.
The efficiency of this digital amplifier is typically 90%,
reducing the size of both the power supplies and heatsinks
needed. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5112, safeguarding the device and speakers against
fault conditions that could damage the system.
PO - Output Power - W
100m
RL = 6
TC = 75
C
1
10
100
0.01
0.1
1
THD+N - T
otal Harmonic Distortion + Noise - %
THD + NOISE vs OUTPUT POWER
f - Frequency - Hz
20
100
1k
10k
THD+N - T
otal Harmonic Distortion + Noise - %
0.001
0.1
1
20k
RL = 6
TC = 75
C
0.01
THD + NOISE vs FREQUENCY
PO = 50 W
PO = 1 W
PO = 10 W
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2004, Texas Instruments Incorporated
TAS5112
SLES048C - JULY 2003 - REVISED MARCH 2004
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5112 is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top), shown as follows.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
GREG
OTW
SD_CD
SD_AB
PWM_DP
PWM_DM
RESET_CD
PWM_CM
PWM_CP
DREG_RTN
M3
M2
M1
DREG
PWM_BP
PWM_BM
RESET_AB
PWM_AM
PWM_AP
GND
DGND
GND
DVDD
GREG
GND
GND
GND
GVDD
BST_D
PVDD_D
PVDD_D
OUT_D
OUT_D
GND
GND
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD
GND
DFD PACKAGE
(TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TAS5112
UNITS
DVDD TO DGND
0.3 V to 4.2 V
GVDD TO GND
33.5 V
PVDD_X TO GND (dc voltage)
33.5 V
PVDD_X TO GND (spike voltage(2))
48 V
OUT_X TO GND (dc voltage)
33.5 V
OUT_X TO GND (spike voltage(2))
48 V
BST_X TO GND (dc voltage)
48 V
BST_X TO GND (spike voltage(2))
53 V
GREG TO GND (3)
14.2 V
PWM_XP, RESET, M1, M2, M3, SD,
OTW
0.3 V to DVDD + 0.3 V
Maximum operating junction
temperature, TJ
40
C to 150
C
Storage temperature
40
C to 125
C
(1) Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device
reliability.
(2) The duration of voltage spike should be less than 100 ns.
(3) GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V.
ORDERING INFORMATION
TA
PACKAGE
DESCRIPTION
0
C to 70
C
TAS5112DFD
56-pin small TSSOP
(1) For the most current specification and package information, refer to
our Web site at www.ti.com.
PACKAGE DISSIPATION RATINGS
PACKAGE
R
JC
(
C/W)
R
JA
(
C/W)
56-pin DAD TSSOP
1.14
See Note 1
(1) The TAS5112 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, R
JA, a system parameter that characterizes the
thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
R
JA values are provided in the Thermal Information section. This
example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.
TAS5112
SLES048C - JULY 2003 - REVISED MARCH 2004
www.ti.com
3
Terminal Functions
TERMINAL
FUNCTION(1)
DESCRIPTION
NAME
NO.
FUNCTION(1)
DESCRIPTION
BST_A
31
P
High-side bootstrap supply (BST), external capacitor to OUT_A required
BST_B
42
P
High-side bootstrap supply (BST), external capacitor to OUT_B required
BST_C
43
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
54
P
HS bootstrap supply (BST), external capacitor to OUT_D required
DGND
23
P
Digital I/O reference ground
DREG
16
P
Digital supply voltage regulator decoupling pin, capacitor connected to GND
DREG_RTN
12
P
Digital supply voltage regulator decoupling return pin
DVDD
25
P
I/O reference supply input (3.3 V)
GND
1, 2, 22, 24,
27, 28, 29, 36,
37, 48, 49, 56
P
Power ground
GREG
3, 26
P
Gate drive voltage regulator decoupling pin, capacitor to REG_GND
GVDD
30, 55
P
Voltage supply to on-chip gate drive and digital supply voltage regulators
M1 (TST0)
15
I
Mode selection pin
M2
14
I
Mode selection pin
M3
13
I
Mode selection pin
OTW
4
O
Overtemperature warning output, open drain with internal pullup resistor
OUT_A
34, 35
O
Output, half-bridge A
OUT_B
38, 39
O
Output, half-bridge B
OUT_C
46, 47
O
Output, half-bridge C
OUT_D
50, 51
O
Output, half-bridge D
PVDD_A
32, 33
P
Power supply input for half-bridge A
PVDD_B
40, 41
P
Power supply input for half-bridge B
PVDD_C
44, 45
P
Power supply input for half-bridge C
PVDD_D
52, 53
P
Power supply input for half-bridge D
PWM_AM
20
I
Input signal (negative), half-bridge A
PWM_AP
21
I
Input signal (positive), half-bridge A
PWM_BM
18
I
Input signal (negative), half-bridge B
PWM_BP
17
I
Input signal (positive), half-bridge B
PWM_CM
10
I
Input signal (negative), half-bridge C
PWM_CP
11
I
Input signal (positive), half-bridge C
PWM_DM
8
I
Input signal (negative), half-bridge D
PWM_DP
7
I
Input signal (positive), half-bridge D
RESET_AB
19
I
Reset signal, active low
RESET_CD
9
I
Reset signal, active low
SD_AB
6
O
Shutdown signal for half-bridges A and B, active-low
SD_CD
5
O
Shutdown signal for half-bridges C and D, active-low
(1) I = input, O = Output, P = Power
TAS5112
SLES048C - JULY 2003 - REVISED MARCH 2004
www.ti.com
4
FUNCTIONAL BLOCK DIAGRAM
GREG
GVDD
GREG
DREG_RTN
Timing
Control
Gate
Drive
PWM_AP
OUT_A
GND
PVDD_A
BST_A
PWM
Receiver
OUT_B
GND
PVDD_B
GREG
Protection A
Protection B
PWM_BP
RESET
GREG
BST_B
DREG
To Protection
Blocks
OTW
SD
DREG
DREG_RTN
GREG
DREG
Gate
Drive
Gate
Drive
Gate
Drive
GREG
OT
Protection
UVP
PWM
Receiver
Timing
Control
This diagram shows one channel.
TAS5112
SLES048C - JULY 2003 - REVISED MARCH 2004
www.ti.com
5
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
DVDD
Digital supply (1)
Relative to DGND
3
3.3
3.6
V
GVDD
Supply for internal gate drive and logic
regulators
Relative to GND
16
29.5
30.5
V
PVDD_x
Half-bridge supply
Relative to GND, RL= 6
to 8
0
29.5
30.5
V
TJ
Junction temperature
0
125
_
C
(1) It is recommended for DVDD to be connected to DREG via a 100-
resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-
resistor, RL = 6
, 8X fs = 384 kHz, unless otherwise noted
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
TA=25
C
TA=25
C
TCase=
75
C
TA=40
C
TO 85
C
UNITS
MIN/TYP/
MAX
AC PERFORMANCE, BTL Mode, 1 kHz
RL = 8
, THD = 0.2%,
AES17 filter, 1 kHz
40
W
Typ
Po
Output power
RL = 8
, THD = 10%, AES17
filter, 1 kHz
50
W
Typ
Po
Output power
RL = 6
, THD = 0.2%,
AES17 filter, 1 kHz
50
W
Typ
RL = 6
, THD = 10%, AES17
filter, 1 kHz
62
W
Typ
Po = 1 W/ channel, RL = 6
,
AES17 filter
0.03%
Typ
THD+N
Total harmonic distortion
+ noise
Po = 10 W/channel, RL = 6
,
AES17 filter
0.04%
Typ
+ noise
Po = 50 W/channel, RL = 6
,
AES17 filter
0.2%
Typ
Vn
Output integrated voltage
noise
A-weighted, mute, RL = 6
,,
20 Hz to 20 kHz, AES17 filter
260
V
Max
SNR
Signal-to-noise ratio
A-weighted, AES17 filter
96
dB
Typ
DR
Dynamic range
f = 1 kHz, A-weighted,
AES17 filter
96
dB
Typ
INTERNAL VOLTAGE REGULATOR
DREG
Voltage regulator
Io = 1 mA,
PVDD = 18 V-30.5 V
3.1
V
Typ
GREG
Voltage regulator
Io = 1.2 mA,
PVDD = 18 V-30.5 V
13.4
V
Typ
IVGDD
GVDD supply current,
operating
fS = 384 kHz, no load, 50%
duty cycle
24
mA
Max
IDVDD
DVDD supply current,
operating
fS = 384 kHz, no load
1
5
mA
Max
OUTPUT STAGE MOSFETs
Ron,LS
Forward on-resistance,
low side
TJ = 25
C
155
m
Typ
Ron,HS
Forward on-resistance,
high side
TJ = 25
C
155
m
Typ
PDF 
ZIP