TAS5152
SLES127 - FEBRUARY 2005
STEREO DIGITAL AMPLIFIER POWER STAGE
TM
FEATURES
D
2
125 W at 10% THD+N Into 4-
W
BTL
D
2
98 W at 10% THD+N Into 6-
W
BTL
D
2
76 W at 10% THD+N Into 8-
W
BTL
D
4
45 W at 10% THD+N Into 3-
W
SE
D
4
35 W at 10% THD+N Into 4-
W
SE
D
1
192 W at 10% THD+N Into 3-
W
PBTL
D
1
240 W at 10% THD+N Into 2-
W
PBTL
D
>100 dB SNR (A-Weighted)
D
<0.1% THD+N at 1 W
D
Thermally Enhanced Package Option:
- DKD (36-Pin PSOP3)
D
High-Efficiency Power Stage (>90%) With
140-m
W
Output MOSFETs
D
Power-On Reset for Protection on Power Up
Without Any Power-Supply Sequencing
D
Integrated Self-Protection Circuits Including:
- Undervoltage
- Overtemperature
- Overload
- Short Circuit
D
Error Reporting
D
EMI Compliant When Used With
Recommended System Design
D
Intelligent Gate Drive
APPLICATIONS
D
Mini/Micro Audio System
D
DVD Receiver
D
Home Theater
DESCRIPTION
The TAS5152 is a third-generation, high-performance,
integrated stereo digital amplifier power stage with
improved protection system. The TAS5152 is capable
of driving a 4-
bridge-tied load (BTL) at up to 125 W
per channel with low integrated noise at the output, low
THD+N performance, and low idle power dissipation.
A low-cost, high-fidelity audio system can be built using
a TI chipset, comprised of a modulator (e.g., TAS5508)
and the TAS5152. This system only requires a simple
passive LC demodulation filter to deliver high-quality,
high-efficiency audio amplification with proven EMI
compliance. This device requires two power supplies,
12 V for GVDD and VDD, and 35 V for PVDD. The
TAS5152 does not require power-up sequencing due to
internal power-on reset. The efficiency of this digital
amplifier is greater than 90% into 6
, which enables the
use of smaller power supplies and heatsinks.
The TAS5152 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overcurrent protection, undervoltage protection, and
overtemperature protection. The TAS5152 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the
demodulation output filter.
PVDD - Supply Voltage - V
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0
5
10
15
20
25
30
35
P
O
- Output Power - W
BTL OUTPUT POWER vs SUPPLY VOLTAGE
8
4
TC = 75
C
THD+N @ 10%
6
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2005, Texas Instruments Incorporated
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
The TAS5152 is available in a 36-pin PSOP3 (DKD)
thermally enhanced package. The package contains a
heat slug that is located on the top side of the device for
convenient thermal coupling to the heatsink.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
DKD PACKAGE
(TOP VIEW)
MODE Selection Pins
MODE PINS
PWM INPUT
OUTPUT
CONFIGU-
PROTECTION
SCHEME
M3
M2
M1
CONFIGU-
RATION
SCHEME
0
0
0
2N (1) AD/BD
modulation
2 channels
BTL output
BTL mode (2)
0
0
1
Reserved
0
1
0
1N (1) AD
modulation
2 channels
BTL output
BTL mode (2)
0
1
1
1N (1) AD
modulation
1 channel
PBTL output
PBTL mode.
Only PWM_A
input is used.
1
0
0
1N (1) AD
modulation
4 channels
SE output
Protection works
similarly to BTL
mode (2). Only
difference in SE
mode is that
OUT_x is Hi-Z
instead of a
pulldown through
internal pulldown
resistor.
1
0
1
1
1
0
Reserved
1
1
1
Reserved
(1) The 1N and 2N naming convention is used to indicate the required
number of PWM lines to the power stage per channel in a specific
mode.
(2) An overload protection (OLP) occurring on A or B causes both
channels to shut down. An OLP on C or D works similarly. Global
errors like overtemperature error (OTE), undervoltage protection
(UVP) and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings
(1)
PARAMETER
TAS5152DKD
R
JC (
C/W)--2 BTL or 4 SE
channels (8 transistors)
1.28
R
JC
C/W)--1 BTL or 2 SE
channel(s) (4 transistors)
2.56
R
JC (
C/W)--(1 transistor)
8.6
Pad area (2)
80 mm2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) R
CH is an important consideration. Assume a 2-mil thickness of
typical thermal grease between the pad area and the heatsink. The
R
CH with this condition is 0.8
C/W for the DKD package and
1.8
C/W for the DDV package.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
3
Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
TAS5152
VDD to AGND
0.3 V to 13.2 V
GVDD_X to AGND
0.3 V to 13.2 V
PVDD_X to GND_X (2)
0.3 V to 50 V
OUT_X to GND_X (2)
0.3 V to 50 V
BST_X to GND_X (2)
0.3 V to 63.2 V
VREG to AGND
0.3 V to 4.2 V
GND_X to GND
0.3 V to 0.3 V
GND_X to AGND
0.3 V to 0.3 V
GND to AGND
0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to
AGND
0.3 V to 4.2 V
RESET_X, SD, OTW to AGND
0.3 V to 7 V
Maximum continuous sink current (SD,
OTW)
9 mA
Maximum operating junction
temperature range, TJ
0
C to 125
C
Storage temperature
40
_
C to 125
_
C
Lead temperature, 1,6 mm (1/16 inch)
from case for 10 seconds
260
_
C
Minimum pulse width low
50 ns
(1) Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device
reliability.
(2) These voltages represent the dc voltage + peak ac waveform
measured at the terminal of the device in all conditions.
Ordering Information
TA
PACKAGE
DESCRIPTION
0
C to 70
C
TAS5152DKD
36-pin PSOP3
For the most current specification and package
information, see the TI Web site at www.ti.com.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
4
Terminal Functions
TERMINAL
FUNCTION (1)
DESCRIPTION
NAME
NO.
FUNCTION (1)
DESCRIPTION
AGND
9
P
Analog ground
BST_A
35
P
HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B
28
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C
27
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
20
P
HS bootstrap supply (BST), external capacitor to OUT_D required
GND
8
P
Ground
GND_A
32
P
Power ground for half-bridge A
GND_B
31
P
Power ground for half-bridge B
GND_C
24
P
Power ground for half-bridge C
GND_D
23
P
Power ground for half-bridge D
GVDD_A
36
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_B
1
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_C
18
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
GVDD_D
19
P
Gate-drive voltage supply requires 0.1-
F capacitor to AGND
M1
13
I
Mode selection pin
M2
12
I
Mode selection pin
M3
11
I
Mode selection pin
OC_ADJ
7
O
Analog overcurrent programming pin requires resistor to ground
OTW
2
O
Overtemperature warning signal, open drain, active-low
OUT_A
33
O
Output, half-bridge A
OUT_B
30
O
Output, half-bridge B
OUT_C
25
O
Output, half-bridge C
OUT_D
22
O
Output, half-bridge D
PVDD_A
34
P
Power supply input for half-bridge A requires close decoupling of 0.1-
F capacitor to
GND_A
PVDD_B
29
P
Power supply input for half-bridge B requires close decoupling of 0.1-
F capacitor to
GND_B
PVDD_C
26
P
Power supply input for half-bridge C requires close decoupling of 0.1-
F capacitor to
GND_C
PVDD_D
21
P
Power supply input for half-bridge D requires close decoupling of 0.1-
F capacitor to
GND_D
PWM_A
4
I
Input signal for half-bridge A
PWM_B
6
I
Input signal for half-bridge B
PWM_C
14
I
Input signal for half-bridge C
PWM_D
16
I
Input signal for half-bridge D
RESET_AB
5
I
Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD
15
I
Reset signal for half-bridge C and half-bridge D, active-low
SD
3
O
Shutdown signal, open drain, active-low
VDD
17
P
Power supply for digital voltage regulator requires 0.1-
F capacitor to GND.
VREG
10
P
Digital regulator supply filter pin requires 0.1-
F capacitor to AGND
(1) I = input, O = Output, P = Power
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
5
SYSTEM BLOCK DIAGRAM
2nd-Order L-C
Output Filter
for Each
Half-Bridge
Bootstrap
Capacitors
2-Channel
H-Bridge
BTL Mode
System
Microcontroller
OUT_A
OUT_B
OUT_C
OUT_D
BST_A
BST_B
BST_C
BST_D
RESET_AB
RESET_CD
System
Power
Supply
Hardwire
Mode
Control
PVDD
GVDD (12 V)/VDD (12 V)
GND
Hardwire
OC Limit
M1
M3
PVDD
Power
Supply
Decoupling
35 V
12 V
GND
VAC
PWM_A
PWM_C
PWM_D
PWM_B
VALID
M2
Left-
Channel
Output
Right-
Channel
Output
Input
H-Bridge 1
Input
H-Bridge 2
GVDD
VDD
VREG
Power Supply
Decoupling
4
PVDD_A, B, C, D
GND_A, B, C, D
GVDD_A, B, C, D
4
4
VDD
GND
VREG
AGND
OC_ADJ
Bootstrap
Capacitors
2nd-Order L-C
Output Filter
for Each
Half-Bridge
SD
OTW
Output
H-Bridge 2
Output
H-Bridge 1
OTW
SD
TAS5508
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
6
FUNCTIONAL BLOCK DIAGRAM
Temp.
Sense
M1
M2
RESET_AB
SD
OTW
AGND
OC_ADJ
VREG
VREG
VDD
M3
Power
On
Reset
Under-
voltage
Protection
GND
PWM_D
OUT_D
GND_D
PVDD_D
BST_D
Timing
Gate
Drive
PWM
Rcv.
Overload
Protection
Isense
GVDD_D
RESET_CD
4
Protection
and
I/O Logic
PWM_C
OUT_C
GND_C
PVDD_C
BST_C
Timing
Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_C
PWM_B
OUT_B
GND_B
PVDD_B
BST_B
Timing
Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_B
PWM_A
OUT_A
GND_A
PVDD_A
BST_A
Timing
Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_A
Ctrl.
BTL/PBTL-Configuration
Pulldown Resistor
BTL/PBTL-Configuration
Pulldown Resistor
BTL/PBTL-Configuration
Pulldown Resistor
BTL/PBTL-Configuration
Pulldown Resistor
Internal Pullup
Resistors to VREG
TAS5152
SLES127 - FEBRUARY 2005
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7
RECOMMENDED OPERATING CONDITIONS
CONDITIONS
MIN
NOM
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
0
35
37
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator input
DC supply voltage
10.8
12
13.2
V
RL (BTL)
Output filter: L = 10
H, C = 470 nF
3
4
RL (SE)
Load impedance
Output filter: L = 10
H, C = 470 nF
Output AD modulation, switching
frequency > 350 kHz
2
3
RL (PBTL)
Load impedance
Output AD modulation, switching
frequency > 350 kHz
1.5
2
LOutput (BTL)
Minimum output inductance under
10
LOutput (SE)
Output-filter inductance
Minimum output inductance under
short-circuit condition
10
H
LOutput (PBTL)
Output-filter inductance
short-circuit condition
10
H
FPWM
PWM frame rate
192
384
432
kHz
TJ
Junction temperature
0
125
_
C
AUDIO SPECIFICATIONS (BTL)
PVDD_X = 35 V, GVDD = VDD = 12 V, BTL mode, RL = 4
, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75
C,
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
TAS5152
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
RL =
4
,
10% THD, clipped input
signal
125
RL = 6
,
10% THD, clipped input
signal
98
Po
Power output per channel
RL = 8
,
10% THD, clipped input
signal
76
W
Po
Power output per channel
RL =
4
, 0 dBFS,
unclipped input
signal
96
W
RL = 6
, 0 dBFS,
unclipped input
signal
72
RL = 8
,
0 dBFS,
unclipped input
signal
57
THD+N
Total harmonic distortion + noise
0 dBFS
0.3
%
THD+N
Total harmonic distortion + noise
1 W
0.1
%
Vn
Output integrated noise
A-weighted
145
V
SNR
Signal-to-noise ratio (1)
A-weighted
102
dB
DNR
Dynamic range
A-weighted, input level = 60 dBFS
using TAS5508 modulator
102
dB
DNR
Dynamic range
A-weighted, input level = 60 dBFS
using TAS5518 modulator
110
dB
Pidle
Power dissipation due to idle losses (IPVDDx)
PO = 0 W, 2 channels switching (2)
2
W
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
TAS5152
SLES127 - FEBRUARY 2005
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8
AUDIO SPECIFICATIONS (Single-Ended Output)
PVDD_X = 35 V, GVDD = VDD = 12 V, SE mode, RL = 4
, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75
C,
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
TAS5152
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
RL =
3
,
10% THD, clipped input
signal
45
Po
Power output per channel
RL = 4
,
10% THD, clipped input
signal
35
W
Po
Power output per channel
RL =
3
, 0 dBFS,
unclipped input
signal
35
W
RL = 4
, 0 dBFS,
unclipped input
signal
25
THD+N
Total harmonic distortion + noise
0 dBFS
0.2
%
THD+N
Total harmonic distortion + noise
1 W
0.1
%
Vn
Output integrated noise
A-weighted
90
V
SNR
Signal-to-noise ratio (1)
A-weighted
100
dB
DNR
Dynamic range
A-weighted, input level = 60 dBFS
using TAS5508 modulator
100
dB
Pidle
Power dissipation due to idle losses (IPVDDx)
PO = 0 W, 4 channels switching (2)
2
W
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATIONS (PBTL)
PVDD_X = 35 V, GVDD = VDD = 12 V, PBTL mode, RL = 3
, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature =
75
C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index
limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
TAS5152
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
RL =
3
,
10% THD, clipped input
signal
192
Po
Power output per channel
RL = 2
,
10% THD, clipped input
signal
240
W
Po
Power output per channel
RL =
3
, 0 dBFS,
unclipped input
signal
145
W
RL = 2
, 0 dBFS,
unclipped input
signal
190
THD+N
Total harmonic distortion + noise
0 dBFS
0.2
%
THD+N
Total harmonic distortion + noise
1 W
0.1
%
Vn
Output integrated noise
A-weighted
160
V
SNR
Signal-to-noise ratio (1)
A-weighted
102
dB
DNR
Dynamic range
A-weighted, input level = 60 dBFS
using TAS5508 modulator
102
dB
DNR
Dynamic range
A-weighted, input level = 60 dBFS
using TAS5518 modulator
110
dB
Pidle
Power dissipation due to idle losses (IPVDDx)
PO = 0 W, 1 channel switching (2)
2
W
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
9
ELECTRICAL CHARACTERISTICS
RL= 4
. FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
TAS5152
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Internal Voltage Regulator and Current Consumption
VREG
Voltage regulator, only used as a reference node
VDD = 12 V
3
3.3
3.6
V
IVDD
VDD supply current
Operating, 50% duty cycle
7
17
mA
IVDD
VDD supply current
Idle, reset mode
6
11
mA
IGVDD_x
Gate supply current per half-bridge
50% duty cycle
5
16
mA
IGVDD_x
Gate supply current per half-bridge
Reset mode
0.3
1
mA
IPVDD_x
Half-bridge idle current
50% duty cycle, without
output filter or load
15
25
mA
IPVDD_x
Half-bridge idle current
Reset mode, no switching
7
25
A
Output Stage MOSFETs
RDSon,LS
Drain-to-source resistance, LS
TJ
=
25
C, includes
metallization resistance,
GVDD = 12 V
140
155
m
RDSon,HS Drain-to-source resistance, HS
TJ
=
25
C, includes
metallization resistance,
GVDD = 12 V
140
155
m
TAS5152
SLES127 - FEBRUARY 2005
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10
ELECTRICAL CHARACTERISTICS (continued)
RL= 4
. FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
TAS5152
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I/O Protection
V
uvp,G
Undervoltage protection limit, GVDD_x
9.8
V
V
uvp,hyst
(1)
Undervoltage protection hysteresis
250
mV
OTW(1)
Overtemperature warning
115
125
135
_
C
OTWHYST(1)
Temperature drop needed below OTW temp. for
OTW to be inactive after the OTW event
25
_
C
OTE(1)
Overtemperature error
145
155
165
_
C
OTE-OTW
differential
(1)
OTE-OTW differential
30
_
C
OTEHYST(1)
Temperature drop needed below OTE temp. for
SD to be released following an OTE event
25
_
C
OLPC
Overload protection counter
Fpwm = 384 kHz
1.25
ms
IOC
Overcurrent limit protection
Resistor-programmable, high
end, ROCP = 15 k
8.5
10.8
11.8
A
IOCT
Overcurrent response time
210
ns
ROCP
OC programming resistor range
Resistor tolerance = 5%
15
69
k
RPD
Internal pulldown resistor at the output of each
half-bridge
Connected when RESET is
active to provide bootstrap
capacitor charge. Not used in
SE mode
2.5
k
Static Digital Specifications
VIH
High-level input voltage
PWM_A, PWM_B, PWM_C,
PWM_D, M1, M2, M3,
2
V
VIL
Low-level input voltage
PWM_D, M1, M2, M3,
RESET_AB, RESET_CD
0.8
V
Leakage
Input leakage current
10
10
A
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW to VREG, SD to
VREG
20
26
32
k
Internal pullup resistor
3
3.3
3.6
VOH
High-level output voltage
External pullup of 4.7 k
to
5 V
4.5
5
V
VOL
Low-level output voltage
IO = 4 mA
0.2
0.4
V
FANOUT
Device fanout OTW , SD
No external pullup
30
Devices
(1) Specified by design
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
11
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
Figure 1
PO - Output Power - W
10
1
THD+N - T
otal Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
0.01
0.1
10
1
TC = 75
C
PVDD = 35 V
One Channel
100
4
6
8
PVDD - Supply Voltage - V
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0
5
10
15
20
25
30
35
P
O
- Output Power - W
OUTPUT POWER
vs
SUPPLY VOLTAGE
8
4
TC = 75
C
THD+N @ 10%
6
Figure 2
Figure 3
PVDD - Supply Voltage - V
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0
5
10
15
20
25
30
35
P
O
- Output Power - W
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
8
4
TC = 75
C
6
PO - Output Power - W
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75 100 125 150 175 200 225 250
Efficiency - %
SYSTEM EFFICIENCY
vs
OUTPUT POWER
TC = 25
C
Two Channels
Figure 4
6
4
8
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
12
Figure 5
PO - Output Power - W
0
5
10
15
20
25
30
35
40
45
50
0
25
50
75 100 125 150 175 200 225 250
Power Loss - W
SYSTEM POWER LOSS
vs
OUTPUT POWER
6
4
8
TC = 25
C
Figure 6
TC - Case Temperature -
C
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
10
20
30
40
50
60
70
80
90 100 110 120
P
O
- Output Power - W
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
8
4
THD+N @10%
6
Figure 7
f - Frequency - kHz
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
2
4
6
8
10
12
14
16
18
20
22
Noise Amplitude - dBr
NOISE AMPLITUDE
vs
FREQUENCY
TC = 75
C
60 dB
1 kHz
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
13
TYPICAL CHARACTERISTICS, SE CONFIGURATION
Figure 8
PO - Output Power - W
10
1
THD+N - T
otal Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
0.01
0.1
10
1
TC = 75
C
PVDD = 35 V
One Channel
3
4
50
Figure 9
PVDD - Supply Voltage - V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
P
O
- Output Power - W
OUTPUT POWER
vs
SUPPLY VOLTAGE
4
TC = 75
C
THD+N @ 10%
3
TC - Case Temperature -
C
0
5
10
15
20
25
30
35
40
45
50
55
60
10
20
30
40
50
60
70
80
90 100 110 120
P
O
- Output Power - W
OUTPUT POWER
vs
CASE TEMPERATURE
4
THD+N@ 10%
3
Figure 10
TAS5152
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www.ti.com
14
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
Figure 11
PO - Output Power - W
10
1
THD+N - T
otal Harmonic Distortion + Noise - %
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
0.01
0.1
10
1
TC = 75
C
PVDD = 35 V
One Channel
2
3
300
100
PVDD - Supply Voltage - V
0
20
40
60
80
100
120
140
160
180
200
220
240
260
0
5
10
15
20
25
30
35
P
O
- Output Power - W
OUTPUT POWER
vs
SUPPLY VOLTAGE
3
TC = 75
C
THD+N @ 10%
2
Figure 12
100
120
140
160
180
200
220
240
260
280
300
10
20
30
40
50
60
70
80
90 100 110 120
Figure 13
TC - Case Temperature -
C
P
O
- Output Power - W
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
THD+N @ 10%
2
3
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
15
VALID
GVDD
10
10
10
F
100 nF
GVDD
1
100 nF
BKND_ERR
PWM_P_1
PWM_M_1
PWM_P_2
PWM_M_2
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
22 k
100 nF
33 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000
F
50 V
PVDD
470 nF
100 V
10
H@10 A
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
50 V
100 nF
50 V
3.3
10 nF
50 V
10 nF
50 V
1000
F
50 V
PVDD
3.3
100 nF
50 V
47
F
50 V
47
F
50 V
47
F
50 V
10
F
100 nF
100 nF
100 nF
10
H@10 A
TAS5152DKD
0
Optional
TAS5508
10
10
47
F
50 V
470 nF
100 V
10
H@10 A
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
50 V
100 nF
50 V
10
H@10 A
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
16
VALID
GVDD
10
10
10
F
100 nF
GVDD
1
100 nF
BKND_ERR
PWM_P_1
PWM_P_2
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
22 k
100 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000
F
50 V
PVDD
470 nF
100 V
10
H@10 A
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
50 V
50 nF
100 V
3.3
10 nF
50 V
10 nF
50 V
1000
F
50 V
PVDD
3.3
100 nF
50 V
47
F
50 V
47
F
50 V
47
F
50 V
10
F
100 nF
100 nF
100 nF
10
H@10 A
TAS5152DKD
0
Optional
TAS5508
10
10
47
F
50 V
470 nF
100 V
10
H@10 A
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
50 V
100 nF
50 V
10
H@10 A
33 nF
No connect
No connect
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
17
PVDD/2
PVDD/2
PVDD/2
PVDD/2
VALID
GVDD
10
10
10
F
100 nF
GVDD
1
100 nF
BKND_ERR
PWM_P_1
PWM_P_2
PWM_P_3
PWM_P_4
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
39 k
100 nF
33 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000
F
50 V
PVDD
10
H@10 A
3.3
10 nF
50 V
10 nF
50 V
1000
F
50 V
PVDD
3.3
100 nF
50 V
47
F
50 V
47
F
50 V
47
F
50 V
10
F
100 nF
100 nF
100 nF
10
H@10 A
TAS5152DKD
0
Optional
TAS5508
10
10
47
F
50 V
10
H@10 A
10
H@10 A
10 nF
50 V
3.3
100 nF
100 V
10 nF @ 50 V
3.3
100 nF
100 V
1
F
50 V
A
B
C
D
220
F
50 V
220
F
50 V
PVDD
D
C
2.7 k
10 nF
50 V
3.3
100 nF
100 V
10 nF @ 50 V
3.3
100 nF
100 V
1
F
50 V
220
F
50 V
220
F
50 V
PVDD
10 nF
50 V
3.3
100 nF
100 V
10 nF @ 50 V
3.3
100 nF
100 V
1
F
50 V
220
F
50 V
220
F
50 V
PVDD
10 nF
50 V
3.3
100 nF
100 V
10 nF @ 50 V
3.3
100 nF
100 V
1
F
50 V
220
F
50 V
220
F
50 V
PVDD
2.7 k
2.7 k
2.7 k
A
B
Figure 16. Typical SE Application
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
18
VALID
GVDD
10
10
10
F
100 nF
GVDD
1
100 nF
BKND_ERR
PWM_P_1
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
30 k
100 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000
F
50 V
PVDD
10
H@10 A
3.3
10 nF
50 V
10 nF
50 V
1000
F
50 V
PVDD
3.3
100 nF
50 V
47
F
50 V
47
F
50 V
47
F
50 V
10
F
100 nF
100 nF
100 nF
10
H@10 A
TAS5152DKD
0
Optional
TAS5508
10
10
47
F
50 V
10
H@10 A
10
H@10 A
33 nF
PWM_M_1
470 nF
63 V
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
100 V
100 nF
100 V
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
19
VALID
GVDD
10
10
10
F
100 nF
GVDD
1
100 nF
BKND_ERR
PWM_P_1
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
RESET_CD
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
36
35
34
33
23
19
20
21
22
24
25
26
27
28
32
31
30
29
GND_D
GVDD_D
GVDD_A
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
30 k
100 nF
33 nF
33 nF
33 nF
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000
F
50 V
PVDD
10
H@10 A
3.3
10 nF
50 V
10 nF
50 V
1000
F
50 V
PVDD
3.3
100 nF
50 V
47
F
50 V
47
F
50 V
47
F
50 V
10
F
100 nF
100 nF
100 nF
10
H@10 A
TAS5152DKD
0
Optional
TAS5508
10
10
47
F
50 V
10
H@10 A
10
H@10 A
33 nF
470 nF
63 V
10 nF
50 V
10 nF
50 V
3.3
3.3
100 nF
100 V
100 nF
100 V
No connect
No connect
No connect
Figure 18. Typical Non-Differential (1N) PBTL Application
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
20
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5152 needs only a
12-V supply in addition to the (typically) 35-V power-stage
supply. An internal voltage regulator provides suitable
voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating
voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring
only a few external capacitors.
In order to provide outstanding electrical and acoustical
characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent
half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins
(BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply
for all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see
application diagram for details). These RC filters provide
the recommended high-frequency isolation. Special
attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In
general, inductance between the power supply pins and
decoupling capacitors must be avoided. (See reference
board documentation for additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each bootstrap
pin (BST_X) to the power-stage output pin (OUT_X).
When the power-stage output is low, the bootstrap
capacitor is charged through an internal diode connected
between the gate-drive power-supply pin (GVDD_X) and
the bootstrap pin. When the power-stage output is high,
the bootstrap capacitor potential is shifted above the
output potential and thus provides a suitable voltage
supply for the high-side gate driver. In an application with
PWM switching frequencies in the range 352 kHz to 384
kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF
capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power
stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle. In an application running at a
reduced switching frequency, generally 192 kHz, the
bootstrap capacitor might need to be increased in value.
Special attention should be paid to the power-stage power
supply; this includes component selection, PCB
placement and routing. As indicated, each half-bridge has
independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and
system reliability it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5152 reference design.
For additional information on recommended power supply
and required components, see the application diagrams
given previously in this data sheet.
The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
35-V power-stage supply is assumed to have low output
impedance and low noise. The power-supply sequence is
not critical as facilitated by the internal power-on-reset
circuit. Moreover, the TAS5152 is fully protected against
erroneous power-stage turnon due to parasitic gate
charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the
Recommended Operating Conditions section of this data
sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The TAS5152 does not require a power-up sequence. The
outputs of the H-bridges remain in a high-impedance state
until the gate-drive supply voltage (GVDD_X) and VDD
voltage are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics
section of this data sheet). Although not specifically
required, it is recommended to hold RESET_AB and
RESET_CD in a low state while powering up the device.
This allows an internal circuit to charge the external
bootstrap capacitors by enabling a weak pulldown of the
half-bridge output.
When the TAS5152 is being used with TI PWM modulators
such as the TAS5508, no special attention to the state of
RESET_AB and RESET_CD is required, provided that the
chipset is configured as recommended.
Powering Down
The TAS5152 does not require a power-down sequence.
The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are
above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics section of this
data sheet). Although not specifically required, it is a good
practice to hold RESET_AB and RESET_CD low during
power down, thus preventing audible artifacts including
pops or clicks.
When the TAS5152 is being used with TI PWM modulators
such as the TAS5508, no special attention to the state of
RESET_AB and RESET_CD is required, provided that the
chipset is configured as recommended.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
21
ERROR REPORTING
The SD and OTW pins are both active-low, open-drain
outputs. Their function is for protection-mode signaling to
a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the
SD pin going low. Likewise, OTW goes low when the
device junction temperature exceeds 125
C (see the
following table).
SD
OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0
1
Overload (OLP) or undervoltage (UVP)
1
0
Junction temperature higher than 125
C
(overtemperature warning)
1
1
Junction temperature lower than 125
C and no
OLP or UVP faults (normal operation)
Note that asserting either RESET_AB or RESET_CD low
forces the SD signal high, independent of faults being
present. TI recommends to monitoring the OTW signal
using the system microcontroller and responding to an
overtemperature warning signal by, e.g., turning down the
volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup
resistor to 3.3V is provided on both SD and OTW outputs.
Level compliance for 5-V logic can be obtained by adding
external pullup resistors to 5 V (see the Electrical
Characteristics section of this data sheet for further
specifications).
DEVICE PROTECTION SYSTEM
TAS5152 contains advanced protection circuitry carefully
designed to facilitate system integration and ease of use,
as well as to safeguard the device from permanent failure
due to a wide range of fault conditions such as short
circuits, overload, overtemperature, and undervoltage.
The TAS5152 responds to a fault by immediately setting
the power stage in a high-impedance state (Hi-Z) and
asserting the SD pin low. In situations other than overload,
the device automatically recovers when the fault condition
has been removed, i.e., the junction temperature has
dropped or the voltage supply has increased. For highest
possible reliability, recovering from an overload fault
requires external reset of the device (see the Device Reset
section of this data sheet) no sooner than 1 second after
the shutdown.
Use of TAS5152 in High-Modulation-Index
Capable Systems
This device requires at least 50 ns of low time on the output
per 384-kHz PWM frame rate in order to keep the
bootstrap capacitors charged. As an example, if the
modulation index is set to 99.2% in the TAS5508, this
setting allows PWM pulse durations down to 20 ns. This
signal, which does not meet the 50-ns requirement, is sent
to the PWM_x pin and this low-state pulse time does not
allow the bootstrap capacitor to stay charged. In this
situation, the low voltage across the bootstrap capacitor
can cause a failure of the high-side MOSFET transistor,
especially when driving a low-impedance load. The
TAS5152 device requires limiting the TAS5508 modulation
index to 96.1% to keep the bootstrap capacitor charged
under all signals and loads.
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5508 or TAS5086, with the
modulation index set at 96.1% to interface with TAS5152.
Overcurrent (OC) Protection With Current
Limiting and Overload Detection
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC threshold)
on all high-side and low-side power-stage FETs. See the
following table for OC-adjust resistor values. The detector
outputs are closely monitored by two protection systems.
The first protection system controls the power stage in
order to prevent the output current from further increasing,
i.e., it performs a current-limiting function rather than
prematurely shutting down during combinations of
high-level music transients and extreme speaker load
impedance drops. If the high-current situation persists,
i.e., the power stage is being overloaded, a second
protection system triggers a latching shutdown, resulting
in the power stage being set in the high-impedance (Hi-Z)
state. Current limiting and overload protection are
independent for the half-bridges A and B and, respectively,
C and D. That is, if the bridge-tied load between
half-bridges A and B causes an overload fault, only
half-bridges A and B are shut down.
D
For the lowest-cost bill of materials in terms
of component selection, the OC threshold
measure should be limited, considering the
power output requirement and minimum
load impedance. Higher-impedance loads
require a lower OC threshold.
D
The demodulation-filter inductor must retain
at least 3
H of inductance at twice the OC
threshold setting.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
22
Unfortunately, most inductors have decreasing inductance
with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature
naturally occurs when operating at high output currents,
due to core losses and the DC resistance of the inductor's
copper winding. A thorough analysis of inductor saturation
and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues such
as lack of enough output power and/or unexpected
shutdowns due to too-sensitive overload detection.
In general, it is recommended to follow closely the external
component selection and PCB layout as given in the
Application section.
For added flexibility, the OC threshold is programmable
within a limited range using a single external resistor
connected between the OC_ADJ pin and AGND. (See the
Electrical Characteristics section of this data sheet for
information on the correlation between programming-
resistor value and the OC threshold.) It should be noted
that a properly functioning overcurrent detector assumes
the presence of a properly designed demodulation filter at
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage but
only on the speaker terminals (after the demodulation
filter). It is required to follow certain guidelines when
selecting the OC threshold and an appropriate
demodulation inductor:
OC-Adjust Resistor Values
(k
W
)
Max. Current Before OC
Occurs (A)
15
10.8
22
9.4
27
8.6
39
6.4
47
6
69
4.7
Overtemperature Protection
The TAS5152 has a two-level temperature-protection
system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125
C
(nominal) and, if the device junction temperature exceeds
155
C (nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance state (Hi-Z) and SD being asserted low.
OTE is latched in this case. To clear the OTE latch, both
RESET_AB and RESET_CD must be asserted.
Thereafter, the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5152 fully protect the
device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload
circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages
reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance state (Hi-Z) and SD being asserted low.
The device automatically resumes operation when all
supply voltages have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control of
half-bridges A/B and C/D. When RESET_AB is asserted
low, all four power-stage FETs in half-bridges A and B are
forced into a high-impedance state (Hi-Z). Likewise,
asserting RESET_CD low forces all four power-stage
FETs in half-bridges C and D into a high-impedance state.
Thus, both reset pins are well suited for hard-muting the
power stage if needed.
In BTL modes, to accommodate bootstrap charging prior
to switching start, asserting the reset inputs low enables
weak pulldown of the half-bridge outputs. In the SE mode,
the weak pulldowns are not enabled, and it is therefore
recommended to ensure bootstrap capacitor charging by
providing a low pulse on the PWM inputs when reset is
asserted high.
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD is
forced high.
A rising-edge transition on either reset input allows the
device to resume operation after an overload fault.
TAS5152
SLES127 - FEBRUARY 2005
www.ti.com
23
MECHANICAL DATA
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
TAS5152DKD
ACTIVE
SSOP
DKD
36
29
Pb-Free
(RoHS)
CU SNBI
Level-4-260C-72
HR/
Level-2-220C-1 YEAR
TAS5152DKDR
ACTIVE
SSOP
DKD
36
500
Pb-Free
(RoHS)
CU SNBI
Level-4-260C-72
HR/
Level-2-220C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
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