TM
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FEATURES
APPLICATIONS
DESCRIPTION
PVDD = 40 V
T
C
= 75
C
10
70
G012
0.01
0.1
20
1
1
10
P
O
Output Power W
THD+N T
otal Harmonic Distortion + Noise %
6
Satellite
3
Subwoofer
TAS5186
SLES136 MAY 2005
6-Channel, 210-W, Digital-Amplifier Power Stage
The TAS5186 requires only simple passive demodu-
lation filters on its outputs to deliver high-quality,
Total Output Power @ 10% THD+N
high-efficiency audio amplification. The efficiency of
530 W @ 6
+ 160 W @ 3
the TAS5186 is greater than 90% when driving 6-
satellites and a 3-
subwoofer speaker.
105-dB SNR (A-Weighted)
< 0.05% THD+N @ 1 W
The TAS5186 has an innovative protection system
integrated on-chip, safeguarding the device against a
Power Stage Efficiency > 90% Into
wide range of fault conditions that could damage the
Recommended Loads (SE)
system. These safeguards are short-circuit protection,
Integrated Self-Protection Circuits
overload protection, undervoltage protection, and
Undervoltage
overtemperature protection. The TAS5186 has a new
proprietary current-limiting circuit that reduces the
Overtemperature
possibility of device shutdown during high-level music
Overload
transients. A new programmable overcurrent detector
Short Circuit
allows the use of lower-cost inductors in the demodu-
lation output filter.
Integrated Active-Bias Control to Avoid DC
Pop
TOTAL HARMONIC DISTORTION + NOISE
vs
Thermally Enhanced 44-pin HTSSOP Package
OUTPUT POWER
EMI-Compliant When Used With
Recommended System Design
DVD Receiver
Home Theater in a Box
The TAS5186 is a high-performance, six-channel,
digital-amplifier power stage with an improved protec-
tion system. The TAS5186 is capable of driving a
6-
, single-ended
load up to 30 W per each
front/satellite
channel
and
a
3-
,
single-ended
subwoofer greater than 60 W at 10% THD+N per-
formance.
A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186. This device does not
require power-up sequencing because of the internal
power-on reset.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, PurePath Digital are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
GENERAL INFORMATION
TERMINAL ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PGND_EF
PWM_F
GVDD_DEF
VDD
PWM_E
PWM_D
RESET
M3
M2
M1
GND
AGND
VREG
OC_ADJ
SD
OTW
PWM_C
PWM_B
PWM_A
GVDD_ABC
BST_BIAS
OUT_BIAS
DDV PACKAGE
(TOP VIEW)
BST_F
PVDD_F
OUT_F
PGND_EF
OUT_E
PVDD_E
BST_E
BST_D
PVDD_D
OUT_D
PGND_D
PGND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
PGND_AB
OUT_A
PVDD_A
BST_A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P0016-01
TAS5186
SLES136 MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPADTM package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heatsink.
2
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TAS5186
SLES136 MAY 2005
GENERAL INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
TYPE
(1)
DESCRIPTION
NAME
NO.
AGND
12
P
Analog ground
BST_A
23
P
HS bootstrap supply (BST), capacitor to OUT_A required
BST_B
29
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_BIAS
21
P
BIAS bootstrap supply, external capacitor to OUT_BIAS required
BST_C
30
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
37
P
HS bootstrap supply (BST), external capacitor to OUT_D required
BST_E
38
P
HS bootstrap supply (BST), external capacitor to OUT_E required
BST_F
44
P
HS bootstrap supply (BST), external capacitor to OUT_F required
GND
11
P
Chip ground
GVDD_ABC
20
P
Gate drive voltage supply
GVDD_DEF
3
P
Gate drive voltage supply
M1
10
I
Mode selection pin
M2
9
I
Mode selection pin
M3
8
I
Mode selection pin
OC_ADJ
14
O
Overcurrent threshold programming pin, resistor to ground required
OTW
16
O
Overtemperature warning open-drain output signal, active-low
OUT_A
25
O
Output, half-bridge A, satellite
OUT_B
27
O
Output, half-bridge B, satellite
OUT_BIAS
22
O
BIAS half-bridge output pin
OUT_C
32
O
Output, half-bridge C, subwoofer
OUT_D
35
O
Output, half-bridge D, satellite
OUT_E
40
O
Output, half-bridge E, satellite
OUT_F
42
O
Output, half-bridge F, satellite
PGND_AB
26
P
Power ground
PGND_C
33
P
Power ground
PGND_D
34
P
Power ground
PGND_EF
1, 41
P
Power ground
PVDD_A
24
P
Power-supply input for half-bridge A
PVDD_B
28
P
Power-supply input for half-bridge B
PVDD_C
31
P
Power-supply input for half-bridge C
PVDD_D
36
P
Power-supply input for half-bridge D
PVDD_E
39
P
Power-supply input for half-bridge E
PVDD_F
43
P
Power-supply input for half-bridge F
PWM_A
19
I
PWM input signal for half-bridge A
PWM_B
18
I
PWM input signal for half-bridge B
PWM_C
17
I
PWM input signal for half-bridge C
PWM_D
6
I
PWM input signal for half-bridge D
PWM_E
5
I
PWM input signal for half-bridge E
PWM_F
2
I
PWM input signal for half-bridge F
RESET
7
I
Reset signal (active-low logic)
SD
15
O
Shutdown open-drain output signal, active-low
VDD
4
P
Power supply for digital voltage regulator
VREG
13
O
Digital regulator supply filter pin, output
(1)
I = input; O = output; P = power
3
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PACKAGE HEAT DISSIPATION RATINGS
(1)
ABSOLUTE MAXIMUM RATINGS
TAS5186
SLES136 MAY 2005
Table 1. MODE Selection Pins
MODE PINS
(1)
MODE
M2
M3
NAME
DESCRIPTION
0
0
2.1 mode
Channels A, B, and C enabled; channels D, E, and F disabled
0
1
5.1 mode
All channels enabled
1
0/1
Reserved
(1)
M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
PARAMETER
TAS5186DDV
R
JC
(
C/W)--1 satellite (sat.) FET only
10.3
R
JC
(
C/W)--1 subwoofer (sub.) FET only
5.2
R
JC
(
C/W)--1 sat. half-bridge
5.2
R
JC
(
C/W)--1 sub. half-bridge
2.6
R
JC
(
C/W)--5 sat. half-bridges + 1 sub.
1.74
Typical pad area
(2)
34.9 mm
2
(1)
JC is junction-to-case, CH is case-to-heatsink.
(2)
R
CH
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
R
CH
with this condition is typically 2C/W for this package.
over operating free-air temperature range (unless otherwise noted)
(1)
TAS5186
VDD to AGND
0.3 V to 13.2 V
GVDD_X to AGND
0.3 V to 13.2 V
PVDD_X to PGND_X
(2)
0.3 V to 50 V
OUT_X to PGND_X
(2)
0.3 V to 50 V
BST_X to PGND_X
(2)
0.3 V to 63.2 V
VREG to AGND
0.3 V to 4.2 V
PGND_X to GND
0.3 V to 0.3 V
PGND_X to AGND
0.3 V to 0.3 V
GND to AGND
0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND
0.3 V to 4.2 V
RESET, SD, OTW to AGND
0.3 V to 7 V
Maximum operating junction temperature range (T
J
)
0 to 125C
Storage temperature
40C to 125C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260C
Minimum PWM pulse duration, low
30 ns
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
4
www.ti.com
+
M3
M1
M2
OUT_F
PVDD_F
BST_F
GVDD_DEF
PWM_E
PWM_F
PWM_A
PWM_B
OTW
SD
PWM_C
VDD
AGND
OC_ADJ
VREG
PWM_D
RESET
OUT_E
PVDD_E
PGND_EF
BST_E
GVDD_ABC
GND
OUT_D
PVDD_D
PGND_D
BST_D
OUT_C
PVDD_C
BST_C
OUT_B
PVDD_B
PGND_AB
BST_B
OUT_A
PVDD_A
BST_A
VALID2
VALID1
To
P
PVDD
12 V
OUT_BIAS
BST_BIAS
21
22
43
44
42
41
39
38
40
36
37
35
34
31
30
32
SAT
28
29
27
26
25
23
24
3
20
4
13
14
12
10
9
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
2
5
6
15
16
11
PGND_C
33
17
18
19
7
8
PGND_EF
1
PurePath
Digital
TM
Modulator
TAS5086
TAS5186
S0061-01
SAT
SAT
SUB
SAT
SAT
680
33 nF
+
+
+
+
+
+
22
H
270
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
33 nF
33 nF
33 nF
33 nF
33 nF
270
F
270
F
270
F
270
F
270
F
1000
F
1000
F
270
F
270
F
270
F
270
F
22
H
22
H
22
H
22
H
22
H
330
330
330
330
330
330
0.47
F
0.47
F
0.47
F
0.47
F
0.47
F
0.47
F
1
F
1
F
1
F
1
F
1
F
1
F
33 nF
1
F
15 k
1
F
0.1
F
0.1
F
10
F
TAS5186
SLES136 MAY 2005
TYPICAL SYSTEM DIAGRAM
PurePath DigitalTM
5
www.ti.com
M1
M2
RESET
SD
OTW
AGND
OC_ADJ
VREG
VREG
VDD
GVDD_DEF
M3
Undervoltage
Protection
GND
PWM_F
OUT_F
PGND_EF
PVDD_F
BST_F
PWM
Receiver
I
Sense
Protection
and
I/O Logic
Power On
Reset
Temperature
Sense
Overload
Protection
Control
Timing
Gate
Drive
PWM_E
OUT_E
PGND_EF
PVDD_E
BST_E
PWM
Receiver
Control
Timing
Gate
Drive
PWM_D
OUT_D
PGND_D
PVDD_D
BST_D
PWM
Receiver
Control
Timing
Gate
Drive
PWM_C
OUT_C
PGND_C
PVDD_C
BST_C
PWM
Receiver
Control
Timing
Gate
Drive
PWM_B
OUT_B
PGND_AB
PVDD_B
BST_B
PWM
Receiver
Control
Timing
Gate
Drive
PWM_A
OUT_A
PVDD_A
BST_A
PWM
Receiver
Control
Timing
Gate
Drive
OUT_BIAS
BST_BIAS
Control
Timing
Gate
Drive
B0034-01
Internal Pullup
Resistors to VREG
GVDD_ABC
TAS5186
SLES136 MAY 2005
FUNCTIONAL BLOCK DIAGRAM
6
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RECOMMENDED OPERATING CONDITIONS
AUDIO SPECIFICATION
TAS5186
SLES136 MAY 2005
MIN
TYP
MAX
UNIT
PVDD_X
Half-bridge supply, SE
DC supply voltage at pin(s)
0
40
V
GVDD
Gate drive and guard ring supply voltage
DC voltage at pin(s)
10.8
12
13.2
V
VDD
Digital regulator supply
DC supply voltage at pin
10.8
12
13.2
V
Any value of R
PU,EXT
within
VPU
Pullup voltage supply
3
5
5.5
V
recommended range
Resistive load impedance, satellite
Recommended demodulation filter
R
L,SAT
4
6
channels
(1)
Resistive load impedance, subwoofer
Recommended demodulation filter
R
L,SUB
2.25
3
channel
Minimum output inductance under
L
output
Demodulation filter inductance
5
22
H
short-circuit condition
C
output,sat
Demodulation filter capacitance
1
F
C
output,sub
Demodulation filter capacitance
0.47
F
F
PWM
PWM frame rate
192
384
432
kHz
(1)
Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP.
PVDD_X = 40 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, F
PWM
= 384 kHz, case temperature =
75C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless
otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
R
L
= 6
, 10% THD, clipped input signal
30
R
L
= 8
, 10% THD, clipped input signal
25
P
O,sat
Power output per satellite channel
W
R
L
= 6
, 0 dBFS, unclipped input signal
25
R
L
= 8
, 0 dBFS, unclipped input signal
20
R
L
= 3
, 10% THD, clipped input signal
60
R
L
= 4
, 10% THD, clipped input signal
52
P
O,sub
Power output, subwoofer
W
R
L
= 3
, 0 dBFS, unclipped input signal
50
R
L
= 4
, 0 dBFS, unclipped input signal
40
R
L
= 6
, P
O
= 25 W
0.3%
Total harmonic distortion + noise,
satellite
R
L
= 6
, 1 W
0.03%
THD + N
R
L
= 3
, P
O
= 50 W
0.5%
Total harmonic distortion + noise,
subwoofer
R
L
= 3
, 1 W
0.03%
Output integrated noise, satellite
A-weighted
55
V
n
V
Output integrated noise, subwoofer
A-weighted
60
SNR
System signal-to-noise ratio
A-weighted
105
dB
DNR
Dynamic range
(1)
A-weighted, 60 dBFs input signal
105
dB
P
O
= 0 W, all channels running 5.1 mode
(2)
8
W
Power dissipation due to idle losses
P
idle
(IPVDDX)
P
O
= 0 W, 2.1 mode
4
W
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
7
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ELECTRICAL CHARACTERISTICS
TAS5186
SLES136 MAY 2005
F
PWM
= 384 kHz, GVDD = 12 V, VDD = 12 V, T
C
(case temperature) = 25
C, unless otherwise noted. All performance is in
accordance with recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference node
VDD = 12 V
3
3.3
3.6
V
Operating, 50% duty cycle
7
20
IVDD
VDD supply current
mA
Idle, reset mode
6
16
50% duty cycle
5
22
IGVDD_X
Gate supply current per half-bridge
mA
Idle, reset mode
1
3
50% duty cycle, without output filter or load, 5.1
180
mode
IPVDD_X
Half-bridge idle current
mA
50% duty cycle, without output filter or load, 2.1
100
mode
OUTPUT STAGE MOSFETs
R
DSon
, LS Sat
Drain-to-source resistance, low side, satellite
T
J
= 25C, includes metallization resistance
210
m
R
DSon
, HS Sat
Drain-to-source resistance, high side, satellite
T
J
= 25C, includes metallization resistance
210
m
R
Dson
, LS Sub
Drain-to-source resistance, low side, subwoofer
T
J
= 25C, includes metallization resistance
110
m
R
Dson
, HS Sub
Drain-to-source resistance, high side, subwoofer
T
J
= 25C, includes metallization resistance
110
m
I/O PROTECTION
V
UVP, G
Undervoltage protection limit GVDD_X
10
V
V
UVP, hyst
(1)
Undervoltage protection hysteresis
250
mV
OTW
(1)
Overtemperature warning
125
C
Temperature drop needed below OTW temp. for
OTW
hyst
(1)
25
C
OTW to be inactive after the OTW event
OTE
(1)
Overtemperature error
155
C
Temperature drop needed below OTE temp. for SD
OTE
HYST
(1)
25
C
to be released after the OTE event
OLCP
Overload protection counter
1.25
ms
Resistor programmable, high end,
Overcurrent limit protection, sat.
5
A
Rocp = 15 k
I
OC
Resistor programmable, high end,
Overcurrent limit protection, sub.
8
A
Rocp = 15 k
I
OCT
Overcurrent response time
210
ns
Rocp
OC programming resistor range
Resistor tolerance = 5%
15
k
STATIC DIGITAL SPECIFICATION
V
IH
High-level input voltage
2
PWM_X, M1, M2, M3, RESET
V
V
IL
Low-level input voltage
0.8
I
LEAK
Input leakage current
Static condition
80
80
A
OTW/SHUTDOWN (SD)
Internal pullup resistor to DREG (3.3 V) for SD and
R
INT_PU
26
k
OTW
Internal pullup resistor only
3
3.3
3.6
V
OH
High-level output voltage
External pullup: 4.7-k
resistor to 5 V
4.5
5
V
V
OL
Low-level output voltage
I
O
= 4 mA
0.2
0.4
FANOUT
Device fanout OTW, SD
No external pullup
30
Devices
(1)
Specified by design.
8
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TYPICAL CHARACTERISTICS, 5.1 MODE
Satellite
PVDD = 40 V
T
C
= 75
C
THD+N T
otal Harmonic Distortion + Noise %
10
40
G001
0.01
0.1
20
1
1
10
6
8
P
O
Output Power W
Subwoofer
PVDD = 40 V
T
C
= 75
C
10
70
G002
0.01
0.1
20
1
1
10
3
4
P
O
Output Power W
THD+N T
otal Harmonic Distortion + Noise %
PVDD Supply Voltage V
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
0
5
10
15
20
25
30
35
40
P
O
Output Power W
G003
Satellite
1 Channel
T
C
= 75
C
THD+N = 10%
6
8
PVDD Supply Voltage V
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
0
5
10
15
20
25
30
35
40
G004
Subwoofer
1 Channel
T
C
= 75
C
THD+N = 10%
3
4
P
O
Output Power W
TAS5186
SLES136 MAY 2005
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
Figure 1.
Figure 2.
OUTPUT POWER
OUTPUT POWER
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 3.
Figure 4.
9
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PVDD Supply Voltage V
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
0
5
10
15
20
25
30
35
40
G005
Satellite
1 Channel
T
C
= 75
C
Unclipped Input Signal
6
8
P
O
Output Power W
PVDD Supply Voltage V
0
5
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
25
30
35
40
G006
Subwoofer
1 Channel
T
C
= 75
C
Unclipped Input Signal
3
4
P
O
Output Power W
0
10
20
30
40
50
60
70
80
90
100
0
20 40 60 80 100 120 140 160 180 200 220 240
System Efficiency %
G007
5.1 Mode
PVDD = 40 V
T
C
= 25
C
R
L(SAT)
= 8
R
L(SUB)
= 4
P
O
Total Output Power W
R
L(SAT)
= 6
R
L(SUB)
= 3
0
5
10
15
20
25
30
35
40
0
20 40 60 80 100 120 140 160 180 200 220 240
System Power Loss W
G008
5.1 Mode
PVDD = 40 V
T
C
= 25
C
P
O
Total Output Power W
R
L(SAT)
= 8
R
L(SUB)
= 4
R
L(SAT)
= 6
R
L(SUB)
= 3
TAS5186
SLES136 MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
OUTPUT POWER
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 5.
Figure 6.
SYSTEM EFFICIENCY
SYSTEM POWER LOSS
vs
vs
TOTAL OUTPUT POWER
TOTAL OUTPUT POWER
Figure 7.
Figure 8.
10
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T
C
Case Temperature
C
0
5
10
15
20
25
30
35
40
20
30
40
50
60
70
80
90
100
110
G009
Satellite
1 Channel
THD+N = 10%
6
8
P
O
Output Power W
T
C
Case Temperature
C
0
10
20
30
40
50
60
70
80
20
30
40
50
60
70
80
90
100
110
G010
3
4
Subwoofer
1 Channel
THD+N = 10%
P
O
Output Power W
f Frequency kHz
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
2
4
6
8
10
12
14
16
18
20
22
Amplitude dB
G011
Satellite
1 Channel
PVDD = 40 V
T
C
= 75
C
TAS5186
SLES136 MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
OUTPUT POWER
vs
vs
CASE TEMPERATURE
CASE TEMPERATURE
Figure 9.
Figure 10.
AMPLITUDE
vs
FREQUENCY
Figure 11.
11
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
SYSTEM POWER-UP/DOWN SEQUENCE
Powering Down
Error Reporting
TAS5186
SLES136 MAY 2005
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin on the same
side of the PCB as the TAS5186. It is recommended
To facilitate system design, the TAS5186 needs only
to follow the PCB layout of the TAS5186 reference
a
12-V
supply
in
addition
to
a
typical
39-V
design.
For
additional
information
on
the
rec-
power-stage supply. An internal voltage regulator
ommended power supply and required components,
provides suitable voltage levels for the digital and
see the application diagrams given in this data sheet.
low-voltage analog circuitry. Additionally, all circuitry
The
12-V
supply
should
be
powered
from
a
requiring a floating voltage supply, e.g., the high-side
low-noise, low-output-impedance voltage regulator.
gate drive, is accommodated by built-in bootstrap
Likewise, the 39-V power-stage supply is assumed to
circuitry requiring only a few external capacitors.
have low output impedance and low noise. The
power-supply sequence is not critical due to the
In order to provide outstanding electrical and acoustic
internal
power-on-reset
circuit.
Moreover,
the
characteristics, the PWM signal path including gate
TAS5186
is
fully
protected
against
erroneous
drive and output stage is designed as identical,
power-stage turnon due to parasitic gate charging.
independent half-bridges. For this reason, each
Thus, voltage-supply ramp rates (dv/dt) are typically
half-bridge has separate bootstrap pins (BST_X) and
noncritical.
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as power supply for
all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
The TAS5186 does not require a power-up sequence.
GVDD_X and VDD on the printed-circuit board (PCB)
The
outputs
of
the
H-bridge
remain
in
a
by RC filters (see application diagram for details).
high-impedance state until the gate-drive supply volt-
These
RC
filters
provide
the
recommended
age (GVDD_X) and VDD voltage are above the
high-frequency isolation. Special attention should be
undervoltage protection (UVP) voltage threshold (see
paid to placing all decoupling capacitors as close to
the Electrical Characteristics section of this data
their associated pins as possible. In general, induct-
sheet). Although not specifically required, it is rec-
ance between the power-supply pins and decoupling
ommended to hold RESET in a low state while
capacitors must be avoided. (See reference board
powering up the device.
documentation for additional information.)
When the TAS5186 is being used with TI PWM
For a properly functioning bootstrap circuit, a small
modulators such as the TAS5086, no special atten-
ceramic capacitor must be connected from each
tion to the state of RESET is required, provided that
bootstrap pin (BST_X) to the power-stage output pin
the chipset is configured as recommended.
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode
connected
between
the
gate-drive
power-supply pin (GVDD_X) and the bootstrap pin.
The TAS5186 does not require a power-down se-
When the power-stage output voltage is high, the
quence. The device remains fully operational as long
bootstrap capacitor voltage is shifted above the
as the gate-drive supply (GVDD_X) voltage and VDD
output voltage potential and thus provides a suitable
voltage are above the undervoltage protection (UVP)
voltage supply for the high-side gate driver. In an
threshold level (see the Electrical Characteristics
application with PWM switching frequencies in the
section of this data sheet). Although not specifically
range 352 kHz to 384 kHz, it is recommended to use
required, it is a good practice to hold RESET low
33-nF ceramic capacitors, size 0603 or 0805, for the
during power down, thus preventing audible artifacts
bootstrap capacitor. These 33-nF capacitors ensure
including pops and clicks
sufficient energy storage, even during minimal PWM
When the TAS5186 is being used with TI PWM
duty cycles, to keep the high-side power stage FET
modulators such as the TAS5086, no special atten-
(LDMOS) fully started during all of the remaining part
tion to the state of RESET is required, provided that
of the PWM cycle. In an application running at a
the chipset is configured as recommended.
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
The
SD
and
OTW
pins
are
both
active-low,
component selection, PCB placement and routing. As
open-drain outputs. Their function is for protec-
indicated,
each
half-bridge
has
independent
tion-mode signaling to a PWM controller or other
power-stage supply pins (PVDD_X). For optimal elec-
system-control device.
trical performance, EMI compliance, and system re-
liability it is important that each PVDD_X pin is
12
www.ti.com
Device Protection System
OVERCURRENT (OC) PROTECTION WITH
TAS5186
SLES136 MAY 2005
Any fault resulting in device shutdown is signaled by
two protection systems. The first protection system
the SD pin going low. Likewise, OTW goes low when
controls the power stage in order to prevent the
the device junction temperature exceeds 125C (see
output current from further increasing. I.e., it performs
the following table).
a current-limiting function rather than prematurely
shutting down during combinations of high-level mu-
sic transients and extreme speaker load-impedance
SD
OTW
DESCRIPTION
drops. If the high-current situation persists, i.e., the
power stage is being overloaded, a second protection
0
0
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
system triggers a latching shutdown, resulting in the
power stage being set in the high-impedance (Hi-Z)
0
1
Overload (OLP) or undervoltage (UVP)
state.
1
0
Overtemperature warning. Junction temperature
higher than 125C, typical
For
added
flexibility,
the
OC
threshold
is
1
1
Normal operation. Junction temperature lower than
programmable within a limited range using a single
125C, typical
external resistor connected between the OC_ADJ pin
and AGND.
It should be noted that asserting RESET low forces
OC-Adjust Resistor Values
Maximum Current Before OC
the SD and OTW signals high independently of faults
(k
)
Occurs (A)
being present. It is recommended to monitor the
15
5 (sat.), 8 (sub.)
OTW signal using the system microcontroller and to
respond to an overtemperature warning signal by,
18
4.5 (sat.), 7.5 (sub.)
e.g., turning down the volume to prevent further
It should be noted that a properly functioning
heating of the device that would result in device
overcurrent detector assumes the presence of a
shutdown (OTE). To reduce external component
properly
designed
demodulation
filter
at
the
count, an internal pullup resistor to 3.3 V is provided
power-stage output. Short-circuit protection is not
on both the SD and OTW outputs. Level compliance
provided directly at the output pins of the power stage
for 5-V logic can be obtained by adding external
but only on the speaker terminals (after the demodu-
pullup resistors to 5 V (see the Electrical Character-
lation filter). It is required to follow certain guidelines
istics section of this data sheet for further specifi-
when selecting the OC threshold and an appropriate
cations).
demodulation inductor.
For the lowest-cost bill of materials in terms of
component selection, the OC threshold current
The TAS5186 contains advanced protection circuitry
should be limited, considering the power output
carefully designed to facilitate system integration and
requirement
and
minimum
load
impedance.
ease of use, as well as safeguarding the device from
Higher-impedance loads require a lower OC
permanent failure due to a wide range of fault
threshold.
conditions such as short circuit, overload, and
The demodulation filter inductor must retain at
undervoltage. The TAS5186 responds to a fault by
least 5
H of inductance at twice the OC
immediately
setting
the
power
stage
in
a
threshold setting.
high-impedance state (Hi-Z) and asserting the SD pin
low. In situations other than overload, the device
Most inductors have decreasing inductance with in-
automatically recovers when the fault condition has
creasing
temperature
and
increasing
current
been
removed,
e.g.,
the
supply
voltage
has
(saturation). To some degree, an increase in tem-
increasedor
the
temperature
has
dropped.
For
perature naturally occurs when operating at high
highest possible reliability, recovering from an over-
output currents, due to inductor core losses and the
load fault requires external reset of the device no
dc resistance of the inductor copper winding. A
sooner than 1 second after the shutdown (see the
thorough analysis of inductor saturation and thermal
Device Reset section of this data sheet).
properties is strongly recommended.
Setting the OC threshold too low might cause issues
such as lack of output power and/or unexpected
CURRENT LIMITING AND OVERLOAD DE-
shutdowns due to sensitive overload detection.
TECTION
In general, it is recommended to follow closely the
The device has independent, fast-reacting current
external component selection and PCB layout as
detectors with programmable trip threshold (OC
given in the application section.
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
13
www.ti.com
Overtemperature Protection
UNDERVOLTAGE PROTECTION (UVP) AND
DEVICE RESET
ACTIVE-BIAS CONTROL (ABC)
TAS5186
SLES136 MAY 2005
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capaci-
The TAS5186 has a two-level temperature-protection
tor, to the desired potential before switching is started
system that asserts an active-low warning signal
on the PWM outputs. (For recommended configur-
(OTW) when the device junction temperature ex-
ation, see the typical application schematic included
ceeds 125C (typical), and If the device junction
in this data sheet).
temperature exceeds 155C (typical), the device is
put into thermal shutdown, resulting in all half-bridge
The start-up sequence can be controlled through
outputs being set in the high-impedance state (Hi-Z)
sequencing the M3 and RESET pins according to
and SD being asserted low.
Table 2
and
Table 3
.
Table 2. 5.1 Mode--All Output Channels Active
POWER-ON RESET (POR)
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
COMMENT
_B, _C
_E, _F
The UVP and POR circuits of the TAS5186 fully
0
0
Hi-Z
Hi-Z
Hi-Z
All outputs dis-
protect
the
device
in
any
power-up/down
and
abled, nothing is
brownout situation. While powering up, the POR
switching.
circuit resets the overload circuit (OLP) and ensures
1
0
Active
Hi-Z
Hi-Z
OUT_BIAS en-
that all circuits are fully operational when the
abled, all other
GVDD_X and VDD supply voltages reach 10 V
outputs disabled
(typical). Although GVDD_X and VDD are indepen-
1
1
Hi-Z
Active
Active
OUT_BIAS dis-
dently monitored, a supply voltage drop below the
abled, all other
UVP threshold on any VDD or GVDD_X pin results in
outputs
switching
all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
Table 3. 2.1 Mode--Only Output Channels A, B,
when all supply voltages have increased above the
and C Active
UVP threshold.
M3
RESET
OUT_BIAS
OUT_A, OUT_D,
COMMENT
_B, _C
_E, _F
0
0
Hi-Z
Hi-Z
Hi-Z
All outputs dis-
abled, nothing is
When RESET is asserted low, the output FETs in all
switching.
half-bridges are forced into a high-impedance (Hi-Z)
1
0
Active
Hi-Z
Hi-Z
OUT_BIAS en-
state.
abled, all other
outputs disabled
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
0
1
Hi-Z
Active
Hi-Z
OUT_BIAS dis-
abled, all other
is forced high.
outputs
A rising-edge transition on the RESET input allows
switching
the device to resume operation after an overload
When the TAS5186 is used with the TAS5086 PWM
fault.
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
recommended.
Audible
pop
noises
are
often
associated
with
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorpor-
ating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
14
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
TAS5186DDV
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVG4
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVR
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVRG4
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DKD
PREVIEW
SSOP
DKD
44
TBD
Call TI
Call TI
TAS5186DKDR
PREVIEW
SSOP
DKD
44
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2005
Addendum-Page 1
IMPORTANT NOTICE
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