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FEATURES

APPLICATIONS

DESCRIPTION

THD+N T

otal Harmonic Distortion + Noise %

G012

0.01

0.1

 Output Power W

PVDD = 40 V
T

= 75

Satellite

Subwoofer

TAS5186A

SLES156 OCTOBER 2005

6-Channel, 210-W, Digital-Amplifier Power Stage

The

TAS5186A

requires

only

simple

passive

demodulation

filters

its

outputs

deliver

Total Output Power @ 10% THD+N

high-quality, high-efficiency audio amplification. The

 5×30 W @ 6

+ 1×60 W @ 3

device efficiency of the TAS5186A is greater than
90% when driving 6-

satellites and a 3-

subwoofer

105-dB SNR (A-Weighted)

speaker.

0.07% THD+N @ 1 W

The TAS5186A has an innovative protection system

Power Stage Efficiency > 90% Into

integrated on-chip, safeguarding the device against a

Recommended Loads (SE)

wide range of fault conditions that could damage the

Integrated Self-Protection Circuits

system. These safeguards are short-circuit protection,

 Undervoltage

overload protection, undervoltage protection, and
overtemperature protection. The TAS5186A has a

 Overtemperature

new proprietary current-limiting circuit that reduces

 Overload

the possibility of device shutdown during high-level

 Short Circuit

music transients. A new programmable overcurrent
detector allows the use of lower-cost inductors in the

Integrated Active-Bias Control to Avoid DC

demodulation output filter.

Pop

Thermally Enhanced 44-Pin HTSSOP Package

TOTAL HARMONIC DISTORTION + NOISE

EMI-Compliant When Used With

OUTPUT POWER

Recommended System Design

DVD Receiver

Home Theater in a Box

The TAS5186A is a high-performance, six-channel,
digital-amplifier

power

stage

with

improved

protection system. The TAS5186A is capable of
driving a 6-

singleended

load up to 30 W per each

front/satellite

channel

and

single-ended

subwoofer greater than 60 W at 10% THD+N
performance.

A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186A. This device does not
require power-up sequencing because of the internal
power-on reset.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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TAS5186A

SLES156 OCTOBER 2005

GENERAL INFORMATION (continued)

TERMINAL FUNCTIONS

TERMINAL

TYPE

(1)

DESCRIPTION

NAME

NO.

AGND

Analog ground

BST_A

HS bootstrap supply (BST), capacitor to OUT_A required

BST_B

HS bootstrap supply (BST), external capacitor to OUT_B required

BST_BIAS

BIAS bootstrap supply, external capacitor to OUT_BIAS required

BST_C

HS bootstrap supply (BST), external capacitor to OUT_C required

BST_D

HS bootstrap supply (BST), external capacitor to OUT_D required

BST_E

HS bootstrap supply (BST), external capacitor to OUT_E required

BST_F

HS bootstrap supply (BST), external capacitor to OUT_F required

GND

Chip ground

GVDD_ABC

Gate drive voltage supply

GVDD_DEF

Gate drive voltage supply

Mode selection pin

OC_ADJ

Overcurrent threshold programming pin, resistor to ground required

OTW

Overtemperature warning open-drain output signal, active-low

OUT_A

Output, half-bridge A, satellite

OUT_B

Output, half-bridge B, satellite

OUT_BIAS

BIAS half-bridge output pin

OUT_C

Output, half-bridge C, subwoofer

OUT_D

Output, half-bridge D, satellite

OUT_E

Output, half-bridge E, satellite

OUT_F

Output, half-bridge F, satellite

26,

PGND

33,

Power ground

34,

PVDD_A

Power-supply input for half-bridge A

PVDD_B

Power-supply input for half-bridge B

PVDD_C

Power-supply input for half-bridge C

PVDD_D

Power-supply input for half-bridge D

PVDD_E

Power-supply input for half-bridge E

PVDD_F

Power-supply input for half-bridge F

PWM_A

PWM input signal for half-bridge A

PWM_B

PWM input signal for half-bridge B

PWM_C

PWM input signal for half-bridge C

PWM_D

PWM input signal for half-bridge D

PWM_E

PWM input signal for half-bridge E

PWM_F

PWM input signal for half-bridge F

RESET

Reset signal (active-low logic)

Shutdown open-drain output signal, active-low

VDD

Power supply for digital voltage regulator

VREG

Digital regulator supply filter pin, output

(1)

I = input; O = output; P = power

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PACKAGE HEAT DISSIPATION RATINGS

(1)

ABSOLUTE MAXIMUM RATINGS

TAS5186A

SLES156 OCTOBER 2005

Table 1. MODE Selection Pins

MODE PINS

(1)

MODE

NAME

DESCRIPTION

2.1 mode

Channels A, B, and C enabled; channels D, E, and F disabled

5.1 mode

All channels enabled

0/1

Reserved

(1)

M1 must always be connected to GND. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.

PARAMETER

TAS5186ADDV

(

C/W)--1 satellite (sat.) FET only

10.3

(

C/W)--1 subwoofer (sub.) FET only

5.2

(

C/W)--1 sat. half-bridge

5.2

(

C/W)--1 sub. half-bridge

2.6

(

C/W)--5 sat. half-bridges + 1 sub.

1.74

Typical pad area

(2)

34.9 mm

(1)

JC is junction-to-case, CH is case-to-heatsink.

(2)

is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The

with this condition is typically 2°C/W for this package.

over operating free-air temperature range (unless otherwise noted)

(1)

TAS5186A

VDD to AGND

0.3 V to 13.2 V

GVDD_X to AGND

0.3 V to 13.2 V

PVDD_X to PGND_X

(2)

0.3 V to 50 V

OUT_X to PGND_X

(2)

0.3 V to 50 V

BST_X to PGND_X

(2)

0.3 V to 63.2 V

VREG to AGND

0.3 V to 4.2 V

PGND to GND

0.3 V to 0.3 V

PGND to AGND

0.3 V to 0.3 V

GND to AGND

0.3 V to 0.3 V

PWM_X, OC_ADJ, M1, M2, M3 to AGND

0.3 V to 4.2 V

RESET, SD, OTW to AGND

0.3 V to 7 V

Maximum operating junction temperature range (T

)

0 to 125°C

Storage temperature

40°C to 125°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260°C

Minimum PWM pulse duration, low

30 ns

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

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RESET

OTW

AGND

OC_ADJ

VREG

VDD

GVDD_DEF

Undervoltage

Protection

GND

PWM_F

OUT_F

PGND

PVDD_F

BST_F

PWM

Receiver

Sense

Protection

and

I/O Logic

Power-On

Reset

Temperature

Sense

Overload

Protection

Control

Timing

Gate

Drive

PWM_E

OUT_E

PGND

PVDD_E

BST_E

PWM

Receiver

Control

Timing

Gate

Drive

PWM_D

OUT_D

PGND

PVDD_D

BST_D

PWM

Receiver

Control

Timing

Gate

Drive

PWM_C

OUT_C

PGND

PVDD_C

BST_C

PWM

Receiver

Control

Timing

Gate

Drive

PWM_B

OUT_B

PGND

PVDD_B

BST_B

PWM

Receiver

Control

Timing

Gate

Drive

PWM_A

OUT_A

PVDD_A

BST_A

PWM

Receiver

Control

Timing

Gate

Drive

OUT_BIAS

BST_BIAS

Control

Timing

Gate

Drive

B0034-03

Internal Pullup

Resistors to VREG

GVDD_ABC

TAS5186A

SLES156 OCTOBER 2005

TYPICAL SYSTEM DIAGRAM

A schematic diagram for a typical system is appended at the end of the data sheet.

FUNCTIONAL BLOCK DIAGRAM

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RECOMMENDED OPERATING CONDITIONS

AUDIO SPECIFICATION

TAS5186A

SLES156 OCTOBER 2005

MIN

TYP

MAX

UNIT

PVDD_X

Half-bridge supply, SE

DC supply voltage at pin(s)

GVDD

Gate drive and guard ring supply voltage

DC voltage at pin(s)

10.8

13.2

VDD

Digital regulator supply

DC supply voltage at pin

10.8

13.2

Any value of R

PU,EXT

within

VPU

Pullup voltage supply

5.5

recommended range

Resistive load impedance, satellite

Recommended demodulation filter

L,SAT

channels

(1)

Resistive load impedance, subwoofer

Recommended demodulation filter

L,SUB

2.25

channel

Minimum output inductance under

output

Demodulation filter inductance

short-circuit condition

output,sat

Demodulation filter capacitance

output,sub

Demodulation filter capacitance

PWM

PWM frame rate

192

384

432

kHz

(1)

Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP.

PVDD_X = 40 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, F

PWM

= 384 kHz, case temperature =

75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless
otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

= 6

, 10% THD, clipped input signal

= 8

, 10% THD, clipped input signal

O,sat

Power output per satellite channel

= 6

, 0 dBFS, unclipped input signal

= 8

, 0 dBFS, unclipped input signal

= 3

, 10% THD, clipped input signal

= 4

, 10% THD, clipped input signal

O,sub

Power output, subwoofer

= 3

, 0 dBFS, unclipped input signal

= 4

, 0 dBFS, unclipped input signal

= 6

, P

= 25 W

0.3%

Total harmonic distortion + noise,
satellite

= 6

, 1 W

0.07%

THD + N

= 3

, P

= 50 W

0.5%

Total harmonic distortion + noise,
subwoofer

= 3

, 1 W

0.05%

Output integrated noise, satellite

A-weighted

Output integrated noise, subwoofer

A-weighted

SNR

System signal-to-noise ratio

A-weighted

105

Dynamic range

(1)

A-weighted, 60 dBFS input signal,

105

DNR

measured with TAS5086 PWM processor

= 0 W, all channels running 5.1 mode

(2)

22-

H Kwang-Sung inductors (see

4.5

Power dissipation due to idle losses

schematic for information)

idle

(IPVDDX)

= 0 W, 2.1 mode. 22-

H Kwang-Sung

2.2

inductors (see schematic for information)

(1)

SNR is calculated relative to 0-dBFS input level.

(2)

Actual system idle losses are affected by core losses of output inductors.

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ELECTRICAL CHARACTERISTICS

TAS5186A

SLES156 OCTOBER 2005

PWM

= 384 kHz, GVDD = 12 V, VDD = 12 V, T

(case temperature) = 75

C, unless otherwise noted. All performance is in

accordance with recommended operating conditions, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

VREG

Voltage regulator, only used as reference node

VDD = 12 V

3.3

3.6

Operating, 50% duty cycle

IVDD

VDD supply current

Idle, reset mode

50% duty cycle

IGVDD_X

Gate supply current per half-bridge

Idle, reset mode

50% duty cycle, without output filter or load, 5.1

110

mode. 22-

H Kwang-Sung inductors

IPVDD_X

Half-bridge idle current

50% duty cycle, without output filter or load, 2.1

mode. 22-

H Kwang-Sung inductors

OUTPUT STAGE MOSFETs

DSon

, LS Sat

Drain-to-source resistance, low side, satellite

= 25°C, includes metallization resistance

210

DSon

, HS Sat

Drain-to-source resistance, high side, satellite

= 25°C, includes metallization resistance

210

Dson

, LS Sub

Drain-to-source resistance, low side, subwoofer

= 25°C, includes metallization resistance

110

Dson

, HS Sub

Drain-to-source resistance, high side, subwoofer

= 25°C, includes metallization resistance

110

I/O PROTECTION

UVP, G

Undervoltage protection limit GVDD_X

UVP, hyst

(1)

Undervoltage protection hysteresis

250

OTW

(1)

Overtemperature warning

125

°C

Temperature drop needed below OTW temp. for

OTW

hyst

(1)

°C

OTW to be inactive after the OTW event

OTE

(1)

Overtemperature error

155

°C

Temperature drop needed below OTE temp. for SD

OTE

HYST

(1)

°C

to be released after the OTE event

OLCP

Overload protection counter

1.25

Overcurrent limit protection, satellite

Rocp = 18 k

4.5

Overcurrent limit protection, subwoofer

Rocp = 18 k

OCT

Overcurrent response time

210

Rocp

OC programming resistor range

Resistor tolerance = 5%

STATIC DIGITAL SPECIFICATION

High-level input voltage

PWM_X, M1, M2, M3, RESET

Low-level input voltage

0.8

LEAK

Input leakage current

Static condition

OTW/SHUTDOWN (SD)

Internal pullup resistor to DREG (3.3 V) for SD and

INT_PU

OTW

Internal pullup resistor only

3.3

3.6

High-level output voltage

External pullup: 4.7-k

resistor to 5 V

4.5

Low-level output voltage

= 4 mA

0.2

0.4

FANOUT

Device fanout OTW, SD

No external pullup

Devices

(1)

Specified by design.

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PVDD Supply Voltage V

G005

Satellite
1 Channel
T

= 75

Unclipped Input Signal

 Output Power W

PVDD Supply Voltage V

G006

Subwoofer
1 Channel
T

= 75

Unclipped Input Signal

 Output Power W

100

20 40 60 80 100 120 140 160 180 200 220 240

System Efficiency %

G007

5.1 Mode
PVDD = 40 V
T

= 25

L(SAT)

= 8

L(SUB)

= 4

 Total Output Power W

L(SAT)

= 6

L(SUB)

= 3

20 40 60 80 100 120 140 160 180 200 220 240

System Power Loss W

G008

5.1 Mode
PVDD = 40 V
T

= 25

 Total Output Power W

L(SAT)

= 8

L(SUB)

= 4

L(SAT)

= 6

L(SUB)

= 3

TAS5186A

SLES156 OCTOBER 2005

TYPICAL CHARACTERISTICS, 5.1 MODE (continued)

OUTPUT POWER

SUPPLY VOLTAGE

Figure 5.

Figure 6.

SYSTEM EFFICIENCY

SYSTEM POWER LOSS

TOTAL OUTPUT POWER

Figure 7.

Figure 8.

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THEORY OF OPERATION

POWER SUPPLIES

SYSTEM POWER-UP/DOWN SEQUENCE

Powering Down

Error Reporting

TAS5186A

SLES156 OCTOBER 2005

reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin on the same

To facilitate system design, the TAS5186A needs

side

the

PCB

the

TAS5186A.

only a 12-V supply in addition to a typical 39-V

recommended to follow the PCB layout of the

power-stage supply. An internal voltage regulator

TAS5186A

reference

design.

For

additional

provides suitable voltage levels for the digital and

information on the recommended power supply and

low-voltage analog circuitry. Additionally, all circuitry

required components, see the application diagrams

requiring a floating voltage supply, e.g., the high-side

given in this data sheet. The 12-V supply should be

gate drive, is accommodated by built-in bootstrap

powered from a low-noise, low-output-impedance

circuitry requiring only a few external capacitors.

voltage regulator. Likewise, the 39-V power-stage
supply is assumed to have low output impedance and

In order to provide outstanding electrical and acoustic

low noise. The power-supply sequence is not critical

characteristics, the PWM signal path including gate

due to the internal power-on-reset circuit. Moreover,

drive and output stage is designed as identical,

the TAS5186A is fully protected against erroneous

independent half-bridges. For this reason, each

power-stage turnon due to parasitic gate charging.

half-bridge has separate bootstrap pins (BST_X) and

Thus, voltage-supply ramp rates (dv/dt) are typically

power-stage supply pins (PVDD_X). Furthermore, an

noncritical.

additional pin (VDD) is provided as power supply for
all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_X and VDD on the printed-circuit board (PCB)

The

TAS5186A

does

not

require

power-up

by RC filters (see application diagram for details).

sequence. The outputs of the H-bridge remain in a

These

filters

provide

the

recommended

high-impedance state until the gate-drive supply

high-frequency isolation. Special attention should be

voltage (GVDD_X) and VDD voltage are above the

paid to placing all decoupling capacitors as close to

undervoltage protection (UVP) voltage threshold (see

their

associated

pins

possible.

general,

the Electrical Characteristics section of this data

inductance between the power-supply pins and

sheet).

Although

not

specifically

required,

decoupling

capacitors

must

avoided.

(See

recommended to hold RESET in a low state while

reference

board

documentation

for

additional

powering up the device.

information.)

When the TAS5186A is being used with TI PWM

For a properly functioning bootstrap circuit, a small

modulators

such

the

TAS5086,

special

ceramic capacitor must be connected from each

attention to the state of RESET is required, provided

bootstrap pin (BST_X) to the power-stage output pin

that the chipset is configured as recommended.

(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode

connected

between

the

gate-drive

power-supply pin (GVDD_X) and the bootstrap pin.

The TAS5186A does not require a power-down

When the power-stage output voltage is high, the

sequence. The device remains fully operational as

bootstrap capacitor voltage is shifted above the

long as the gate-drive supply (GVDD_X) voltage and

output voltage potential and thus provides a suitable

VDD voltage are above the undervoltage protection

voltage supply for the high-side gate driver. In an

(UVP)

threshold

level

(see

the

Electrical

application with PWM switching frequencies in the

Characteristics section of this data sheet). Although

range 352 kHz to 384 kHz, it is recommended to use

not specifically required, it is a good practice to hold

33-nF ceramic capacitors, size 0603 or 0805, for the

RESET low during power down, thus preventing

bootstrap capacitor. These 33-nF capacitors ensure

audible artifacts including pops and clicks

sufficient energy storage, even during minimal PWM

When the TAS5186A is being used with TI PWM

duty cycles, to keep the high-side power stage FET

modulators

such

the

TAS5086,

special

(LDMOS) fully started during all of the remaining part

attention to the state of RESET is required, provided

of the PWM cycle. In an application running at a

that the chipset is configured as recommended.

reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes

The

and

OTW

pins

are

both

active-low,

component selection, PCB placement and routing. As

open-drain

outputs.

Their

function

for

indicated,

each

half-bridge

has

independent

protection-mode signaling to a PWM controller or

power-stage supply pins (PVDD_X). For optimal

other system-control device.

electrical performance, EMI compliance, and system

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Device Protection System

OVERCURRENT (OC) PROTECTION WITH

TAS5186A

SLES156 OCTOBER 2005

Any fault resulting in device shutdown is signaled by

two protection systems. The first protection system

the SD pin going low. Likewise, OTW goes low when

controls the power stage in order to prevent the

the device junction temperature exceeds 125°C (see

output current from further increasing. i.e., it performs

the following table).

a current-limiting function rather than prematurely
shutting down during combinations of high-level
music

transients

and

extreme

speaker

OTW

DESCRIPTION

load-impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a

Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)

second

protection

system

triggers

latching

shutdown, resulting in the power stage being set in

Overload (OLP) or undervoltage (UVP)

the high-impedance (Hi-Z) state.

Overtemperature warning. Junction temperature
higher than 125°C, typical

For

added

flexibility,

the

threshold

Normal operation. Junction temperature lower than

programmable within a limited range using a single

125°C, typical

external resistor connected between the OC_ADJ pin
and AGND.

It should be noted that asserting RESET low forces

OC-Adjust Resistor Values

Maximum Peak Current Before

the SD and OTW signals high independently of faults

)

OC Occurs (A)

being present. It is recommended to monitor the

4.5 (sat.), 8 (sub.)

OTW signal using the system microcontroller and to
respond to an overtemperature warning signal by,

It should be noted that a properly functioning

e.g., turning down the volume to prevent further

overcurrent detector assumes the presence of a

heating of the device that would result in device

properly

designed

demodulation

filter

the

shutdown (OTE). To reduce external component

power-stage output. Short-circuit protection is not

count, an internal pullup resistor to 3.3 V is provided

provided directly at the output pins of the power stage

on both the SD and OTW outputs. Level compliance

but

only

the

speaker

terminals

(after

the

for 5-V logic can be obtained by adding external

demodulation filter). It is required to follow certain

pullup

resistors

(see

the

Electrical

guidelines when selecting the OC threshold and an

Characteristics section of this data sheet for further

appropriate demodulation inductor.

specifications).

For the lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output

The TAS5186A contains advanced protection circuitry

requirement

and

minimum

load

impedance.

carefully designed to facilitate system integration and

Higher-impedance loads require a lower OC

ease of use, as well as safeguarding the device from

threshold.

permanent failure due to a wide range of fault

The demodulation filter inductor must retain at

conditions such as short circuit, overload, and

least 5

H of inductance at twice the OC

undervoltage. The TAS5186A responds to a fault by

threshold setting.

immediately

setting

the

power

stage

high-impedance state (Hi-Z) and asserting the SD pin

Most inductors have decreasing inductance with

low. In situations other than overload, the device

increasing

temperature

and

increasing

current

automatically recovers when the fault condition has

(saturation).

some

degree,

increase

been removed, e.g., the supply voltage has increased

temperature naturally occurs when operating at high

or the temperature has dropped. For highest possible

output currents, due to inductor core losses and the

reliability, recovering from an overload fault requires

dc resistance of the inductor copper winding. A

external reset of the device no sooner than 1 second

thorough analysis of inductor saturation and thermal

after the shutdown (see the Device Reset section of

properties is strongly recommended.

this data sheet).

Setting the OC threshold too low might cause issues
such as lack of output power and/or unexpected
shutdowns due to sensitive overload detection.

CURRENT LIMITING AND OVERLOAD
DETECTION

In general, it is recommended to follow closely the
external component selection and PCB layout as

The device has independent, fast-reacting current

given in the application section.

detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by

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Overtemperature Protection

UNDERVOLTAGE PROTECTION (UVP) AND

DEVICE RESET

ACTIVE-BIAS CONTROL (ABC)

TAS5186A

SLES156 OCTOBER 2005

element in the audio path, i.e., split-cap capacitors or
series capacitor, to the desired potential before

The

TAS5186A

has

two-level

switching is started on the PWM outputs. (For

temperature-protection

system

that

asserts

recommended

configuration,

see

the

typical

active-low warning signal (OTW) when the device

application schematic included in this data sheet).

junction temperature exceeds 125°C (typical), and If
the device junction temperature exceeds 155°C

The start-up sequence can be controlled through

(typical), the device is put into thermal shutdown,

sequencing the M3 and RESET pins according to

resulting in all half-bridge outputs being set in the

Table 2

and

Table 3

high-impedance state (Hi-Z) and SD being asserted
low.

Table 2. 5.1 Mode--All Output Channels Active

RESET

OUT_BIAS

OUT_A, OUT_D,

COMMENT

_B, _C

_E, _F

POWER-ON RESET (POR)

Hi-Z

All outputs
disabled,

The UVP and POR circuits of the TAS5186A fully

nothing is

protect

the

device

any

power-up/down

and

switching.

brownout situation. While powering up, the POR

Active

Hi-Z

OUT_BIAS

circuit resets the overload circuit (OLP) and ensures

enabled, all

that all circuits are fully operational when the

other outputs
disabled

GVDD_X and VDD supply voltages reach 10 V
(typical).

Although

GVDD_X

and

VDD

are

Hi-Z

Active

OUT_BIAS
disabled, all

independently monitored, a supply voltage drop

other outputs

below the UVP threshold on any VDD or GVDD_X

switching

pin results in all half-bridge outputs immediately being
set in the high-impedance (Hi-Z) state and SD being

Table 3. 2.1 Mode--Only Output Channels A, B,

asserted low. The device automatically resumes

and C Active

operation when all supply voltages have increased
above the UVP threshold.

RESET

OUT_BIAS

OUT_A, OUT_D,

COMMENT

_B, _C

_E, _F

Hi-Z

All outputs
disabled,

When RESET is asserted low, the output FETs in all

nothing is

half-bridges are forced into a high-impedance (Hi-Z)

switching.

state.

Active

Hi-Z

OUT_BIAS
enabled, all

Asserting the RESET input low removes any fault

other outputs

information to be signaled on the SD output, i.e., SD

disabled

is forced high.

Hi-Z

Active

Hi-Z

OUT_BIAS
disabled, all

A rising-edge transition on the RESET input allows

other outputs

the device to resume operation after an overload

switching

fault.

When the TAS5186A is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as

Audible

pop

noises

are

often

associated

with

recommended.

single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem

has

been

virtually

eliminated

incorporating a proprietary active-bias control circuitry
as part of the TAS5186A feature set. By the use of
only a few passive external components (typically
resistors), the ABC can pre-charge the dc-blocking

GND_B

GVDD

/SD

/TW

PWM_E

PWM_F

/VALID1

PWM_A

PWM_C

PWM_B

PWM_D

GVDD

/VALID2

GND_D

GND_C

GND_F

GND_E

OUT_F

OUT_E

OUT_D

OUT_C

OUT_B

GND_A

OUT_A

PVDD

GND

Rev:

Page Title:

DIGITAL AUDIO & VIDEO DIVISION

TEXAS INSTRUMENTS INCORPORATED

Project:

File Name:

Date:

Engineer:

Page:

Size: A2

2.10

Jonas Svendsen

Power Stage

A758-SCH-001(2.10).DSN

TAS5086-5186V6EVM

Monday, September 12, 2005

Parts List No.2

Rev:

Page Title:

DIGITAL AUDIO & VIDEO DIVISION

TEXAS INSTRUMENTS INCORPORATED

Project:

File Name:

Date:

Engineer:

Page:

Size: A2

2.10

Jonas Svendsen

Power Stage

A758-SCH-001(2.10).DSN

TAS5086-5186V6EVM

Monday, September 12, 2005

Parts List No.2

Rev:

Page Title:

DIGITAL AUDIO & VIDEO DIVISION

TEXAS INSTRUMENTS INCORPORATED

Project:

File Name:

Date:

Engineer:

Page:

Size: A2

2.10

Jonas Svendsen

Power Stage

A758-SCH-001(2.10).DSN

TAS5086-5186V6EVM

Monday, September 12, 2005

Parts List No.2

Patents pending in circuitry design and layout (WO99/59241 & WO99/59242).

This circuitry may only be used together with the integrated circuit TAS5186 from Texas Instruments Incorporated.

POWER OUTPUT STAGE (SE)

LAYOUT NOTE:
PLACE NEAR
SPEAKER PINS

DESIGN NOTE:
SPLIT CAPS

DESIGN NOTE:
DEMODULATION
FILTER

DESIGN NOTE:
FILTER DISCHARGE

DESIGN NOTE:
EMI/ESD SNUBBERS

LAYOUT NOTE:
PLACE AFTER
FILTER CAPS

LAYOUT NOTE:
PLACE AFTER
SPLIT CAPS

LAYOUT NOTE:
PLACE AFTER
HEATSINK

C176
10nF

50V
0805

C176
10nF

50V
0805

R116
10.0k

1206

R116
10.0k

1206

R163
1.00R

0805

R163
1.00R

0805

PGND_EF

PWM_F

GVDD_DEF

VDD

PWM_E

PWM_D

RESET

GND

AGND

VREG

OC_ADJ

OTW

PWM_B

PWM_A

GVDD_ABC

BST_BIAS

OUT_BIAS

BST_A

PVDD_A

OUT_A

PGND_AB

OUT_B

PVDD_B

BST_B

BST_C

PVDD_C

OUT_C

PWM_C

PVDD_D

OUT_D

PGND_D

PGND_C

BST_D

BST_E

PVDD_E

OUT_E

PGND_EF

OUT_F

PVDD_F

BST_F

U100

PTAS5186

U100

PTAS5186

C162
10nF

50V
0805

C162
10nF

50V
0805

R153
2.70k

1206

R153
2.70k

1206

C126
270uF

50V

C126
270uF

50V

C183
10nF

50V
0805

C183
10nF

50V
0805

C140
470nF

63V

C140
470nF

63V

C144
470nF

63V

C144
470nF

63V

C165
10nF

50V
0805

C165
10nF

50V
0805

C171
10nF

50V
0805

C171
10nF

50V
0805

C104
100nF

0805
50V

C104
100nF

0805
50V

R164
1.00R

0805

R164
1.00R

0805

R170
1.00R

0805

R170
1.00R

0805

R160
1.00R

0805

R160
1.00R

0805

C107
100nF

0805
50V

C107
100nF

0805
50V

C102
1uF

0805

C102
1uF

0805

R161
1.00R

0805

R161
1.00R

0805

C173
10nF

50V
0805

C173
10nF

50V
0805

C163
10nF

50V
0805

C163
10nF

50V
0805

C177
10nF

50V
0805

C177
10nF

50V
0805

R162
1.00R

0805

R162
1.00R

0805

R167
1.00R

0805

R167
1.00R

0805

C166
10nF

50V
0805

C166
10nF

50V
0805

R154
2.70k

1206

R154
2.70k

1206

C128
270uF

50V

C128
270uF

50V

C120
270uF

50V

C120
270uF

50V

C180
10nF

50V
0805

C180
10nF

50V
0805

C110
10nF

1206
200V

C110
10nF

1206
200V

R122

470R

SFR16

R122

470R

SFR16

C111
10nF

1206
200V

C111
10nF

1206
200V

L145
22uH

8020P-01-200L

Kwang Sung

L145
22uH

8020P-01-200L

Kwang Sung

R125

1k8

SFR16

R125

1k8

SFR16

L142
10uH

8020P-02-100L

Kwang Sung

L142
10uH

8020P-02-100L

Kwang Sung

C105
100nF

0805
50V

C105
100nF

0805
50V

C115
10nF

1206
200V

C115
10nF

1206
200V

C131
270uF

50V

C131
270uF

50V

C161
10nF

50V
0805

C161
10nF

50V
0805

C125
1200uF

50V

C125
1200uF

50V

R120

1k8

SFR16

R120

1k8

SFR16

R121

1k8

SFR16

R121

1k8

SFR16

C167
10nF

50V
0805

C167
10nF

50V
0805

R169
1.00R

0805

R169
1.00R

0805

C117
1uF

0805

C117
1uF

0805

C109
100nF

0805
50V

C109
100nF

0805
50V

C168
10nF

50V
0805

C168
10nF

50V
0805

R166
1.00R

0805

R166
1.00R

0805

L141
22uH

8020P-01-200L

Kwang Sung

L141
22uH

8020P-01-200L

Kwang Sung

C103
10nF

0805

C103
10nF

0805

R100
0R

0603

R100
0R

0603

C181
10nF

50V
0805

C181
10nF

50V
0805

L140
22uH

8020P-01-200L

Kwang Sung

L140
22uH

8020P-01-200L

Kwang Sung

C123
270uF

50V

C123
270uF

50V

C112
10nF

1206
200V

C112
10nF

1206
200V

C145
470nF

63V

C145
470nF

63V

C142
1uF

63V

C142
1uF

63V

C101

100nF

0603

C101

100nF

0603

C100
1uF

0805

C100
1uF

0805

R103

18.2k

0603

R103

18.2k

0603

R123

1k8

SFR16

R123

1k8

SFR16

R168
1.00R

0805

R168
1.00R

0805

C169
10nF

50V
0805

C169
10nF

50V
0805

L143
22uH

8020P-01-200L

Kwang Sung

L143
22uH

8020P-01-200L

Kwang Sung

C141
470nF

63V

C141
470nF

63V

C172
10nF

50V
0805

C172
10nF

50V
0805

C178
10nF

50V
0805

C178
10nF

50V
0805

C127
270uF

50V

C127
270uF

50V

C174
10nF

50V
0805

C174
10nF

50V
0805

R155
2.70k

1206

R155
2.70k

1206

R152
2.70k

1206

R152
2.70k

1206

C130
270uF

50V

C130
270uF

50V

C106
100nF

0805
50V

C106
100nF

0805
50V

C124
1200uF

50V

C124
1200uF

50V

C114
10nF

1206
200V

C114
10nF

1206
200V

R124

1k8

SFR16

R124

1k8

SFR16

C108
100nF

0805
50V

C108
100nF

0805
50V

R151
2.70k

1206

R151
2.70k

1206

L144
22uH

8020P-01-200L

Kwang Sung

L144
22uH

8020P-01-200L

Kwang Sung

C122
270uF

50V

C122
270uF

50V

C182
10nF

50V
0805

C182
10nF

50V
0805

C143
470nF

63V

C143
470nF

63V

C179
10nF

50V
0805

C179
10nF

50V
0805

C129
270uF

50V

C129
270uF

50V

R165
1.00R

0805

R165
1.00R

0805

R171
1.00R

0805

R171
1.00R

0805

C175
10nF

50V
0805

C175
10nF

50V
0805

C121
270uF

50V

C121
270uF

50V

C164
10nF

50V
0805

C164
10nF

50V
0805

C170
10nF

50V
0805

C170
10nF

50V
0805

R115
10.0k

1206

R115
10.0k

1206

C160
10nF

50V
0805

C160
10nF

50V
0805

R117

15R

SFR16

R117

15R

SFR16

R150
2.70k

1206

R150
2.70k

1206

C113
10nF

1206
200V

C113
10nF

1206
200V

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

TAS5186ADDV

ACTIVE

HTSSOP

DDV

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5186ADDVG4

ACTIVE

HTSSOP

DDV

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5186ADDVR

ACTIVE

HTSSOP

DDV

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

TAS5186ADDVRG4

ACTIVE

HTSSOP

DDV

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

Addendum-Page 1

IMPORTANT NOTICE

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TAS5186A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TAS5186A