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Mailing Address:

Texas Instruments
Post Office Box 655303 Dallas, Texas 75265

Contents

iii

July 2004

SLES115

Contents

Section

Page

Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1

TAS5518 System Diagrams

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

TAS5518 Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.1

Audio Input/Output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.2

Audio Processing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3

PWM Processing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.4

General Features

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3

Physical Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1

Terminal Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2

Ordering Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.3

Terminal Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4

TAS5518 Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1

Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2

Clock, PLL, and Serial Data Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3

C Serial Control Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.4

Device Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.5

Digital Audio Processor (DAP)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5

TAS5518 DAP Architecture

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.1

TAS5518 DAP Architecture Diagrams

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.2

C Coefficient Number Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6

Input Crossbar Mixer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7

Biquad Filters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8

Bass and Treble Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9

Volume, Auto Mute, and Mute

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9.1

Auto Mute and Mute

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10

Loudness Compensation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10.1

Loudness Example

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11.2

Compression/Expansion Coefficient Computation Engine Parameters

. . . . . . . . . .

1.12

Output Mixer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13

PWM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13.1

DC Blocking (High Pass Enable/ Disable)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13.2

De-Emphasis Filter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13.3

Power Supply Volume Control (PSVC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13.4

AM Interference Avoidance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS5518 Controls and Status

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1

C Status Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1

General Status Register (0x01)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2

Error Status Register (0x02)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

TAS5518 Pin Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

Reset (RESET)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2

Power Down (PDN)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3

Backend Error (BKND_ERR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4

Speaker / Headphone Selector (HP_SEL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5

Mute (MUTE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

July 2004

SLES115

2.3

Device Configuration Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1

Channel Configuration Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2

Headphone Configuration Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3

Audio System Configurations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4

Recovery from Clock Error

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5

Power Supply Volume Control Enable

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6

Volume and Mute Update Rate

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.7

Modulation Index Limit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.8

Inter-channel Delay

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4

Master Clock and Serial Data Rate Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1

PLL Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5

Bank Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1

Manual Bank Selection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2

Automatic Bank Selection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3

Bank Set

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4

Bank Switch Timeline

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5

Bank Switching Example 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.6

Bank Switching Example 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Dynamic Performance (At Recommended Operating Conditions at 25°C)

. . . . . . . . . . . . . . . .

3.3

Recommended Operating Conditions (over 0°C to 70°C)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4

Electrical Characteristics Over Recommended Operating Conditions

. . . . . . . . . . . . . . . . . . . .

3.5

PWM Operation at Recommended Operating Conditions Over 0°C to 70°C

. . . . . . . . . . . . . . .

3.6

Switching Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1

Clock Signals Over Recommended Operating Conditions

. . . . . . . . . . . . . . . . . . . . .

3.6.2

Serial Audio Port

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3

C Serial Control Port Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.4

Reset Timing (RESET)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.5

Power-Down (PDN) Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.6

Backend Error (BKND_ERR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.7

MUTE Timing--MUTE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.8

Headphone Select (HP_SEL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.9

Volume Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7

Serial Audio Interface Control and Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1

S Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.2

Left Justified

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3

Right Justified

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Serial Control Interface (Slave Address 0x36)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

General I

C Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

Single and Multiple Byte Transfers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

Single Byte Write

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4

Multiple Byte Write

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5

Incremental Multiple Byte Write

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6

Single Byte Read

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7

Multiple Byte Read

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Control I

C Register Summary

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

July 2004

SLES115

Serial Control Interface Register Definitions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1

Clock Control Register (0x00)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2

General Status Register 0 (0x01)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

Error Status Register (0x02)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4

System Control Register 1 (0x03)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5

System Control Register 2 (0x04)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6

Channel Configuration Control Register (0x05-X0C)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7

Headphone Configuration Control Register (0x0D)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8

Serial Data Interface Control Register (0x0E)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9

Soft Mute Register (0x0F)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10

Automute Control Register(0x14)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11

Automute PWM Threshold and Backend Reset Period (0x15)

. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12

Modulation Index Limit Register (0x16)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13

Interchannel Channel Delay Registers (0x1B - 0x22) and Offset Register (0x23)

. . . . . . . . . .

6.14

Bank Switching Command (0x40)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15

Input Mixer Registers (0x41 0x48, Channels 1 - 8)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16

Bass Management Registers (0x49 0x50)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.17

Biquad Filters Register (0x51 0x88)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.18

Bass and Treble Bypass Register (0x89 0x90, Channels 1 - 8)

. . . . . . . . . . . . . . . . . . . . . . . .

6.19

Loudness Registers (0x91 0x95)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.20

DRC1 Control (0x96, Channels 1-7)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.21

DRC2 Control (0x97, Channel 8)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.22

DRC1 Data Registers (0x98 0x9C)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.23

DRC2 Data Registers (0x9D 0xA1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.24

DRC Bypass Registers (0xA2 0xA9)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.25

8x2 Output Mixer Registers (0xAA 0xAF)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.26

8x3 Output Mixer Registers (0xB0 0xB1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.27

Volume Biquad Register (0xCF)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.28

Volume Treble and Bass Slew Rates (0xD0)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.29

Volume Registers (0xD1 - 0xD9)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.30

Bass Filter Set Register (0xDA)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.31

Bass Filter Index Register (0xDB)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.32

Treble Filter Set Register (0xDC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.33

Treble Filter Index (0xDD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.34

AM Mode Register (0xDE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.35

PSVC Range Register (0xDF)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.36

General Control Register (0xE0)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.37

Incremental Multiple Write Append Register (0xFE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAS5518 Example Application Schematic

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

July 2004

SLES115

List of Illustrations

Figure

Title

Page

1-1. TAS5518 Functional Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2. Typical TAS5518 Application (DVD Receiver)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3. Recommended TAS5518 + TAS5121 Channel Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4. TAS5518 DAP Architecture With I

C Registers (Fs 3 96 kHz)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5. TAS5518 Architecture With I

C Registers (Fs = 176.4 kHz or Fs = 192 kHz)

. . . . . . . . . . . . . . . . . . .

1-6. TAS5518 Detailed Channel Processing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-7. 5.23 Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-8. Conversion Weighting Factors--5.23 Format to Floating Point

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-9. Alignment of 5.23 Coefficient in 32-Bit I

C Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-10. 25.23 Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-11. Alignment of 5.23 Coefficient in 32-Bit I

C Word

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-12. Alignment of 25.23 Coefficient in Two 32-Bit I

C Words

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-13. TAS5518 Digital Audio Processing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-14. Input Crossbar Mixer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-15. Biquad Filter Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-16. Auto Mute Threshold

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-17. Loudness Compensation Functional Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-18. Loudness Example Plots

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-19. DRC Positioning in TAS5518 Processing Flow

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-20. Dynamic Range Compression (DRC) Transfer Function Structure

. . . . . . . . . . . . . . . . . . . . . . . . . . .

1-21. Output Mixers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-22. De-emphasis Filter Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-23. Power Supply and Digital Gains (Log Space)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-24. Power Supply and Digital Gains (Linear Space)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-25. Block Diagrams of Typical Systems Requiring TAS5518 Automatic AM Interference

Avoidance Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1. Slave Mode Serial Data Interface Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2. SCL and SDA Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3. Start and Stop Conditions Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4. Reset Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5. Power-Down Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6. Error Recovery Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-7. Mute Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8. HP_SEL Timing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-9. I

S Format 64 Fs Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-10. Left Justified 64 Fs Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-11. Right Justified 64 Fs Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1. Typical I

C Sequence

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2. Single Byte Write Transfer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3. Multiple Byte Write Transfer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4. Single Byte Read Transfer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5. Multiple Byte Read Transfer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

vii

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List of Tables

Table

Title

Page

1-1. Serial Data Formats

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-2. TAS5518 Audio Processing Feature Sets

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)

. . . . . . . . . . . . . . . . . . . . . . . . . .

1-4. Bass and Treble Filter Selections

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5. Linear Gain Step Size

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-6. Default Loudness Compensation Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-7. Loudness Function Parameters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-8. DRC Recommended Changes From TAS5518 Defaults

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1. Device Outputs During Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2. Values Set During Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-3. Device Outputs During Power Down

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-4. Device Outputs During Backend Error

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-5. Description of the Channel Configuration Registers (0x05 to 0x0C)

. . . . . . . . . . . . . . . . . . . . . . . . . . .

2-6. Recommended TAS5518 Configurations for Texas Instruments Power Stages

. . . . . . . . . . . . . . . . .

2-7. Audio System Configuration (General Control Register 0xE0)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-8. Volume Ramp Rates in ms

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-9. Inter-Channel Delay Default Values

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1. Clock Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2. General Status Register (0x01)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-3. Error Status Register (0X02)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-4. System Control Register 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-5. System Control Register 2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-6. Channel Configuration Control Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-7. Headphone Configuration Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-8. Serial Data Interface Control Register Format

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-9. Soft Mute Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-10. Automute Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-11. Automute PWM Threshold and Backend Reset Period

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-12. Modulation Index Limit Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-13. Interchannel Channel Delay Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-14. Channel Offset Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-15. Bank Switching Command

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-16. Input Mixer Registers Format (0x41 0x48, Channels 1 - 8)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-17. Bass Management Registers Format (0x49 0x50)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-18. Biquad Filters Registers Format (0x51 0x88)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass)

. . . . . . . . . . . . . . . . . .

6-20. Bass and Treble Bypass Register Format (0x89-0x90)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-21. Loudness Registers Format (0x91 0x95)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-22. DCR1 Control (0x96, Channels 1-7)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-23. DRC2 Control (0x97, Channel 8)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-24. DRC1 Data Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-25. DRC2 Data Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-26. DRC Bypass Registers Format (0xA2-0xA9)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-27. Output Mixer Control Register Format (Upper 4 Bytes)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-28. Output Mixer Control (Lower 4 Bytes)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-29. Output Mixer Control (Upper 4 Bytes)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-30. Output Mixer Control (Middle 4 Bytes)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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6-31. Output Mixer Control (Lower 4 Bytes)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-32. Volume Biquad Register Format (Default = All-pass)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-33. Volume Gain Update Rate (Slew Rate)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-34. Treble and Bass Gain Step Size (Slew Rate)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-35. Volume Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-36. Master and Individual Volume Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-37. Channel 8 Sub Woofer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-38. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and

Left Surround in Eight Channel Configuration)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-39. Channel 4 and 3 (Right and Left Rear)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-40. Channel 7, 2, 1 (Center, Right Front, and Left Front)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-41. Bass Filter Index Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-42. Bass Filter Index

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-43. Channel 8 Sub Woofer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-44. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right

and Left Surround in Eight Channel Configuration)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-45. Channel 4 and 3 (Right and Left Rear)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-46. Channel 7, 2, 1 (Center, Right Front, and Left Front)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-47. Treble Filter Index Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-48. Treble Filter Index

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-49. AM Mode Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-50. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)

. . . . . . . . . . . . . . . . . . . . . . .

6-51. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)

. . . . . . . . . . . . . . . . . . . . .

6-52. PSVC Range Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-53. General Control Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction

SLES115 -- August 2004

TAS5518

Introduction

The TAS5518 is an eight channel digital pulse width a modulator (PWM) that provides superior dynamic range

performance and a high level of system integration. The typical dynamic range in a well-designed system is

110 dB and the power supply volume control (PSVC) feature provides up to 24 dB of additional dynamic range

at normal listening levels.

The TAS5518 is designed to interface seamlessly with most audio digital signal processors. This device

automatically adjusts control configurations in response to clock and data rate changes and idle conditions.

This enables the TAS5518 to provide an easy to use control interface with relaxed timing requirements.

The TAS5518 can drive eight channels of H-bridge power stages. Texas Instruments H-bridge devices

TAS5111, TAS5112, and TAS5182 + FETs are designed to work seamlessly with the TAS5518. The TAS5518

supports both single-ended or bridge-tied load configurations. It also provides a high-performance differential

output to drive an external differential input analog headphone amplifier (such as the TPA112).

The TAS5518 uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.

The 8x over sampling, combined with a 5

-order noise shaper, provides a broad flat noise floor and excellent

dynamic range from 20 Hz to 20 kHz.

The TAS5518 is a clock slave-only device. It receives MCLK, SCLK, and LRCLK from other system

components. It accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs and a 64-Fs bit clock.

PWM_HPP& MR

PWM_HPP & ML

MCLK

XTL_ OUT

XTL_ IN

PLL_FLTM

PLL_FLTP

OSC CAP

SCLK

LRCLK

SDIN1

SDIN2

SDIN3

SDIN4

SDA

SCL

VR_PLL AVDD_PLL AVSS_PLL AVDD_REF VBGAP VRA_PLL VRD_PLL DVDD DVSS AVDD AVSS

PWM Section

PWM AP& Am7 Center

PWM AP& AM4 R Rear

PWM AP& AM3 L Rear

PWM AP& AM8 Sub woofer

PWM AP& AM1 L Front

PWM AP& AM2 R Front

Clock,

PLL,

and

Serial Data I/F

PWM AP& AM5 L Surround

PWM L Line Out

PWM AP& AM6 R Surround

PWM R Line Out

8 x 2 Crossbar Mixer

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

Soft

Tone

Biquads

Loud

Comp DRC

8 x 8 Crossbar Mixer

Digital Audio Processor

VALID

System Control

DAP

Control

PWM Control

Control

Output Control

Det

PSVC

PWM

Emph

Interpo

late

SRC

Block

Power Supply

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

PWM

Emph

Interpo

late

SRC

Block

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

RESET

PDN

MUTE

HP_SEL

BKND_ERR

Serial

Control

Volume

Control

PSVC

Figure 1-1. TAS5518 Functional Structure

Introduction

SLES115 -- August 2004

TAS5518

1.1

TAS5518 System Diagrams

Typical applications for the TAS5518 are 6- to 8-channel audio systems such as DVD receiver or AV receiver.

Figure 1-2 shows the basic system diagram of the DVD receiver.

DVD Loader

Power Supply

Tuner

TAS5518

Texas Instruments

Digital Audio Amplifier

MPEG Decoder

Front-Panel Controls

Micro

Figure 1-2. Typical TAS5518 Application (DVD Receiver)

Figure 1-3 shows the recommended channel configuration when using the TAS5518 with the TAS5121 power

stage. Note that each channel is normally dedicated to a particular function.

TAS5518

TAS5121

PWM_M_1

PWM_P_1

PWM_M_2

PWM_P_2

PWM_M_3

PWM_P_3

PWM_M_4

PWM_P_4

PWM_M_7

PWM_P_7

PWM_M_8

PWM_P_8

PWM_M_5

PWM_P_5

PWM_M_6

PWM_P_6

LEFT

RIGHT

LEFT

SURROUND

CENTER

SUBWOOFER

RIGHT

SURROUND

LEFT BACK

SURROUND

RIGHT BACK

SURROUND

SDIN1,2,3,4 (8 chan. PCM)

Clocks

I2C Control

& Status

HW Control

& Status

PWM to Analog

(Line Level)

Lineout Left

Lineout Right

PWM to Analog

(Headphone Level)

Headphone

Out Left

Headphone

Out Right

Figure 1-3. Recommended TAS5518 + TAS5121 Channel Configuration

Introduction

SLES115 -- August 2004

TAS5518

1.2

TAS5518 Features

1.2.1 Audio Input / Output

Automatic Master Clock Rate and Data Sample Rate Detection

Eight Serial Audio Input Channels

Eight PWM Audio Output Channels Configurable as Six Channels With Stereo Line Out or Eight Channels

Line Output is a PWM Output to Drive an External Differential Input Operational Amplifier

Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112

PWM Outputs Support Single Ended and Bridge Tied Loads

32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates

Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I

64 x Fs Bit Clock Rate

128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates (Up to a Maximum of 50 MHz)

1.2.2 Audio Processing

48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features

Volume Control Range +36 dB to 127 dB

Master Volume Control Range of +18 dB to 100 dB

Eight Individual Channel Volume Control Range of +18-dB to -127-dB

Programmable Soft Volume and Mute Update Rates

Four Bass and Treble Tone Controls with ±18-dB Range, Selectable Corner Frequencies, and 2

Order

Slopes

L, R, and C

LS, RS

LR, RR

Sub

Configurable Loudness Compensation

Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes

Seven Bi-quads Per Channel

Full 8x8 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input

Channels

8x2 Output Mixer Channels 1-6. Each Output Can Be Any Ratio of Any Two Signal Processed Channels

8x3 Output mixer Channels 7 and 8. Each Output can be Any Ratio of Any Three Signal Processed

Channels

Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically (Based on

Specific Data Rates)

DC Blocking Filters

Able to Support a Variety of Bass Management Algorithms

Introduction

SLES115 -- August 2004

TAS5518

1.3

Physical Characteristics

1.3.1 Terminal Assignments

VR_PWM
PWM_P_4
PWM_M_4
PWM_P_3
PWM_M_3
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VALID
DVSS
BKND_ERR
DVDD
DVSS
DVSS
VR_DIG

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

VRA_PLL

PLL_FLT_RET

PLL_FLTM

PLL_FLTP

AVSS
AVSS

VRD_PLL

AVSS_PLL

AVDD_PLL

VBGAP

RESET

HP_SEL

PDN

MUTE
DVDD

DVSS

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

TQFP PACKAGE

(TOP VIEW)

VR_DPLL

OSC_CAP

XTL_OUT

XTL_IN

RESER

VED

RESER

VED

RESER

VED

SDA

SCL

LRCLK

SCLK

SDIN4

SDIN3

SDIN2

SDIN1

PSVC

RESER

VED

MCLK

PWM_HPPR

PWM_HPMR

PWM_HPPL

PWM_HPML

PWM_P_6

PWM_M_6

PWM_P_5

PWM_M_5

DVDD_PWM

DVSS_PWM

PWM_P_8

PWM_M_8

PWM_P_7

PWM_M_7

1.3.2 Ordering Information

PLASTIC 64-PIN PQFP (PN)

0°C to 70°C

TAS5518PAG

1.3.3 Terminal Descriptions

TERMINAL

I/O

5-V

TERMIN-

DESCRIPTION

NO.

NAME

I/O

5-V

TOLERANT

TERMIN-

ATION

DESCRIPTION

VRA_PLL

Voltage reference for PLL analog supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected

between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.

PLL_FLT_RET

PLL external filter return

PLL_FLTM

PLL negative input. Connected to PLL_FLT_RTN via an RC network

PLL_FLTP

PLL positive input. Connected to PLL_FLT_RTN via an RC network

AVSS

Analog ground

AVSS

Analog ground

Introduction

SLES115 -- August 2004

TAS5518

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

VRD_PLL

Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected

between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.

AVSS_PLL

Analog ground for PLL. This terminal should reference the same ground as power
terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be
minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground distribution techniques to achieve a quiet ground reference
at this terminal.

AVDD_PLL

3.3-V analog power supply for PLL This terminal can be connected to the same
power source used to drive power terminal DVDD, but to achieve low PLL jitter, this
terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor.

VBGAP

Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.
Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.

RESET

5 V

Pull up

System reset input, active low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that restores the
TAS5518 to its default conditions, sets the valid output low, and places the PWM
in the hard mute (M) state. Master volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 4-5 ms. device
initialization and set the volume at mute.

HP_SEL

5 V

Pull up

Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected
headphone is off.

PDN

5 V

Pull up

Power down, active low. PDN powers down all logic and stops all clocks whenever
a logic low is applied. The internal parameters are preserved through a power down
cycle, as long as a RESET is not active. The duration for system recovery from
power down is 100 ms.

MUTE

5 V

Pull up

Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a
logic high) The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.

DVDD

Digital power 3.3-V supply for digital core and most of I/O buffers

DVSS

Digital ground for digital core and most of I/O buffers

VR_DPLL

Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital PLL logic. A 0.1-µF low ESR capacitor should be

connected between this terminal and DVSS_CORE. This terminal must not be
used to power external devices.

OSC_CAP

Oscillator capacitor

XTL_OUT

XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the
recommended crystal type.

XTL_IN

XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5518 via use of an external fundamental mode
crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the
recommended crystal type.

RESERVED

Connect to digital ground

RESERVED

Connect to digital ground

RESERVED

Connect to digital ground

SDA

DIO

5 V

C serial control data interface input / output

SCL

5 V

C serial control clock input output

LRCLK

5 V

Serial audio data left / right clock (sampling rate clock)

SCLK

5 V

Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data
bit clock that is supplied to the serial bit clock to other I

S bus.

Introduction

SLES115 -- August 2004

TAS5518

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

SDIN4

5 V

Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

SDIN3

5 V

Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

SDIN2

5 V

Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

SDIN1

5 V

Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four

discrete (stereo) data formats and is capable of inputting data at 64 Fs.

PSVC

Power supply volume control PWM output

VR_DIG

Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be

connected between this terminal and DVSS. This terminal must not be used to
power external devices

DVSS

Digital ground

DVSS

Digital ground

DVDD

3.3-V digital power supply

BKND_ERR

Pull up

Active low. A backend error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in all system parameters unaffected, while all
H-bridge drive signals going to a hard mute (M) state.

DVSS

Digital ground

VALID

Output indicating validity of PWM outputs active high

PWM_M_1

PWM 1 output (differential -)

PWM_P_1

PWM 1 output (differential +)

PWM_M_2

PWM 2 output (differential -)

PWM_P_2

PWM 2 output (differential +)

PWM_M_3

PWM 3 output (differential -)

PWM_P_3

PWM 3 output (differential +)

PWM_M_4

PWM 4 output (differential -)

PWM_P_4

PWM 4 output (differential +)

VR_PWM

Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor

should be connected between this terminal and DVSS_PWM. This terminal must
not be used to power external devices.

PWM_M_7

PWM 7 (Line out L) output (differential -)

PWM_P_7

PWM 7 (Line out L) output (differential +)

PWM_M_8

PWM 8 (Line out R) output (differential -)

PWM_P_8

PWM 8 (Line out R) output (differential +)

DVSS_PWM

Digital ground for PWM

DVDD_PWM

3.3-V digital power supply for PWM

PWM_M_5

PWM 5 output (differential -)

PWM_P_5

PWM 5 output (differential +)

PWM_M_6

PWM 6 output (differential -)

PWM_P_6

PWM 6 output (differential +)

PWM_HPML

PWM left channel headphone (differential -)

PWM_HPPL

PWM left channel headphone (differential +)

PWM_HPMR

PWM right channel headphone (differential -)

PWM_HPPR

PWM right channel headphone (differential +)

Introduction

SLES115 -- August 2004

TAS5518

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

MCLK

5 V

Pulldown MCLK is a 3.3-V clock master clock input. The input frequency of this clock can

range from 4 MHz to 50 MHz.

RESERVED

Connect to digital ground

NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output

2. All pullups are 200-µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure

proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pull ups must be able to sink 200 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must

be able to source 200 µA, while maintaining a logic `1' drive level.

3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.

4. 13.5-MHz crystal (HCM49)

1.4

TAS5518 Functional Description

Figure 1-4 shows the TAS5518 functional structure. The next sections describe the TAS5518 functional

blocks:
·

Power Supply

Clock, PLL, and Serial Data Interface

Serial Control Interface

Device Control

Digital Audio Processor (DAP)

Pulse Width Modulation (PWM) Processor

1.4.1 Power Supply

The power supply section contains supply regulators that provide analog and digital regulated power for

various sections of the TAS5518. The analog supply supports the analog PLL, while digital supplies support

the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control

(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.

1.4.2 Clock, PLL, and Serial Data Interface

The TAS5518 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts

MCLK, SCLK, and LRCLK as inputs only.

The TAS5518 uses the external crystal to provide a time base for:
·

Continuous data and clock error detection and management

Automatic data rate detection and configuration

Automatic MCLK rate detection and configuration (automatic bank switching)

Supporting I

C operation/ communication while MCLK is absent

The TAS5518 automatically handles clock errors, data rate changes, and master clock frequency changes

without requiring intervention from an external system controller. This feature significantly reduces system

complexity and design.

Introduction

SLES115 -- August 2004

TAS5518

1.4.2.1

Serial Audio Interface

The TAS5518 operates as a slave only / receive only serial data interface in all modes. The TAS5518 has four

PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2,

SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two's complement format.

The serial data input interface of the TAS5518 can be configured in right justified, I

S, or left-justified modes.

The serial data interface format is specified using the I

C data interface control register. The supported formats

and word lengths are shown in Table 1-1.

Table 1-1. Serial Data Formats

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD LENGTHS

Right justified

I2S

Left Justified

Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5518 accepts 32-, 38-, 44.1-, 48-, 88.2-,

96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I

S serial data formats using

a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).

The parameters of this clock and serial data interface are I

C configurable.

1.4.3 I

C Serial Control Interface

The TAS5518 has an I

C serial control slave interface (address 0x36) to receive commands from a system

controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz)

operations without wait states. Since the TAS5518 has a crystal time base, this interface operates even when

MCLK is absent.

The serial control interface supports both single byte and multi-byte read / write operations for status registers

and the general control registers associated with the PWM. However, for the DAP data processing registers,

the serial control interface also supports multiple byte (4 byte) write operations.

The I

C supports a special mode which permits I

C write operations to be broken up into multiple data write

operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations

that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.

This permits the system to incrementally write large register values without blocking other I

C transactions.

In order to use this feature, the first chunk of data is written to the target I

C address and each subsequent

chunk of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent.

An incremental read operation is not supported.

1.4.4 Device Control

The TAS5518 control section provides the control and sequencing for the TAS5518. The device control

provides both high and low level control for the serial control interface, clock and serial data interfaces, digital

audio processor, and pulse width modulator sections.

1.4.5 Digital Audio Processor (DAP)

The DAP arithmetic unit is used to implement all audio processing functions soft volume, loudness

compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing.

Figure 1-6 shows the TAS5518 DAP architecture.

Introduction

SLES115 -- August 2004

TAS5518

The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section.

The DAP supports two configurations, one for 32-kHz 96-kHz data and one for 176.4-kHz to 192-kHz data.

1.4.5.1

TAS5518 Audio Processing Configurations

The 32 - 96 kHz configuration supports eight channels of data processing that can be configured as eight

channels or six channels with two channels for separate stereo line outputs.

The 176.4 - 192 kHz configuration supports three channels of signal processing with five channels passed

though (or derived from the three processed channels).

To efficiently support the processing requirements of both multi-channel 32 96-kHz data and the two channel

176.4 and 192-kHz data, the TAS5518 supports separate audio processing features for 32 96-kHz data rates

and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5518 processing feature sets.

1.4.5.2

TAS5518 Audio Signal Processing Functions

The DAP provides 10 primary signal processing functions.
1. The data processing input has a full 8x8 input crossbar mixer. This enables each input to be any ratio of

the eight input channels.

2. Two I

C programmable threshold detectors in each channel support auto mute.

3. Seven biquads per channel
4. Four soft bass and treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd

order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:
-

Bass and Treble 1: Channel 1 (Left), Channel 2 (Right), and Channel 7 (Center)

Bass and Treble 2: Channel 3 (Left Surround) and Channel 4 (Right Surround)

Bass and Treble 3: Channel 5 (Left Back Surround) and Channel 6 (Right Back Surround)

Bass and Treble 4: Channel 8 (Subwoofer)

5. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to

127 dB. This permits a total volume device control range of +36 dB to 127 dB plus mute. The master

volume control can be configured to control six or eight channels. The DAP soft volume and mute update

interval is I

C programmable. The update is performed at a fixed rate regardless of the sample rate.

6. Programmable loudness compensation that is controlled via the combination of the master and individual

volume settings.

7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values are provided

used as input parameters using the maximum RMS (master volume x individual channel volume).

8. 8x2 output mixer (channels 1-6). Each output can be any ratio of any two signal processed channels.
9. 8x3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal processed channels.
10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate

dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be

automatically selected for one or more data sample rates or can be manually selected under I

C program

control. This feature enables coefficients for different sample rates to be stored in the TAS5518 and then

select when needed.

Introduction

SLES115 -- August 2004

TAS5518

Table 1-2. TAS5518 Audio Processing Feature Sets

FEATURE

32 - 96 kHz

8 CHANNEL FEATURE SET

32 - 96 kHz

6 + 2 LINE OUT FEATURE SET

176.4- AND 192-kHz

FEATURE SET

Signal processing
channels

6 + 2

Pass through channels

N/A

Master volume

1 for eight channels

1 for six channels

1 for three channels

Individual channel
volume controls

Bass and treble tone
controls

Four Bass and Treble tone controls

with ±18 dB range, programmable

corner frequencies, and 2nd order

slopes

L, R and C (Ch 1, 2, and 7)

LS, RS (Ch 3 and 4)

LBS, RBS (Ch 5 and 6)

Sub (Ch 8)

Four Bass and Treble tone controls

with ±18 dB range, programmable

corner frequencies, and 2nd order

slopes

L, R and C (Ch 1, 2, and 7)

LS, RS (Ch 3 and 4)

Sub, (Ch 8)

Line L and R (Ch 5 and 6)

Two Bass and Treble tone controls

with ±18 dB range, programmable

corner frequencies, and 2nd order

slopes

L and R (Ch 1 and 2)

Sub (Ch 8)

Biquads

Dynamic range
compressors

DRC1 for seven satellites and DRC2

for sub

DRC1 for five satellites and DRC2

for sub (Ch 5 and 6 Uncompressed)

DRC1 for two satellites and DRC2

for sub

Input output
mapping/mixing

Each of the eight signal-processing channels input can be any ratio of the
eight input channels.
Each of the eight outputs can be any ratio of any two processed channels.

Each of the three

signal-processing channels or the

five pass-though channels inputs

can be any ratio of the eight input

channels.

Each of the eight outputs can be

any ratio of any of the three

processed or five bypass

channels.

DC blocking filters
(Implemented in PWM
Section)

Eight channels

Digital de-emphasis
(Implemented in PWM
Section)

Eight channels for 32 kHz, 44.1 kHz,

and 48 kHz

Six channels for 32 kHz, 44.1 kHz,

and 48 kHz

N/A

Loudness

Eight channels

Six channels

Three channels

Number of Coefficient
sets Stored

Three additional coefficient sets can be stored in memory

1.5

TAS5518 DAP Architecture

1.5.1 TAS5518 DAP Architecture Diagrams

Figure 1-4 shows the TAS5518 DAP architecture for Fs = 96 kHz. Note the TAS5518 bass management

architecture shown in channels 1, 2, 7, and 8. Note that the I

C registers are shown to help the designer

configure the TAS5518.

Figure 1-5 shows the TAS5518 architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels 1,

2, and 8 contain all the features. Channels 3-7 are pass-through except for master volume control.

Figure 1-6 shows TAS5518 detailed channel processing. The output mixer is 8X2 for channels 1-6 and *X3

for channels 7 and 8.

Introduction

SLES115 -- August 2004

TAS5518

Coeff = 0 (lin)

(I2C 0x4F)

(I2C 0x50)

Coeff = 1 (lin)

IP Mixer 1

(I2C 0x41)

IP Mixer 2

(I2C 0x42)

IP Mixer 3

(I2C 0x43)

IP Mixer 4

(I2C 0x44)

IP Mixer 5

(I2C 0x45)

IP Mixer 6

(I2C 0x46)

IP Mixer 7

(I2C 0x47)

IP Mixer 8

(I2C 0x48)

Coeff = 0 (lin)

(I2C 0x4A)

Coeff = 0 (lin)

(I2C 0x49)

Coeff = 0 (lin)

(I2C 0x4C)

Coeff = 1 (lin)

(I2C 0x4D)

Coeff = 0 (lin)

(I2C 0x4B)

Coeff = 0 (lin)

(I2C 0x4E)

SDIN1-L(L)

SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

Bass &

Treble 1

(0xDA-

0xDD)

L to

PWM1

OP Mixer 1

(I2C 0xAA)

8X2 Output

Mixer

7 DAP1

(0x51-

0x57)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 1

(0xDA-

0xDD)

R to

PWM2

OP Mixer 2

(I2C 0xAB)

8X2 Output

Mixer

7 DAP2

(0x58-

0x5E)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 2

(0xDA-

0xDD)

LS to

PWM3

OP Mixer 3

(I2C 0xAC)

8X2 Output

Mixer

7 DAP3

(0x5F-

0x65)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 2

(0xDA-

0xDD)

RS to

PWM4

OP Mixer 4

(I2C 0xAD)

8X2 Output

Mixer

7 DAP4

(0x66-

0x6C)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 3

(0xDA-

0xDD)

LBS to

PWM5

OP Mixer 5

(I2C 0xAE)

8X2 Output

Mixer

7 DAP5

(0x6D-

0x73)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 3

(0xDA-

0xDD)

RBS to

PWM6

OP Mixer 6

(I2C 0xAF)

8X2 Output

Mixer

7 DAP6

(0x74-

0x7A)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 1

(0xDA-

0xDD)

C to

PWM7

OP Mixer 7

(I2C 0xB0)

8X3 Output

Mixer

5 DAP7

(0x7D-

0x81)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 4

(0xDA-

0xDD)

Sub to

PWM8

OP Mixer 8

(I2C 0xB1)

8X3 Output

Mixer

5 DAP8

(0x84-

0x88)

Loud-

ness

(0x91-

0x95)

DRC2

(0x9D-

0xA1)

2 DAP7

(0x7B-

0x7C)

2 DAP8

(0x82-

0x83)

DAP1

Volume

(0xD1)

Master Vol

(0xD9)

DAP2

Volume

(0xD2)

Master Vol

(0xD9)

DAP3

Volume

(0xD3)

Master Vol

(0xD9)

DAP4

Volume

(0xD4)

Master Vol

(0xD9)

DAP5

Volume

(0xD5)

Master Vol

(0xD9)

DAP6

Volume

(0xD6)

Master Vol

(0xD9)

DAP7

Volume

(0xD7)

Master Vol

(0xD9)

DAP8

Volume

(0xD8)

Master Vol

(0xD9)

Max Vol

SDIN1-L(L)

SDIN1-R(R)

SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)

SDIN2-L(LS)

SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)

SDIN2-R(RS)

SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)

SDIN3-L(LBS)

SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)

SDIN3-R(RBS)

SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R(RBS)

SDIN4-L(C)

SDIN4-R (LFE)

SDIN1-L(L)
SDIN1-R(R)
SDIN2-L(LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R(RBS)
SDIN4-L (C)

SDIN4-R(LFE)

Default input is BOLD

Figure 1-4. TAS5518 DAP Architecture With I

C Registers (Fs 96 kHz)

Introduction

SLES115 -- August 2004

TAS5518

IP Mixer 1

(I2C 0x41)

8 X 8

Crossbar

Input Mixer

IP Mixer 2

(I2C 0x42)

8 X 8

Crossbar

Input Mixer

IP Mixer 3

(I2C 0x43)

8 X 8

Crossbar

Input Mixer

IP Mixer 4

(I2C 0x44)

8 X 8

Crossbar

Input Mixer

IP Mixer 5

(I2C 0x45)

8 X 8

Crossbar

Input Mixer

IP Mixer 6

(I2C 0x46)

8 X 8

Crossbar

Input Mixer

IP Mixer 7

(I2C 0x47)

8 X 8

Crossbar

Input Mixer

IP Mixer 8

(I2C 0x48)

8 X 8

Crossbar

Input Mixer

SDIN1-L (L)

SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)
SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)

SDIN3-R (RBS

)

SDIN4-L (C)
SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)

SDIN4-R (LFE)

Bass &

Treble 1

(0xDA-

0xDD)

L to

PWM1

OP Mixer 1

(I2C 0xAA)

8X2 Output

Mixer

7 DAP1

(0x51-

0x57)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

Bass &

Treble 1

(0xDA-

0xDD)

R to

PWM2

OP Mixer 2

(I2C 0xAB)

8X2 Output

Mixer

7 DAP2

(0x58-

0x5E)

Loud-

ness

(0x91-

0x95)

DRC1

(0x96-

0x9C)

LS to

PWM3

OP Mixer 3

(I2C 0xAC)

8X2 Output

Mixer

RS to

PWM4

OP Mixer 4

(I2C 0xAD)

8X2 Output

Mixer

LBS to

PWM5

OP Mixer 5

(I2C 0xAE)

8X2 Output

Mixer

RBS to

PWM6

OP Mixer 6

(I2C 0xAF)

8X2 Output

Mixer

C to

PWM7

OP Mixer 7

(I2C 0xB0)

8X3 Output

Mixer

Bass &

Treble 4

(0xDA-

0xDD)

Sub to

PWM8

OP Mixer 8

(I2C 0xB1)

8X3 Output

Mixer

5 DAP8

(0x84-

0x88)

Loud-

ness

(0x91-

0x95)

DRC2

(0x9D-

0xA1)

DAP1

Volume

(0xD1)

Master Vol

(0xD9)

DAP2

Volume

(0xD2)

Master Vol

(0xD9)

DAP8

Volume

(0xD8)

Master Vol

(0xD9)

2 DAP8

(0x82-

0x83)

Max Vol

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Default input is BOLD

Figure 1-5. TAS5518 Architecture With I

C Registers (Fs = 176.4 kHz or Fs = 192 kHz)

Introduction

SLES115 -- August 2004

TAS5518

7 Biquads

in Series

Bass and

Treble

Loudness

DRC

Input Mixer

1 Other

Channel Output

From 7 Available

32-Bit
Trunc

PWM

Proc

Volume

A_to_ipmix

B_to_ipmix

SDIN1

C_to_ipmix

D_to_ipmix

SDIN2

E_to_ipmix

F_to_ipmix

SDIN3

G_to_ipmix

H_to_ipmix

SDIN4

Max

Volume

Left

Right

Channel

Volume

Master

Volume

Bass and Treble

Bypass

Bass and Treble

In-Line

Pre-

Volume

Post-

Volume

DRC

In-Line

DRC

Bypass

Output

Gain

Output Mixer Sums

Any Two Channels

PWM

Output

Figure 1-6. TAS5518 Detailed Channel Processing

1.5.2 I

C Coefficient Number Formats

The architecture of the TAS5518 is contained in ROM resources within the TAS5518 and cannot be altered.

However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I

C bus interface,

provide a user with the flexibility to set the TAS5518 to a configuration that achieves the system level goals.

The firmware is executed in a 48-bit signed fixed-point arithmetic machine. The most significant bit of the 48-bit

data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying

a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output product is then truncated

to a signed 48-bit number. Level offset operations are implemented by adding a 48-bit signed offset coefficient

to a 48-bit signed data value. In most cases, if the addition results in overflowing the 48-bit signed number

format, saturation logic is used. This means that if the summation results in a positive number that is greater

than 0x7FFF_FFFF_FFFF (the spaces are used to ease the reading of the hexadecimal number), the number

is set to 0x7FFF_FFFF_FFFF. If the summation results in a negative number that is less than

0x8000_0000_0000 0000, the number is set to 0x8000_0000_0000 0000.

Introduction

SLES115 -- August 2004

TAS5518

1.5.2.1

28-Bit 5.23 Number Format

All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23

numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point.

This is shown in the Figure 1-7.

-23

Bit

S_xxxx.xxxx_xxxx_xxxx_xxxx_xxx

-4

Bit

-1

Bit

Sign Bit

Bit

Figure 1-7. 5.23 Format

The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 1-8. If

the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct

number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must

be inverted, a 1 added to the result, and then the weighting shown in Figure 1-8 applied to obtain the

magnitude of the negative number.

(1 or 0) x 2

+ (1 or 0) x 2

+ ... + (1 or 0) x 2

+ (1 or 0) x 2

-1

+ ... + (1 or 0) x 2

-4

+ ... + (1 or 0) x 2

-23

Bit

-1

Bit

-4

Bit

-23

Bit

Figure 1-8. Conversion Weighting Factors--5.23 Format to Floating Point

Gain coefficients, entered via the I

C bus, must be entered as 32-bit binary numbers. The format of the 32-bit

number (4-byte or 8-digit hexadecimal number) is shown in Figure 1-9.

Coefficient

Digit 8

u u u

S x x x

Coefficient

Digit 7

x. x x x

Coefficient

Digit 6

x x x x

Coefficient

Digit 5

x x x x

Coefficient

Digit 4

x x x x

Coefficient

Digit 3

x x x x

Coefficient

Digit 2

x x x x

Coefficient

Digit 1

Fraction

Digit 5

Sign

Bit

Fraction

Digit 6

Fraction

Digit 4

Fraction

Digit 3

Fraction

Digit 2

Fraction

Digit 1

Integer

Digit 1

u = unused or don't care bits
Digit = hexadecimal digit

Figure 1-9. Alignment of 5.23 Coefficient in 32-Bit I

C Word

As Figure 1-9 shows, the hex value of the integer part of the gain coefficient cannot be concatenated with the

hex value of the fractional part of the gain coefficient to form the 32-bit I

C coefficient. The reason is that the

28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex

digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower

3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the

zero-valued most significant hex digit).

Introduction

SLES115 -- August 2004

TAS5518

Coefficient

Digit 16

u u u

u u u u

Coefficient

Digit 15

u u u u

Coefficient

Digit 14

u u u u

Coefficient

Digit 13

S x x x

Coefficient

Digit 12

x x x x

Coefficient

Digit 11

x x x x

Coefficient

Digit 10

x x x x

Coefficient

Digit 9

Word 1
(Most
Significant
Word)

Integer

Digit 3

Integer

Digit 4

(Bits 2

- 2

)

Integer

Digit 2

Integer

Digit 1

Sign

Bit

Coefficient

Digit 8

x x x

x x x x

Coefficient

Digit 7

x. x x x

Coefficient

Digit 6

x x x x

Coefficient

Digit 5

x x x x

Coefficient

Digit 4

x x x x

Coefficient

Digit 3

x x x x

Coefficient

Digit 2

x x x x

Coefficient

Digit 1

Word 2
(Least
Significant
Word)

Fraction

Digit 5

Integer

Digit 4

(Bit 2

)

Fraction

Digit 6

Fraction

Digit 4

Fraction

Digit 3

Fraction

Digit 2

Fraction

Digit 1

Integer

Digit 6

Integer

Digit 5

u = unused or don't care bits
Digit = hexadecimal digit

Figure 1-12. Alignment of 25.23 Coefficient in Two 32-Bit I

C Words

1.5.2.3

TAS5518 Audio Processing

The TAS5518 digital audio processing is designed such that noise produced by filter operations is maintained

below the smallest signal amplitude of interest, as shown in Figure 1-13. The TAS5518 achieves this by

increasing the precision of the signal representation substantially above the number of bits that are absolutely

necessary to represent the input signal.

Maximum Signal

Amplitude

Signal bits

output

Noise Floor as a

result of additional

precision

Ideal Input

Desired Output

Reduced

SNR signal

output

Noise Floor with no

additional precision

Possible Outputs

Filter

Operation

Signal bits

input

Overflow

Values retained by

overflow bits

Figure 1-13. TAS5518 Digital Audio Processing

Introduction

SLES115 -- August 2004

TAS5518

1.7

Biquad Filters

For 32-kHz to 96-kHz data, the TAS5518 provides 56 biquads across the eight channels (seven per channel)

For 176.4-kHz and 192-kHz data, the TAS5518 has 21 biquads across the three channels (seven per

channel). All of the biquad filters are second order direct form I structure.

The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the

biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number)

and a signed 28-bit coefficient (5.23 format number). The 76-bit ALU in the TAS5518 allows the 76-bit

resolution to be retained when summing the mixer outputs (filter products).

The five 28-bit coefficients for the each of the 56 biquads are programmable via the I

C interface. See

Table 1-3.

-1

Magnitude

Truncation

-1

Magnitude

Truncation

-1

Figure 1-15. Biquad Filter Structure

All five coefficients for one biquad filter structure are written to one I

C register containing 20 bytes (or five

32-bit words). The structure is the same for all biquads in the TAS5518. Registers 0x51 0x88 show all the

biquads in the TAS5518. Note that u(31:28) bits are unused and default to 0x0.

Table 1-3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)

DESCRIPTION

REGISTER FIELD CONTENTS

INITIALIZATION GAIN COEFFICIENT VALUE

DECIMAL

HEX

Coefficient

u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)

1.0

0x00, 0x80, 0x00, 0x00

Coefficient

u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)

0.0

0x00, 0x00, 0x00, 0x00

1.8

Bass and Treble Controls

From 32-kHz to 96-kHz data, the TAS5518 has four Bass and Treble tone controls. Each control has a ±18-dB

control range with selectable corner frequencies and 2nd order slopes. These controls operate four channel

groups:
·

L, R & C (Channels 1, 2, and 7)

LS, RS (Channels 3 and 4)

LBS, RBS (or alternately called L and R Lineout.) (Channels 5 and 6)

Sub (Channel 8)

Introduction

SLES115 -- August 2004

TAS5518

For 176.4 kHz and 192 kHz data, the TAS5518 has two Bass and Treble tone controls. Each control has a
±18-dB I

C control range with selectable corner frequencies and 2nd order slopes. These controls operate

two channel groups:

L & R

Sub

The bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment.

Table 1-4. Bass and Treble Filter Selections

(kHz)

3-dB CORNER FREQUENCIES

FILTER

SET 1

FILTER

SET 1

FILTER

SET 2

FILTER

SET 2

FILTER

SET 3

FILTER

SET 3

FILTER

SET 4

FILTER

SET 4

FILTER

SET 5

FILTER

SET 5

BASS

TREBLE

BASS

TREBLE

BASS

TREBLE

BASS

TREBLE

BASS

TREBLE

917

1833

125

3000

146

3667

167

4333

1088

2177

148

3562

173

4354

198

5146

44.1

1263

115

2527

172

4134

201

5053

230

5972

1375

125

2750

188

4500

219

5500

250

6500

88.2

115

2527

230

5053

345

8269

402

10106

459

11944

125

2750

250

5500

375

9000

438

11000

500

13000

176.4

230

5053

459

10106

689

16538

804

20213

919

23888

192

250

5500

500

11000

750

18000

875

22000

1000

26000

The I

C registers that control Bass and Treble are:

Bass and Treble By-Pass Register (0x89 0x90, channels 1-8)

Bass and Treble Slew Rates (0xD0)

Bass Filter Sets 1-5 (0xDA)

Bass Filter Index (0xDB)

Treble Filter Sets 1-5 (0xDC)

Treble Filter Index (0xDD)

1.9

Volume, Auto Mute, and Mute

The TAS5518 provides individual channel and master volume controls. Each control provides an adjustment

range of +18.0618 dB to 100 dB in 0.25 dB increments. This permits a total volume device control range of

+36 dB to 100 dB plus mute. The master volume control can be configured to control six or eight channels.

The TAS5518 has a master soft mute control that can be enabled by a terminal or I

C command. The device

also has individual channel soft mute controls that can are enabled via I

The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft

gain linear update with an I

C programmable linear step size at a fixed temporal rate. The linear soft gain step

size can be varied from 0.5 to 0.003906.

Table 1-5. Linear Gain Step Size

STEP SIZE (GAIN)

0.5

0.25

0.125

0.0625

0.03125

0.015625

0.007813

0.003906

Time to go from 36.124 db to -127 dB in ms

10.67

21.33

42.67

85.34

170.67

341.35

682.70

1365.4

Time to go from 18.062 db to -127 dB in ms

1.33

2.67

5.33

10.67

21.33

42.67

85.33

170.67

Time to go from 0 db to -127 dB in ms

0.17

0.33

0.67

1.33

2.67

5.33

10.67

21.33

Introduction

SLES115 -- August 2004

TAS5518

1.9.1 Auto Mute and Mute

The TAS5518 has individual channel automute controls that are enabled via the I

C interface. There are two

separate detectors used to trigger the automute:
·

Input Auto Mute: All channels are muted when all 8 inputs to the TAS5518 are less in magnitude than the

input threshold value for a programmable amount of time.

Output Auto Mute: A single channel is muted when the output of the DAP section is less in magnitude than

the input threshold value for a programmable amount of time.

The detection period and thresholds for these two detectors are the same.

This time interval is selectable via I

C to be from 1 ms. to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10,

20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default

value is mask programmable.

The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable

via I

C. The range of the input threshold adjustment is from below the LSB (bit position 0) to below bit position

12 in a 24 bit input data word (bit positions 8 to 20 in the DSPE). This provides an input threshold that can be

adjusted for 12 to 24 bits of data. The default value is mask programmable.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DVD Data Range

CD Data Range

Threshold Range

24-Bit Input

32-Bit in DSPE

Representation

Figure 1-16. Auto Mute Threshold

The auto mute state is exited when the TAS5518 receives one sample that is greater that the output threshold.

The output threshold can be one of two values:
·

Equal to the input threshold

6 dB (one bit position) greater than the input threshold

The value for the output threshold is selectable via I

C. The default value is mask programmable.

The system latency enables the data value that is above the threshold to be preserved and output.

A mute command initiated by automute, master mute, individual I

C mute, the AM interference mute

sequence, or the bank switch mute sequence overrides an unmute command or a volume command. While

a mute command is activated, the commanded channels transition to the mute state. When a channel is

unmuted, it goes to the last commanded volume setting that has been received for that channel.

1.10 Loudness Compensation

The loudness compensation function compensates for the Fletcher-Munson loudness curves. The TAS5518

loudness implementation tracks the volume control setting to provide spectral compensation for weak low or

high frequency response at low volume levels. For the volume tracking function both linear and log control laws

can be implemented. Any biquad filter response can be used to provide the desired loudness curve. The

control parameters for the loudness control are programmable via the I

C interface.

Introduction

SLES115 -- August 2004

TAS5518

The TAS5518 has a single set of loudness controls for the eight channels. In 6-channel mode loudness is

available to the six speaker outputs and also the line outputs. The loudness control input uses the Maximum

individual master volume (V) to control the loudness that is applied to all channels. In 192-kHz and 176.4-kHz

modes, the loudness function is active only for channels 1, 2, and 8.

Audio In

Audio Out

Loudness Function = f (V)

Loudness

Biquad

H(Z)

Figure 1-17. Loudness Compensation Functional Block Diagram

Loudness Function = f (V) = G x [2

[(Log V) x LG + LO]

] + O or alternatively,

Loudness Function = f (V) = G x [V

x 2

] + O

For example, for the default values LG = -0.5, LO = 0.0, G = 1.0, and O = 0.0 then:

Loudness Function = 1 / SQRT (V) which is the recommended transfer function for loudness. So,

Audio Out = (Audio In) x V + H (Z) x SQRT (V). Other transfer functions are possible.

Table 1-6. Default Loudness Compensation Parameters

LOUDNESS

DESCRIPTION

USAGE

DATA

SUB ADD

DEFAULT

LOUDNESS

TERM

DESCRIPTION

USAGE

DATA

FORMAT

SUB-ADD

RESS

HEX

FLOAT

Max volume

Gains audio

5.23

Log V

Log

(max volume)

Loudness function

5.23

00000000

0.0

H (Z)

Loudness biquad

Controls shape of

Loudness curves

5.23

0x95

b0 = 0000D513

b1 = 00000000

b2 = 0FFF2AED

a1 = 00FE5045

a2 = 0F81AA27

b0 = 0.006503

b1 = 0

b2 = -0.006503

a1 = 1.986825

a2 = -0.986995

Gain (log space)

Loudness function

5.23

0x91

FFC00000

-0.5

Offset (log space)

Loudness function

25.23

0x92

00000000

Gain

Switch to enable

Loudness (ON = 1,

OFF = 0)

5.23

0x93

00000000

Offset

Provides offset

25.23

0x94

00000000

Introduction

SLES115 -- August 2004

TAS5518

1.11 Dynamic Range Control (DRC)

The DRC provides both compression and expansion capabilities over three separate and definable regions

of audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each

of the three regions a distinct compression or expansion transfer function can be established and the slope

of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two

boundaries defining the three regions can also be set by programmable offset coefficients. The DRC

implements the composite transfer function by computing a 5.23 format gain coefficient from each sample

output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input is

the audio data stream. The mixer output is the DRC-adjusted audio data.

There are two distinct DRC blocks in the TAS5518. DRC1 services channels 1-7 in the 8-channel mode and

channels 1-4, and 7 in the 6-channel mode. This DRC computes rms estimates of the audio data streams on

all channels that it controls. The estimates are then compared on a sample-by-sample basis and the larger

of the estimates is used to compute the compression/expansion gain coefficient. The gain coefficient is then

applied to appropriate channels audio stream. DRC2 services only channel 8. This DRC also computes an

rms estimate of the signal level on channel 8 and this estimate is used to compute the compression/expansion

gain coefficient applied to the channel 8 audio stream.

All of the TAS5518 default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 1-8

shows the recommended time constants and their HEX values. If the user wants to implement other DRC

functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available

from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It will

then output the TAS5518 hex coefficients for download to the TAS5518.

Table 1-8. DRC Recommended Changes From TAS5518 Defaults

SUBADDRESS

REGISTER FIELDS

RECOMMENDED TIME

CONSTANT (MS)

RECOMMENDED

HEX VALUE

DEFAULT HEX

0x98

DRC1 energy

0000883F

DRC1 (1 energy)

007F77C0

0x9C

DRC1 attack

0000883F

DRC1 (1 attack)

007F77C0

DRC1 decay

0001538F

000000AE

DRC1 (1 decay)

007EAC70

007FFF51

0x9D

DRC2 energy

0000883F

DRC2 (1 energy)

007F77C0

0xA1

DRC2 attack

0000883F

DRC2 (1 attack)

007F77C0

DRC2 decay

0001538F

000000AE

DRC2 (1 decay)

007EAC70

007FFF51

Recommended DRC set-up flow if the defaults are used:

After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 decay). See

Table 1-8.

Enable either the pre-volume or post-volume DRC

Recommended DRC set-up flow if the DRC design uses values different from the defaults:

After power up, load all DRC coefficients per the DRC design.

Enable either the pre-volume or post-volume DRC

Figure 1-19 shows the positioning of the DRC block in the TAS5518 processing flow. As seen, the DRC input

can come from either before or after soft volume control and loudness processing.

Introduction

SLES115 -- August 2004

TAS5518

7 Biquads

in Series

Bass and

Treble

Bass & Treble

By-Pass

Bass & Treble

In-Line

Loudness

DRC

In-Line

DRC

By-Pass

From Input Mixer

Max

Volume

Pre-

Volume

Post-

Volume

Channel

Volume

Master

Volume

To Output

Mixer

Figure 1-19. DRC Positioning in TAS5518 Processing Flow

Figure 1-20 illustrates a typical DRC transfer function.

DRC Input Level

DRC

-
Compensated Output

1:1 Transfer Function

Implemented Transfer Fucntion

Region

Figure 1-20. Dynamic Range Compression (DRC) Transfer Function Structure

The three regions shown in Figure 1-20 are defined by three sets of programmable coefficients:
·

Thresholds T1 and T2--define region boundaries.

Offsets O1 and O2--define the DRC gain coefficient settings at thresholds T1 and T2 respectively.

Slopes k0, k1, and k2--define whether compression or expansion is to be performed within a given region.

The magnitudes of the slopes define the degree of compression or expansion to be performed.

The three sets of parameters are all defined in logarithmic space and adhere to the following rules:
·

The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value then

have negative values in logarithmic (dB) space.

The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word format

used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial data

received at the serial audio receive port by adding 8 bits of headroom above the 32-bit word and 8 bits

of computational precision below the 32-bit word. If the audio processing steps between the SAP input

and the DRC input result in no accumulative boost or cut, the DRC would operate on the 8 bits of headroom

and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value) audio sample

(0x7FFFFFFF) is seen at the DRC input as a 48-dB sample (8 bits x -6.02 dB/bit = -48 dB).

Introduction

SLES115 -- August 2004

TAS5518

Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to the

rms value of the data into the DRC. Zero valued threshold settings reference the maximum valued rms

input into the DRC and negative valued thresholds reference all other rms input levels. Positive valued

thresholds have no physical meaning and are not allowed. In addition, zero valued threshold settings are

not allowed.

Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of the

DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space. This

means that the threshold settings must be programmed as 48-bit (25.23 format) numbers.

CAUTION: Zero valued and positive valued threshold settings are not allowed and

cause unpredictable behavior if used.

Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain

coefficient at the threshold points T1 and T2 respectively. Positive offsets are defined as cuts, and thus

boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format)

numbers.

Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given region,

and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format)

numbers.

1.11.1 DRC Implementation

The three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient

computation engine, and (3) an attack/decay controller.
·

RMS estimator--This DRC element derives an estimate of the rms value of the audio data stream into

the DRC. For the DRC block shared by CH1 and CH2, two estimates are computed--an estimate of the

CH1 audio data stream into the DRC, and an estimate of the CH2 audio data stream into the DRC. The

outputs of the two estimators are then compared, sample-by-sample, and the larger valued sample is

forwarded to the compression/expansion coefficient computation engine.
Two programmable parameters, ae and (1 ae), set the effective time window over which the rms estimate

is made. For the DRC block shared by CH1 and CH2, the programmable parameters apply to both rms

estimators. The time window over which the rms estimation is computed can be determined by:

twindow +

* 1

FS n(1 * ae)

Compression/expansion coefficient computation--This DRC element converts the output of the rms

estimator to a logarithmic number, determines the region that the input resides, and then computes and

outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters--T1,

T2, O1, O2, k0, k1, and k2--define the three compression/expansion regions implemented by this

element.

Attack/decay control--This DRC element controls the transition time of changes in the coefficient

computed in the compression/expansion coefficient computation element. Four programmable

parameters define the operation of this element. Parameters ad and 1 - ad set the decay or release time

constant to be used for volume boost (expansion). Parameters aa and 1 - aa set the attack time constant

to be used for volume cuts. The transition time constants can be determined by:

ta +

* 1

FS n(1 * aa)

td +

* 1

FS n(1 * ad)

1.11.2

Compression/Expansion Coefficient Computation Engine Parameters

There are seven programmable parameters assigned to each DRC block: two threshold parameters - T1 and

T2, two offset parameters - O1 and O2, and three slope parameters - k0, k1, and k2. The threshold parameters

establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing

known gain settings at the threshold levels, and the slope parameters define whether a given region is a

compression or an expansion region.

Introduction

SLES115 -- August 2004

TAS5518

The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers. These

mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the audio data in

the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input and the DRC. The

selection of threshold values must take the gain (attenuation) of these mixers into account. The DRC

implementation examples that follow illustrate the effect these mixers have on establishing the threshold

settings.

T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes the

boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic

space, and which region is active for any given rms estimator output sample is determined by the logarithmic

value of the sample.

Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB)

or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the

value of the derived gain coefficient is 1.0 (0x00, 80, 00, 00 in 5.23 format). k2 is the slope of the DRC transfer

function for rms input levels above T2 and k1 is the slope of the DRC transfer function for rms input levels below

T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that there cannot be a discontinuity

in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the

transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term

O1 must obey the following equation.

O1No Discontinuity + |T1 * T2| k1 ) O2 For ( |T1| w |T2| )

T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the

user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is realized.

Going down in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this input

level, the offset of the transfer function curve from the 1:1 transfer curve does not equal O1, there is a

discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no

discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at the input level

T1 is offset from the 1:1 transfer curve by the value O1. The examples that follow illustrate both continuous

and discontinuous transfer curves at T1.

Going down in volume from T1, starting at the offset level O1, the slope k0 defines the compression/expansion

activity in the lower region of the DRC transfer curve.

1.11.2.1 Threshold Parameter Computation

For thresholds,

= -6.0206T

INPUT

= -6.0206T

SUB_ADDRESS_ENTRY

If, for example, it is desired to set T1 = -64 dB, then the subaddressaddress entry required to set T1 to -64 dB

is:

T1SUB_ADDRESS_ENTRY +

*64

*6.0206 +

10.63

T1 is entered as a 48-bit number in 25.23 format. Therefore:

T1 = 10.63 = 0_1010.1010_0001_0100_0111_1010_111

= 0x00000550A3D7 in 25.23 format

Introduction

SLES115 -- August 2004

TAS5518

1.11.2.2 Offset Parameter Computation

The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An

equivalent statement is that offsets represent the departure of the actual transfer function from a 1:1 transfer

at the threshold point. Offsets are 25.23 formatted 48-bit logarithmic numbers. They are computed by the

following equation.

OINPUT +

ODESIRED ) 24.0824 dB

6.0206

Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive

numbers. For example, to achieve a boost of 21 dB at threshold T1, the I

C coefficient value entered for O1

must be:

O1INPUT +

21 dB ) 24.0824 dB

6.0206

+ 0.51197555

+ 0.1000_0011_0001_1101_0100
+ 0x00000041886A in 25.23 format

More examples of offset computations are included in the following examples.

1.11.2.3 Slope Parameter Computation

In developing the equations used to determine the subaddress of the input value required to realize a given

compression or expansion within a given region of the DRC, the following convention is adopted.

DRC Transfer = Input Increase : Output Increase

If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC,

a 1:n expansion is being performed. If the DRC realizes a 1 dB increase in output level for every n dB increase

in the rms value of the audio into the DRC, a n:1 compression is being performed.
For 1:n expansion, the slope k can be found by:

k = n - 1

For n:1 compression, the slope k can be found by: k + 1n1
In both expansion (1:n) and compression (n:1), n is implied to be greater than 1. Thus, for expansion:

k = n -1 means k > 0 for n > 1. Likewise, for compression, k + 1n1 means -1 < k < 0 for n > 1. Thus, it appears

that k must always lie in the range k > -1.
The DRC imposes no such restriction and k can be programmed to values as negative as -15.999. To

determine what results when such values of k are entered, it is first helpful to note that the compression and

expansion equations for k are actually the same equation. For example, a 1:2 expansion is also a 0.5:1

compression.

0.5 Compression å k + 1

0.5

1 + 1

1 : 2 Expansion å k + 21 + 1

As can be seen, the same value for k is obtained either way. The ability to choose values of k less than -1 allows

the DRC to implement negative slope transfer curves within a given region. Negative slope transfer curves

are usually not associated with compression and expansion operations, but the definition of these operations

can be expanded to include negative slope transfer functions. For example, if k = -4

Compression Equation : k + *4 + 1n *1 å n +

3 å *

0.3333 : 1 compression

Expansion Equation : k + *4 + n1 å n + 3 å 1 : *3 expansion

With k = -4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the DRC.

As the input increases in volume, the output decreases in volume.

Introduction

SLES115 -- August 2004

TAS5518

1.12 Output Mixer

The TAS5518 provides an 8x2 output mixer for channels 1, 2, 3, 4, 5, and 6. For channels 7 and 8 the TAS5518

provides an 8x3 output mixer. These mixers allow each output to be any ratio of any two (three) signal

processed channels. The control parameters for the output crossbar mixer are programmable via the I

interface.

Output

Gain Coefficient

Select

Output

Gain Coefficient

Output

Gain Coefficient

1, 2, 3, 4, 7 or 8

5 or 6

Select

Output

Select

Output

Select

Output

Select

Output

Figure 1-21. Output Mixers

1.13 PWM

The TAS5518 has eight channels of high performance digital PWM Modulators that are designed to drive

switching output stages (backends) in both single-ended (SE) and H-bridge (bridge tied load) configuration.

The TAS5518 device uses noise-shaping and sophisticated error correction algorithms to achieve high power

efficiency and high-performance digital audio reproduction. The TAS5518 uses an AD1 PWM modulation

combined with a 5

order noise shaper to provide a 110-dB SNR from 20 to 20 kHz.

The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels

configurable as either:
·

Six channels to drive power stages + two channels to drive a differential input active filter to provide a

separately controllable stereo line out

Eight channels to drive power stages

The TAS5518 PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the

TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone will not

operate while the six or eight backend drive channels are operating. The headphone will be enabled via a

headphone select terminal or I

C command.

The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled and

disabled.
The PWM section also contains the power supply volume control (PSVC) PWM.

Introduction

SLES115 -- August 2004

TAS5518

The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
·

Up to 8x over sampling.
-

8x at F

= 44.1 kHz, 48 kHz, 32 kHz, 38 kHz

4x at F

= 88.2 kHz, 96 kHz

2x at F

= 176.4 kHz, 192 kHz

order noise shaping

110-dB dynamic range 0 20 kHz (TAS5518 + TAS5182 system measured at speaker terminals)

THD < 0.01%

Adjustable maximum modulation limit of 93.8% to 99.2%

3.3-V digital signal

1.13.1

DC Blocking (High Pass Enable/ Disable)

Each input channel incorporates a first order digital high-pass filter to block potential dc components. The filter

3 dB point is approximately 0.89-Hz at 44.1-kHz sampling rate. The high-pass filter can be enabled and

disabled via the I

C interface.

1.13.2

De-Emphasis Filter

For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to

support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 1-22 shows a graph of the de-emphasis

filtering characteristics. De-emphasis is set using two bits in the system control register.

Response

-
dB

-10

Frequency - kHz

3.18 (50 µs)

10.6 (15 µs)

Figure 1-22. De-emphasis Filter Characteristics

1.13.3

Power Supply Volume Control (PSVC)

The TAS5518 supports volume control by both conventional digital gain / attenuation and by a combination

of digital and analog gain / attenuation. Varying the H-bridge power supply voltage performs the analog volume

control function. The benefits of using powers supply volume control (PSVC) are reduced idle channel noise,

improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions

at reduced power levels. The power supply volume control (PSVC) is enabled via I

C. When enabled the

PSCV provides a PWM output that is filtered to provide a reference voltage for the power supply. The power

supply adjustment range can be set for -12.04, -18.06, or -24.08 dB, to accommodate a range of variable

power supply designs.

Figure 1-23 and Figure 1-24 show how power supply and digital gains can be used together.

The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match

the PSVC volume transfer function.

TAS5518 Controls and Status

SLES115 -- August 2004

TAS5518

TAS5518 Controls and Status

The TAS5518 provides control and status information from both the I

C registers and device pins.

This section describes some of these controls and status functions. The I

C summary and detailed register

descriptions are contained in sections at the end of this document.

2.1

C Status Registers

The TAS5518 has two status registers that provide general device information. These are the General Status

2.1.1 General Status Register (0x01)

Device identification code

Clip indicator The TAS5518 has a clipping indicator. Writing to the register clears the indicator.

Bank switching is busy

2.1.2 Error Status Register (0x02)

No internal errors (the valid signal is high)

A clock error has occurred These are sticky bits that are cleared by writing to the register.
-

LRCLK error When the number of MCLKs per LRCLK is incorrect

SCLK error When the number of SCLKS per LRCLK is incorrect

Frame slip When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles

PLL phase-lock error

This error status register is normally used for system development only.

2.2

TAS5518 Pin Controls

The TAS5518 provide a number of terminal controls to manage the device operation. These controls are:
·

RESET

PDN

BKND_ERR

HP_SEL

MUTE

2.2.1 Reset (RESET)

The TAS5518 is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry

when power is applied.

RESET is an asynchronous control signal that restores the TAS5518 to the hard mute state (M). Master

volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without

an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all

C and serial data bus operations are ignored.

Table 2-1 shows the device output signals while RESET is active.

Table 2-1. Device Outputs During Reset

SIGNAL

SIGNAL STATE

Valid

Low

PWM P-outputs

Low (M-State)

PWM M-outputs

Low (M-State)

SDA

Signal Input (not driven)

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Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading

edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational

state is performed using a quiet start up sequence to minimize noise. This control uses the PWM reset and

unmute sequence to shut down and start up the PWM. A detailed description of these sequences is contained

in the PWM section. If a completely quiet reset or power down sequence is desired, MUTE should be applied

before applying RESET.

The rising edge of the reset pulse begins device initialization before the transition to the operational mode.

During device initialization, all controls are reset to their initial states. Table 2-2 shows the default control

settings following a reset.

Table 2-2. Values Set During Reset

CONTROL

SETTING

Clock register

Not valid

High pass

Disabled

Unmute from clock error

Hard unmute

PSVC high Z

Disabled

Post DAP detection automute

Enabled

Eight Ch PreDAP detection automute

Enabled

De-emphasis

De-emphasis disabled

Channel configuration control

Configured for the default setting

Headphone configuration control

Configured for the default setting

Serial data interface format

S 24 bit

Individual channel mute

No channels are muted

Automute delay

5 ms

Automute threshold 1

< 8 bits

Automute threshold 2

Same as automute threshold 1

Modulation limit

Maximum modulation limit of 97.7%

Six (or eight low) channel configuration

Eight channels

Slew rate limit

Disengaged for all channels

Interchannel delay

-32, 0, 16, 16, 24, 8, 8, -24

Shutdown PWM on error

Enabled

Volume and mute update rate

Volume ramp 85 ms

Treble and bass slew rate

Update every 1.31 ms

Bank switching

Manual bank selection is enabled

Auto bank switching map

All channels use Bank 1

Biquad coefficients (5508)

Set to All pass

Input mixer coefficients

Input N -> Channel N, no attenuation

Output mixer coefficients

Channel N -> Output N, no attenuation

Subwoofer sum into Ch1 and 2 (5508)

Gain of 0

Ch1 and 2 sum in subwoofer (5508)

Gain of 0

Bass and treble bypass

Gain of 1

Bass and treble Inline

Gain of 0

DRC bypass (5508)

Gain of 1

DRC inline (5508)

Gain of 0

DRC (5508)

DRC disabled, default values

Master volume

Mute

Individual channel volumes

0 dB

All bass and treble Indexes

0x12 neutral

Treble filter sets

Filter Set 3

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CONTROL

SETTING

Bass filter sets

Filter Set 3

Loudness (5508)

Loudness disabled, default values

AM interference enable

Disabled

AM interference IF

455

AM interference select sequence

Tuned freq and mode

0000 , BCD

Subwoofer PSVC control

Enabled

PSVC and PSVC range

Disabled / 0 dB

After the initialization time, the TAS5518 starts the transition to the operational state with the Master volume

set at mute.
Since the TAS5518 has an external crystal time base, following the release of RESET, the TAS5518 sets the

MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state until

the master volume is set to a value other than mute via I

2.2.2 Power Down (PDN)

TheTAS5518 can be placed into the power down mode by holding the PDN terminal low. When power down

mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation

(there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition

to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power down state. To

initiate the power-up sequence requires MCLK to be operational and the TAS5518 to receive 5 MCLKs prior

to the release of PDN.
As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard

mute (M) state. During power down, all I

C and serial data bus operations are ignored. Table 2-3 shows the

device output signals while PDN is active.

Table 2-3. Device Outputs During Power Down

SIGNAL

SIGNAL STATE

Valid

Low

PWM P-outputs

M-state = low

PWM M-outputs

M-state = low

SDA

Signal input

PSVC

M-state = low

Following the application of PDN, the TAS5518 does not perform a quiet shutdown to prevent clicks and pops

produced during the application (the leading edge) of this command. The application of PDN immediately

performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the

C register settings.

The crystal time base allows the TAS5518 to determine the CLK rates. Once these rates are determined, the

TAS5518 unmutes the audio.

2.2.3 Backend Error (BKND_ERR)

Backend error is used to provide error management for backend error conditions. Backend error is a level

sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5

MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM

backend error state. This state is described in the PWM section. Once the backend error sequence is initiated,

a delay of 5 ms is performed before the system starts the output re-initialization sequence. After the

initialization time, the TAS5518 begins normal operation. Backend error does not affect other PWM modulator

operations

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The number of channels that are affected by the BKND_ERR signal is dependent upon the 6-channel

configuration signal. If the I

C setting 6-channel configuration is false, the TAS5518 places all eight PWM

outputs in the PWM backend error state, while not affecting any other internal settings or operations. If the

C setting six configuration is true, the TAS5518 brings the PWM outputs 1-6 to a backend error state, while

not affecting any other internal settings or operations. Table 2-4 shows the device output signal states during

backend error.

Table 2-4. Device Outputs During Backend Error

SIGNAL

SIGNAL STATE

Valid

Low

PWM P-outputs

M-State - low

PWM M-outputs

M-State - low

HPPWM P-outputs

M-State - low

HPPWM M-outputs

M-State - low

SDA

Signal Input (not driven)

2.2.4 Speaker / Headphone Selector (HP_SEL)

The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives

the processed data output from DAP and PWM channels 1 and 2.

In 6-channel configuration this feature does not affect the two lineout channels.

When low, the headphone output is enabled. In this mode the speaker outputs are disabled. When high, the

speaker outputs are enabled and the headphone is disabled.

Changes in the pin logic level results in a state change sequence using soft mute to the hard mute (M) state

for both speaker and headphone followed by a soft unmute.

When HP_SEL is low, the configuration of channels 1 and 2 are defined by the headphone configuration

channels 1 and 2.

2.2.5 Mute (MUTE)

The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp

to previous volume. The TAS55508 has both a master and individual channel mute commands. A terminal

is also provided for the master MUTE. The low active master Mute I

C register and the MUTE terminal are

logically Or'ed together. If either is set to low, a mute on all channels is performed. The master mute command

operates on all channels regardless on whether the system is in six or eight channel configuration.

When MUTE is invoked, the PWM output stops switching and then goes to an idle state.

The master Mute terminal is used to support a variety of other operations in the TAS5518, such as setting the

inter-channel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command

by the master mute terminal, individual I

C mute, the AM interference mute sequence, the bank switch mute

sequence, or automute overrides an unmute command or a volume command. While a mute is active, the

commanded channels will be placed in a mute state. When a channel is unmuted, it goes to the last

commanded volume setting that has been received for that channel.

2.3

Device Configuration Controls

The TAS5518 provides a number of system configuration controls that are set at initialization and following

a reset.
·

Channel Configuration

Headphone Configuration

Audio System Configurations

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Recovery from Clock Error

Power Supply Volume Control Enable

Volume and Mute Update Rate

Modulation Index Limit

Inter-channel Delay

Master Clock and Data Rate Controls

Bank Controls

2.3.1 Channel Configuration Registers

In order for the TAS5518 to have full control of the power stages, registers 0x05 to 0x0C must be programmed

to reflect the proper power stage and how each one should be controlled. Channel configuration registers

consist of eight registers, one for each channel.

The primary reason for using these registers is that different power stages require different handling during

start up, mute/unmute, shutdown, and error recovery. The TAS5518 must select the sequence that gives the

best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.

This sequence depends on which power stage is present at the TAS5518 output.

Table 2-5. Description of the Channel Configuration Registers (0x05 to 0x0C)

BIT

DESCRIPTION

Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is

to follow the error recovery sequence or to continue with no interruption.

Determines if the power stage needs the TAS5518 VALID pin to go low to reset the power stage. Some power stages can be reset

by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power

stages. This provides better control of each power stage.

Determines if the power stage needs the TAS5518 VALID pin to go low to mute the power stage. Some power stages can be muted

by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power

stages. This provides better control of each power stage.

Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5518 PWM

pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.

The power stage TAS5182 has a special PWM input. To ensure that the TAS5518 has full control in all occasions, the PWM output

must be remapped.

Can be used to handle click and pop for some applications.

This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of

both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.

Not used

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Table 2-6 lists the optimal setting for each output stage configuration. Note that the default value is applicable

in all configurations except the TAS5182 SE/BTL configuration.

Table 2-6. Recommended TAS5518 Configurations for Texas Instruments Power Stages

DEVICE

ERROR RECOVERY

CONFIGURATION

Default

RES

BTL

RES

BTL

TAS5111

RES

TAS5111

AUT

BTL

AUT

RES

BTL

TAS5112

RES

TAS5112

AUT

BTL

AUT

TAS5182

RES

BTL

TAS5182

RES

RES: The output stage requires VALID to go low to recover from a shutdown.

AUT: The power stage can auto recover from a shutdown.

BTL: Bridge tied load configuration

SE: Single-ended configuration

2.3.2 Headphone Configuration Registers

The headphone configuration controls are identical to the speaker configuration controls. The headphone

configuration control settings are used in place of the speaker configuration control settings for channels 1

and 2 when the headphones are selected. In reality however, there is only one used configuration setting for

headphones and that is the default setting.

2.3.3 Audio System Configurations

The TAS5518 can be configured to comply with various audio systems: 5.1-channel system, 6-channel

system, 7.1-channel system and 8-channel system.

The audio system configuration is set in the General Control Register (0xE0). Bits D31 D4 must be zero and

D0 is don't care.

Determines if SUB is to be controlled by PSVC (D3 is a write-only bit)

Enable/Disable power supply volume control

Sets number of speakers in the system, including possible line outputs

D3-D1 must be configured as the following according to the audio system in the application:

Table 2-7. Audio System Configuration (General Control Register 0xE0)

AUDIO SYSTEM

D31-D4

DEFAULT

6 channel or 5.1 NOT using PSVC

6 channel using PSVC

5.1 system using PSVC

8 channel or 7.1 NOT using PSVC

8 channel using PSVC

7.1 system using PSVC

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2.3.3.1

Using Line Outputs in 6-Channel Configurations

The audio system can be configured for a 6-channel configuration (with 2 line outs) by writing a 1 to bit D1

of register 0xE0 (General Control Register). In this configuration, channel 5 and 6 processing are exactly the

same as the other channels, except that Master Volume has no effect.

Note that in 6-channel configuration, channels 5 and 6 are unaffected by backend error (BKND_ERR goes

low).

To use channels 5 and 6 as dry unprocessed line outs, the following setup should be done:
·

Channel 5 volume and channel 6 volume should be set for a constant output such as 0 dB.

Bass and Treble for channels 5 and 6 can be used if desired.

DRC1 should be by-passed for channels 5 and 6.

If enabled, the loudness function shapes the response of channels 5 and 6. However, the amplitude of

5 and 6 are not used in determining the loudness response.

If a down mix is desired on the channel 5 and 6 as line out, the down mixing can be performed using the

channel 5 and channel 6 input mixers.

The operation of the channel 5 and 6 biquads is unaffected by the 6/8 channel configuration setting.

2.3.4 Recovery from Clock Error

The TAS5518 can be set to either perform a volume ramp up during the recovery sequence of a clock error

or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature

is enabled via I

C system control register 0x03.

2.3.5 Power Supply Volume Control Enable

The power supply volume control (PSVC) can be enabled and disabled via I

C register 0xE0. The subwoofer

PWM output can configured to be controlled by the PSVC or digitally attenuated when PSVC is enabled (for

powered subwoofer configurations). Note that PSVC cannot be simultaneously enabled along with unmute

outputs after clock error feature.

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2.3.6 Volume and Mute Update Rate

The TAS5518 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute

ramp rates are adjustable by programming the I

C register 0xD0 for the appropriate number of steps to be

512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
·

In normal speed, the update rate is 1 step every 4 / Fs seconds.

In double speed, the update is 1 step every 8 / Fs seconds.

In quad speed, the update is 1 step every 16 / Fs seconds.

Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However,

the variance of the total time to go from +18 dB to mute is less than 25%.

Table 2-8. Volume Ramp Rates in ms

NUMBER OF STEPS

SAMPLE RATE (KHZ)

NUMBER OF STEPS

44.1, 88.2, 176.4

32, 48, 96, 192

512

46.44 ms

42.67 ms

1024

92.88 ms

85.33 ms

2048

185.76 ms

170.67 ms

2.3.7 Modulation Index Limit

PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is

50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For

negative signals, the PWM modulations fall below 50% towards 0%.

However, there is a limit to the maximum modulation possible. During the off-time period, the power stage

connected to the TAS5518 output needs to get ready for he next on-time period. The maximum possible

modulation is then set by the power stage requirements. All Texas Instruments power stages needs maximum

modulation to be 97.7%. This is also the default setting of the TAS5518. Default settings can be changed in

the Modulation Index Register (0x16).

Note that no change should be made to this register when using Texas Instruments power stages.

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2.3.8 Inter-channel Delay

An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per

channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.

The default values are shown in Table 2-9.

Table 2-9. Inter-Channel Delay Default Values

C SUB-ADDRESS

CHANNEL

INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)

0x1B

-24

0x1C

0x1D

-16

0x1E

+16

0x1F

-24

0x20

0x21

-8

0x22

+24

This delay is generated in the PWM and can be changed at any time through the serial control interface I

registers 0x1B 0x22. The absolute offset for channel 1 is set in I

C sub-address 0x23.

NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a

pure path digital amplifier system. The setting is based upon the type of backend power device

that is used and the layout. These values are set during initialization using the I

C serial

interface. Unless otherwise noted, use the default values given in Table 2-9.

2.4

Master Clock and Serial Data Rate Controls

The TAS5518 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right

clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal

allows the TAS5518 to automatically detect MCLK and the data rate.

The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.

The TAS5518 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.

However, there is no constraint as to the phase relationship of these signals. The TAS5518 accepts a 64 x

Fs SCLK rate and a 1 x Fs LRCLK.

If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5518 performs

a clock error and resynchronize the clock timing.

The clock and serial data interface have several control parameters:

MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) - I

C parameter

Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz - I

C parameter

AM Mode Enable / Disable - I

C parameter

During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:

Tuned AM Frequency (for AM interference avoidance) (550 - 1750 kHz) - I

C parameter

Frequency Set Select (1-4) - I

C parameter

Sample Rate - I

C parameter or auto detected

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2.4.1 PLL Operation

The TAS5518 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL

(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital

PLL provides the reference clock for the digital audio processor and the control logic.

The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal

provides the input reference clock for the digital PLL. The crystal provides a time base to support a number

of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal

time base provides a constant rate for all controls and signal timing.

Even if MCLK is not present, the TAS5518 can receive and store I

C commands and provide status.

2.5

Bank Controls

The TAS5518 permits the user to specify and assign sample rate dependent parameters for Biquad,

Loudness, DRC, and Tone in one of three banks that can be manually selected or selected automatically

based upon the data sample rate. Each bank can be enabled for one or more specific sample rates via I

bank control register 0x40. Each bank set holds the following values:
·

Coefficients for Seven Biquads (7X5 = 35 coefficients) for Each of the Eight Channels (Registers 0X51

0x88)

Coefficients for One Loudness Biquad (Register 0x95)

DRC1 Energy and (1 Energy) Values (Register 0x98)

DRC1 Attack, (1 - Attack), Decay, (1 Decay) Values (Register 0x9C)

DRC2 Energy and (1 Energy) Values (Register 0x9D)

DRC2 Attack, (1 - Attack), Decay, (1 Decay) Values (Register 0xA1)

Five Bass Filter-Set Selections (Register 0xDA)

Five Treble Filter-Set Selections (Register 0xDC)

The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,

Bank 2 and Bank 3 must be programmed on power-up since the default values are all zeroes. If bank switching

is used and Bank 2 and Bank 3 are not programmed correctly, then the output of the TAS5518 could be muted

when switching to those banks.

2.5.1 Manual Bank Selection

The three bank selection bits of the bank control register allow the appropriate bank to be manually selected

(000 = Bank 1, 001 = Bank 2, 010 = Bank 3). In the manual mode, when a write occurs to the Biquad, DRC,

or Loudness coefficients, the current selected bank is updated. If audio data is streaming to the TAS5518,

during a manual bank selection, the TAS5518 first performs a mute sequence, then performs the bank switch,

and finally restores the volume using an un-mute sequence.

A mute command initiated by the bank switch mute sequence overrides an un-mute command or a volume

command. While a mute is active, the commanded channels are muted. When a channel is unmated, the

volume level goes to the last commanded volume setting that has been received for that channel.

If MCLK or SCLK is stopped, the TAS5518 performs a bank switch operation. If the clocks should start up once

the manual bank switch command has been received, the bank switch operation is performed during the 5-ms

silent start sequence.

2.5.2 Automatic Bank Selection

To enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control

rate selection registers. The automatic base selection is performed when a frequency change is detected

according to the following scheme:

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1. The system scans Bank 1 data rate associations to see if the Bank 1 is assigned for that data rate.
2. If Bank 1 is assigned, then the Bank 1 coefficients will be loaded.
3. If it is not then, the system scans the bank 2 to see if Bank 1 is assigned for that data rate.
4. If Bank 2 is assigned, then the Bank 2 coefficients will be loaded.
5. If it is not then, the system loads the Bank 3 coefficients.

The default is that all frequencies are enabled for Bank 1. This default is expressed as a value of all 1s in the

Bank 1 auto-selection byte and all 0s in the bank 2 auto-section byte.

2.5.2.1

Coefficients Write Operations While Automatic Bank Switch Is Enabled

In automatic mode if a write occurs to the Tone, EQ, DRC, or Loudness coefficients, the bank that is written

to is the current bank.

2.5.3 Bank Set

Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic

switching modes without causing a bank switch to occur. Bank set mode does not alter the current bank

from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic

mode this prevents a clock error or data rate change from corrupting a bank coefficient write.

To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank

control register. This enables the Tone, EQ, DRC, and Loudness coefficient values of bank 1, 2, or 3 to be

respectively updated.

Once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired

manual or automatic bank selection mode.

2.5.4 Bank Switch Timeline

After a bank switch is initiated (manual or automatic), no I

C writes to the TAS5518 should occur before a

minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.

2.5.5 Bank Switching Example 1

Problem: The audio unit containing a TAS5518 needs to handle different audio formats with different sample

rates. Format #1 requires Fs = 32 kHz, Format #2 requires Fs = 44.1 kHz, and Format #3 requires Fs = 48

kHz. The sample-rate dependent parameters in the TAS5518 require different coefficients and data

depending on the sample rate.

Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks

associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3).

One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
·

Generate bank-related coefficients (see above) for sample rates 32 kHz, 44.1 kHz, and 48 kHz and include

the same in the micro-based TAS5518 I

C firmware.

On TAS5518 power up or reset, the micro runs the following TAS5518 Initialization code:
-

Update Bank 1 (Write 0x00048040 to register 0x40).

Write bank-related I

C registers with appropriate values for Bank 1.

Write Bank 2 (Write 0x00058040 to register 0x40).

Load bank-related I

C registers with appropriate values for Bank 2.

Write Bank 3 (Write 0x00068040 to register 0x40).

Load bank-related I

C registers with appropriate values for Bank 3.

Select automatic bank switching (write 0x00038040 to register 0x40)

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Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and

automatically switches to the appropriate bank.

In this example any sample rates other then 32 kHz and 44.1 kHz will use Bank 3. If other sample rates are

used, then the banks need to be set-up differently.

2.5.6 Bank Switching Example 2

Problem: The audio system uses all of the sample rates supported by the TAS5518. How can the automatic

bank switching be set up to handle this situation?

Strategy: Use the TAS5518 bank switching feature to allow for managing and switching three banks

associated with sample rates as follows:
·

Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz

Bank 2: Coefficients for 88.2kHz and 96 kHz

Bank 3: Coefficients for 176.4 kHz and 192 kHz

One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
·

Generate bank-related coefficients for sample rates 48 kHz (Bank 1), 96 kHz (Bank 2), and 192 kHz (Bank

3) and include the same in the micro-based TAS5518 I

C firmware.

On TAS5518 power-up or reset, the micro runs the following TAS5518 Initialization code:
-

Update Bank 1 (Write 0x0004F00C to register 0x40).

Write bank-related I

C registers with appropriate values for Bank 1.

Write Bank 2 (Write 0x0005F00C to register 0x40).

Load bank-related I

C registers with appropriate values for Bank 2.

Write Bank 3 (Write 0x0006F00C to register 0x40).

Load bank-related I

C registers with appropriate values for Bank 3.

Select automatic bank switching (Write 0x0003F00C to register 0x40)

Now when the audio media changes, the TAS5518 automatically detects the incoming sample rate and

automatically switches to the appropriate bank.

Electrical Specifications

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TAS5518

Electrical Specifications

3.1

Absolute Maximum Ratings

{

UNITS

Supply voltage, DVDD and DVD_PWM

-0.3 V to 3.6 V

Supply voltage, AVDD_PLL

-0.3 V to 3.6 V

3.3-V digital input

-0.5 V to DVDD + 0.5 V

Input voltage

5 V tolerant

(2)

digital input

-0.5 V to 6 V

Input voltage

1.8 V LVCMOS

(3)

-0.5 V to VREF

(1)

+ 0.5 V

Input clamp current, I

< 0 or V

> 1.8 V

±20 mA

Output clamp current, I

< 0 or V

> 1.8 V)

±20 mA

Operating free air temperature

0°C to 70°C

Storage temperature range, T

stg

-65°C to 150°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. VREF is a 1.8-V supply derived from regulators internal to the TAS5518 chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL,

VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source
power to external devices.

2. 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
3. VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM

DISSIPATION RATING TABLE (High-k Board, 1055C Junction)

PACKAGE

255C

POWER RATING

DERATING FACTOR

ABOVE T

= 255C

= 705C

POWER RATING

PAG

1869 mW

23.36 mW/°C

818 mW

3.2

Dynamic Performance (At Recommended Operating Conditions at 255C)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNITS

Dynamic range

TAS5518 + TAS5182 EVM A-weighted (F

= 48 kHz)

110

Total harmonic distortion

TAS5182 A at 1 W

0.1%

Total harmonic distortion

TAS5518 ouput

0.01%

Frequency response

32-kHz to 96-kHz sample rates

±0.1

Frequency response

176.4, 192-kHz sample rates

±0.2

3.3

Recommended Operating Conditions (over 05C to 705C)

MIN

NOM

MAX

UNITS

Digital supply voltage, DVDD and DVDD_PWM

3.3

3.6

Analog supply voltage, AVDD_PLL

3.3

3.6

3.3 V

High-level input voltage, V

5-V tolerant

(4)

High level input voltage, V

1.8-V LVCMOS (XTL_IN)

1.26

3.3 V

0.8

Low-level input voltage, V

5-V tolerant

(4)

0.8

Low level input voltage, V

1.8-V (XTL_IN)

0.54

Operating ambient air temperature range, T

-20

°C

Operating junction temperature range, T

-20

105

°C

NOTE 4: 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.

Electrical Specifications

SLES115 -- August 2004

TAS5518

3.4

Electrical Characteristics Over Recommended Operating Conditions (Unless

Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

High level output voltage

3.3 V TTL and 5 V

(6)

tolerant

= -4 mA

2.4

High-level output voltage

1.8-V LVCMOS (XTL_OUT)

= - 0.55 mA

1.44

Low level output voltage

3.3-V TTL and 5 V

(6)

tolerant

= 4 mA

0.5

Low-level output voltage

1.8-V LVCMOS (XTL_OUT)

= 0.75 mA

0.5

High-impedance output current

3.3-V TTL

±20

µA

3.3-V TTL

= V

±1

Low-level input current

1.8-V LVCMOS (XTL_IN)

= V

±1

µA

Low level input current

5 V tolerant

(5)

= 0 V DVDD = 3 V

±1

µA

3.3-V TTL

= V

±1

High-level input current

1.8-V LVCMOS (XTL_IN)

= V

±1

µA

High level input current

5 V tolerant

(5)

= 5.5 V DVDD = 3 V

±1

µA

Fs = 48 kHz

140

Digital supply voltage DVDD

Fs = 96 kHz

150

Input supply current

Digital supply voltage, DVDD

Fs = 192kHz

155

Input supply current

Power down

Analog supply voltage AVDD

Normal

Analog supply voltage, AVDD

Power down

NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.

6. 5-V tolerant outputs are SCL and SDA

3.5

PWM Operation at Recommended Operating Conditions Over 05C to 705C

PARAMETER

TEST CONDITIONS

MODE

VALUE

UNITS

32-kHz data rate ±4%

12 x sample rate

384

kHz

Output sample rate 1X 8 x over sampled

44.1-, 88.2-, 176.4-kHz data rate ±4%

8, 4, and 2 x sample rate

352.8

kHz

Output sample rate 1X 8 x over sampled

48, 96, 192 kHz data rate ±4%

8, 4, and 2 x sample rate

384

kHz

3.6

Switching Characteristics

3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise

Noted)

3.6.1.1

PLL Input Parameters and External Filter Components

{

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

XTALI

Frequency, XTAL IN

Only use 13.5-MHz crystal 1000 ppm

13.5

MHz

MCLKI

Frequency, MCLK (1 / t

cyc2

)

MHz

MCLK duty cycle duty cycle

40%

50%

60%

MCLK minimum high time

2-V MCLK = 49.152 MHz, Within the min

and max duty cycle constraints

MCLK minimum low time

0.8-V MCLK = 49.152 MHz,

Within the min and max duty cycle constraints

LRCLK allowable drift before LRCLK reset

10 MCLKs

External PLL filter cap C1

SMD 0603 Y5V

100

External PLL filter cap C2

SMD 0603 Y5V

External PLL filter resistor R

SMD 0603, metal film

200

External VRA_PLL decoupling

SMD, Y5V

100

See the TAS5518 Example Application Schematic section.

Serial Audio Interface Control and Timing

SLES115 -- August 2004

TAS5518

3.6.9 Volume Control

3.6.9.1

Control Signal Parameters Over Recommended Operating Conditions (Unless

Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNITS

Maximum attenuation before mute

Individual volume, master volume or a
combination of both

-127

Maximum gain

Individual volume, master volume

Maximum volume before the onset of clipping

0-dB input, any modulation limit

PSVC range

PSVC enabled

12, 18, or 24

PSVC rate

PSVC modulation

Single Sided

PSVC quantization

2048

Steps

PSVC PWM modulation limits

PSVC Rangel = 24 dB

6% (120 :

2048)

95% 1944 :

2048

3.7

Serial Audio Interface Control and Timing

3.7.1 I

S Timing

S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for

the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at

64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of

bit clock. The TAS5518 masks unused trailing data bit positions.

23 22

SCLK

32 Clks

LRCLK (Note Reversed Phase)

Left Channel

24-Bit Mode

19 18

20-Bit Mode

16-Bit Mode

15 14

MSB

LSB

23 22

SCLK

32 Clks

Right Channel

19 18

15 14

MSB

LSB

2-Channel I

S (Philips Format) Stereo Input

NOTE: All data presented in 2s complement form with MSB first.

Figure 3-9. I

S Format 64 Fs Format

C Serial Control Interface (Slave Address 0x36)

SLES115 -- August 2004

TAS5518

C Serial Control Interface (Slave Address 0x36)

The TAS5518 has a bidirectional I

C interface that compatible with the I

C (Inter IC) bus protocol and supports

both 100 Kbps and 400 Kbps data transfer rates for single and multiple byte write and read operations. This

is a slave only device that does not support a multi-master bus environment or wait state insertion. The control

interface is used to program the registers of the device and to read device status.
The TAS5518 supports the standard-mode I

C bus operation (100 kHz maximum) and the fast I

C bus

operation (400 kHz maximum). The TAS5518 performs all I

C operations without I

C wait cycles.

4.1

General I

C Operation

The I

C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits

in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred

in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on

the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with

the master device driving a start condition on the bus and ends with the master device driving a stop condition

on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and

stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.

Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in

Figure 4-1. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication

with another device and then wait for an acknowledge condition. The TAS5518 holds SDA low during

acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next

byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All

compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external

pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

7 Bit Slave Address

R/
W

8 Bit Register Address (N)

8 Bit Register Data For

Address (N)

Start

Stop

SDA

SCL

7 6 5 4 3 2 1 0

8 Bit Register Data For

Address (N)

7 6 5 4 3 2 1 0

Figure 4-1. Typical I

C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the

last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence

is shown in Figure 4-1.
The 7-bit address for the TAS5518 is 0011011.

4.2

Single and Multiple Byte Transfers

The serial control interface supports both single-byte and multiple-byte read / write operations for status

registers and the general control registers associated with the PWM. However, for the DAP data processing

registers, the serial control interface supports only multiple byte (4 byte) read / write operations.
During multiple byte read operations, the TAS5518 responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular

subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple byte write operations, the TAS5518 compares the number of bytes transmitted to the number

of bytes that are required for each specific sub address. If a write command is received for a biquad

subaddress, the TAS5518 expects to receive five 32-bit words. If fewer than five 32-bit data words have been

received when a stop command (or another start command) is received, the data received is discarded.

Similarly, if a write command is received for a mixer coefficient, the TAS5518 expects to receive one 32-bit

word.

C Serial Control Interface (Slave Address 0x36)

SLES115 -- August 2004

TAS5518

Supplying a subaddress for each subaddress transaction is referred to as random I

C addressing. The

TAS5518 also supports sequential I

C addressing. For write transactions, if a subaddress is issued followed

by data for that subaddress and the fifteen subaddresses that follow, a sequential I

C write transaction has

taken place, and the data for all 16 subaddresses is successfully received by the TAS5518. For I

C sequential

write transactions, the subaddress then serves as the start address and the amount of data subsequently

transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true

for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a

partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,

all other data written is accepted; just the incomplete data is discarded.

4.3

Single Byte Write

As shown in Figure 4-2, a single byte data write transfer begins with the master device transmitting a start

condition followed by the I

C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I

C device

address and the read/write bit, the TAS5518 device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5518 internal memory address being accessed.

After receiving the address byte, the TAS5518 again responds with an acknowledge bit. Next, the master

device transmits the data byte to be written to the memory address being accessed. After receiving the data

byte, the TAS5518 again responds with an acknowledge bit. Finally, the master device transmits a stop

condition to complete the single byte data write transfer.

A0 R/W ACK A7

A0 ACK D7

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

C Device Address and

Read/Write Bit

Sub-Address

Data Byte

Figure 4-2. Single Byte Write Transfer

4.4

Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes

are transmitted by the master device to TAS5518 as shown in Figure 4-3. After receiving each data byte, the

TAS5518 responds with an acknowledge bit.

D0 ACK

Stop

Condition

Acknowledge

C Device Address and

Read/Write Bit

Sub-Address

Last Data Byte

A0 R/W ACK A7

A0 ACK D7

ACK

Start

Condition

Acknowledge

First Data Byte

Other Data Bytes

ACK

Acknowledge

Figure 4-3. Multiple Byte Write Transfer

4.5

Incremental Multiple Byte Write

The I

C supports a special mode which permits I

C write operations to be broken up into multiple data write

operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte, ... etc., write

operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes

of data. This permits the system to incrementally write large register values without blocking other I

transactions.

This feature is enabled by the append subaddress function in the TAS5518. This function enables the

TAS5518 to append 4 bytes of data to a register that was opened by a previous I

C register write operation

but has not received its complete number of data bytes. Since the length of the long registers is a multiple of

4 bytes, using 4-byte transfers will have only an integer number of append operations.

C Serial Control Interface (Slave Address 0x36)

SLES115 -- August 2004

TAS5518

When the correct number of bytes has been received, the TAS5518 starts processing the data.

The procedure to perform an incremental multi-byte write operation is as follows:
1. Start a normal I

C write operation by sending the device address, write bit, register subaddress, and the

first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point,

the register has been opened and accepts the remaining data that is sent by writing 4-byte blocks of data

to the append subaddress (0xFE).

2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining

number of bytes in sequential order to complete the register write operation. Each of these append

operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes

of data followed by a stop condition.

3. The operation will be terminated due to an error condition and the data will be flushed:

a. If a new subaddress is written to the TAS5518 before the correct number of bytes have been written.
b. If more or less than 4 bytes are data written at the beginning or during any of the append operations.
c. If a read bit is sent.

4.6

Single Byte Read

As shown in Figure 4-4, a single byte data read transfer begins with the master device transmitting a start

condition followed by the I

C device address and the read/write bit. For the data read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

memory address to be read. As a result, the read/write bit will be a 0. After receiving the TAS5518 address

and the read/write bit, the TAS5518 responds with an acknowledge bit. In addition, after sending the internal

memory address byte or bytes, the master device transmits another start condition followed by the TAS5518

address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After

receiving the TAS5518 and the read/write bit the TAS5518 again responds with an acknowledge bit. Next, the

TAS5518 transmits the data byte from the memory address being read. After receiving the data byte, the

master device transmits a not acknowledge followed by a stop condition to complete the single byte data read

transfer.

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

C Device Address and

Read/Write Bit

Sub-Address

Data Byte

D7 D6

D0 ACK

C Device Address and

Read/Write Bit

Not

Acknowledge

R/W

Repeat Start

Condition

Figure 4-4. Single Byte Read Transfer

4.7

Multiple Byte Read

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS5518 to the master device as shown in Figure 4-5. Except for the last data byte,

the master device responds with an acknowledge bit after receiving each data byte.

ACK

Acknowledge

C Device Address and

Read/Write Bit

R/W

A0 R/W ACK

A0 ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

Last Data Byte

ACK

First Data Byte

Repeat Start

Condition

Not

Acknowledge

C Device Address and

Read/Write Bit

Sub-Address

Other Data Bytes

D0 ACK

Acknowledge

Figure 4-5. Multiple Byte Read Transfer

Serial Control I

C Register Summary

SLES115 -- August 2004

TAS5518

Serial Control I

C Register Summary

The TAS5518 slave address is 0x36. See the Serial Control I

C Register Bit Definitions chapter for complete

bit definitions.

Note that u indicates unused bits.

SUBADDRESS

TOTAL

BYTES

REGISTER FIELDS

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x00

Clock control register

Set data rate and MCLK frequency

1. Fs = 48 kHz
2. MCLK = 256 Fs = 12.288 MHz

0x01

General status register

Clip indicator and ID code for the
TAS5518

0x01

0x02

Error status register

PLL, SCLK, LRCLK, and frame slip
errors

No errors

0x03

System control register 1

PWM high pass, clock set, un-mute
select, PSVC select

1. PWM high pass disabled
2. Auto clock set
3. Hard un-mute on clock error
recovery
4. PSVC HIZ disable

0x04

System control register 2

Automute and de-emphasis control

1. Automute timeout disable
2. Post-DAP detection automute
enabled
3. 8-Ch device input detection
automute enabled
4. Un-mute threshold 6 dB over input
5. No de-emphasis

0x05 0x0C

Channel configuration registers

Configure channels 1, 2, 3, 4, 5, 6, 7,
and 8

1. Enable backend reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Don't remap the output for the
TAS5182
6. Don't go low-low in mute
7. Don't remap Hi-Z state to
low-low state

0x0D

Headphone configuration
register

Configure headphone output

1. Disable backend reset sequence
2 Valid does not have to be low for
reset
3. Valid does not have to be low for
mute
4. Normal BEPolarity
5. Don't remap output to comply
with 5182
6. Don't go low-low in mute
7. Don't remap Hi-Z state to
low-low state

0x0E

Serial data interface register

Set serial data interface to right
justified, I2S, or left justified

24-bit I2S

0x0F

Soft mute register

Soft mute for channels 1, 2, 3, 4, 5, 6,
7, and 8

Un-mute all channels

0x10 0x13

RESERVED

0x14

Automute control

Set auto-mute delay and threshold

1. Set auto-mute delay = 5 ms
2. Set auto-mute threshold less
than bit 8

0x15

Automute PWM threshold and
backend reset period

Set PWM auto-mute threshold, set
backend reset period

1. Set the PWM threshold the same
as the TAS5518 input threshold
2. Set backend reset
period = 5 ms

0x16

Modulation limit register

Set modulation index

97.7%

Serial Control I

C Register Summary

SLES115 -- August 2004

TAS5518

SUBADDRESS

DEFAULT STATE

DESCRIPTION OF CONTENTS

REGISTER FIELDS

TOTAL

BYTES

0x17-0x1A

RESERVED

0x1B0x22

1/Reg.

Inter-channel delay registers

Set inter-channel delay

Channel 1 delay = -23 DCLK
periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = -16 DCLK
periods
Channel 4 delay = +16 DCLK
periods
Channel 5 delay = -24 DCLK
periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = -8 DCLK
periods
Channel 8 delay = 24 DCLK
periods

0x23

Inter-channel offset

Absolute delay offset for channel 1
(0 255)

Minimum absolute default = 0
DCLK periods

0x24-0x3F

RESERVED

0x40

Bank switching command
register

Set up DAP coefficients bank
switching for banks 1, 2, and 3

Manual selection Bank 1

0x410x48

32/Reg

See the Input Mixer Registers
(0x41 0x48, Channels 1 8)
section

8X8 input crossbar mixer setup

SDIN1-Left to input mixer 1
SDIN1-Right to input mixer 2
SDIN2-Left to input mixer 3
SDIN2-Right to input mixer 4
SDIN3-Left to input mixer 5
SDIN3-Right to input mixer 6
SDIN4-Left to input mixer 7
SDIN4-Right to input mixer 8

0x49

ipmix_1_to_ch8

Input mixer 1 to Ch 8 mixer coefficient

0.0

0x4A

ipmix_2_to_ch8

Input mixer 1 to Ch 8 mixer coefficient

0.0

0x4B

ipmix_7_to_ch2

Input mixer 7 to Ch 2 mixer coefficient

0.0

0x4C

Ch7_bp_bq2

Bypass Ch 7 biquad 2 coefficient

0.0

0x4D

Ch7_bq2

Ch 7 biquad 2 coefficient

1.0

0x4E

ipmix_8_to_ch12

Ch 8 biquad 2 output to Ch1 mixer
and Ch2 mixer coefficient

0.0

0x4F

Ch8_bp_bq2

Bypass Ch 8 biquad 2 coefficient 0

0.0

0x50

Ch8_bq2

Ch 8 biquad 2 coefficient

1.0

0x510x88

20/Reg. See the next section

Channels 1, 2, 3, 4, 5, 6, 7, and 8
biquad filter coefficients

All biquads = All pass for all
channels

0x890x90

Bass and Treble Bypass
Ch 1 - 8

Bypass bass and treble for
channels 1-8

Bass and treble bypassed for all
channels

0x91

Loudness Log2 LG

0.5

0x92

Loudness Log2 LO

0.0

0x93

Loudness G

0.0

0x94

Loudness O

0.0

Loudness biquad coefficient b0

0x00, 0x00, 0xD5, 0x13

Loudness biquad coefficient b1

0x00, 0x00, 0x00, 0x00

0x95

Loudness biquad

Loudness biquad coefficient b2

0x0F, 0xFF, 0x2A, 0xED

0x95

Loudness biquad

Loudness biquad coefficient a0

0x00, 0xFE, 0x50, 0x45

Loudness biquad coefficient a1

0x0F, 0x81, 0xAA, 0x27

0x96

DRC1 control channels 1, 2, 3,
4, 5, 6, and 7

DRC1 control channels 1, 2, 3, 4, 5, 6,
and 7

DRC1 disabled in channels 1, 2, 3,
4, 5, 6, and 7

0x97

DRC2 Ch 8 Control

DRC1 control channel 8

DRC2 disabled (channel 8)

Serial Control I

C Register Summary

SLES115 -- August 2004

TAS5518

SUBADDRESS

DEFAULT STATE

DESCRIPTION OF CONTENTS

REGISTER FIELDS

TOTAL

BYTES

0x98

Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 energy

DRC1 energy

0.0041579

0x98

Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 (1- energy)

DRC1 (1 energy)

0.9958421

Channels 1, 2, 3, 4, 5, 6, and 7

DRC1 threshold (T1) upper 4 bytes

0x00, 0x00, 0x00, 0x00

0x99

, , , , , ,

DRC1 threshold T1

DRC1 threshold (T1) lower 4 bytes

0x0B, 0x20, 0xE2, 0xB2

0x99

Channels 1, 2, 3, 4, 5, 6, and 7

DRC1 threshold (T2) upper 4 bytes

0x00, 0x00, 0x00, 0x00

, , , , , ,

DRC1 thresholdT2

DRC1 threshold (T2) lower 4 bytes

0x06, 0xF9, 0xDE, 0x58

Channels 1, 2, 3, 4, 5, 6, and 7
, DRC1 slope k0

DRC1 slope (k0)

0x0F, 0xC0, 0x00, 0x00

0x9A

Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 slope k1

DRC1 slope (k1)

0x0F, 0xC0, 0x00, 0x00

Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 slope k2

DRC1 slope (k2)

0x0F, 0x90, 0x00, 0x00

Channels 1, 2, 3, 4, 5, 6, and 7

DRC1 offset 1 (O1) upper 4 bytes

0x00, 0x00, 0xFF, 0xFF

0x9B

, , , , , ,

DRC1 offset 1

DRC1 offset 1 (O1) lower 4 bytes

0xFF, 0x82, 0x30, 0x98

0x9B

Channels 1, 2, 3, 4, 5, 6, and 7

DRC1 offset 2 (O2) upper 4 bytes

0x00, 0x00, 0x00, 0x00

, , , , , ,

DRC1 offset 2

DRC1 offset 2 (O2) lower 4 bytes

0x01, 0x95, 0xB2, 0xC0

Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 attack

DRC1 attack

0x00, 0x00, 0x88, 0x3F

0x9C

Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1- Attack)

DRC1 (1 Attack)

0x00, 0x7F, 0x77, 0xC0

0x9C

Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 Delay

DRC1 delay

0x00, 0x00, 0x00, 0xAE

Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1- Delay)

DRC1 (1 Delay)

0x00, 0x7F, 0xFF, 0x51

0x9D

Ch 8 DRC2 energy

DRC2 energy

0x00, 0x00, 0x88, 0x3F

0x9D

Ch 8 DRC2 (1- Energy)

DRC2 (1 Energy)

0x00, 0x7F, 0x77, 0xC0

CH 8 DRC2 threshold T1

DRC2 threshold (T1) upper 4 bytes

0x00, 0x00, 0x00, 0x00

0x9E

CH 8 DRC2 threshold T1

DRC2 threshold (T1) lower 4 bytes

0x0B, 0x20, 0xE2, 0xB2

0x9E

CH 8 DRC2 threshold T2

DRC2 threshold (T2) upper 4 bytes

0x00, 0x00, 0x00, 0x00

CH 8 DRC2 threshold T2

DRC2 threshold (T2) lower 4 bytes

0x06, 0xF9, 0xDE, 0x58

Ch 8 DRC2 slope k0

DRC2 slope (k0)

0x00, 0x40, 0x00, 0x00

0x9F

Ch 8 DRC2 slope k1

DRC2 slope (k1)

0x0F, 0xC0, 0x00, 0x00

0x9F

Ch 8 DRC2 slope k2

DRC2 slope (k2)

0x0F, 0x90, 0x00, 0x00

Ch 8 DRC2 offset 1

DRC2 offset (O1) upper 4 bytes

0x00, 0x00, 0xFF, 0xFF

0xA0

Ch 8 DRC2 offset 1

DRC2 offset (O1) lower 4 bytes

0xFF, 0x82, 0x30, 0x98

0xA0

Ch 8 DRC2 offset 2

DRC2 offset (O2) upper 4 bytes

0x00, 0x00, 0x00, 0x00

Ch 8 DRC2 offset 2

DRC2 offset (O2) lower 4 bytes

0x01, 0x95, 0xB2, 0xC0

Ch 8 DRC2 attack

DRC 2 attack

0x00, 0x00, 0x88, 0x3F

0xA1

Ch 8 DRC2 (1- Attack)

DRC2 (1 Attack)

0x00, 0x7F, 0x77, 0xC0

0xA1

Ch 8 DRC2 Delay

DRC2 delay

0x00, 0x00, 0x00, 0xAE

Ch 8 DRC2 (1- Delay)

DRC2 (1 Delay)

0x00, 0x7F, 0xFF, 0x51

0xA2

DRC bypass 1

Channel 1 DRC1 bypass coefficient

1.0

0xA2

DRC inline 1

Channel 1 DRC1 inline coefficient

0.0

0xA3

DRC bypass 2

Channel 2 DRC1 bypass coefficient

1.0

0xA3

DRC inline 2

Channel 2 DRC1 inline coefficient

0.0

Serial Control I

C Register Summary

SLES115 -- August 2004

TAS5518

SUBADDRESS

DEFAULT STATE

DESCRIPTION OF CONTENTS

REGISTER FIELDS

TOTAL

BYTES

0xA4

DRC bypass 3

Channel 3 DRC1 bypass coefficient

1.0

0xA4

DRC inline 3

Channel 3 DRC1 inline coefficient

0.0

0xA5

DRC bypass 4

Channel 4 DRC1 bypass coefficient

1.0

0xA5

DRC inline 4

Channel 4 DRC1 inline coefficient

0.0

0xA6

DRC bypass 5

Channel 5 DRC1 bypass coefficient

1.0

0xA6

DRC inline 5

Channel 5 DRC1 inline coefficient

0.0

0xA7

DRC bypass 6

Channel 6 DRC1 bypass coefficient

1.0

0xA7

DRC inline 6

Channel 6 DRC1 inline coefficient

0.0

0xA8

DRC bypass 7

Channel 7 DRC1 bypass coefficient

1.0

0xA8

DRC inline 7

Channel 7 DRC1 inline coefficient

0.0

0xA9

DRC bypass 8

Channel 8 DRC2 bypass coefficient

1.0

0xA9

DRC inline 8

Channel 8 DRC2 inline coefficient

0.0

0xAA

sel op1-8 and mix to S

Select 0 to 2 of eight channels to
output mixer S

Select channel 1 to PWM 1

0xAB

sel op1-8 and mix to T

Select 0 to 2 of eight channels to
output mixer T

Select channel 2 to PWM 2

0xAC

sel op1-8 and mix to U

Select 0 to 2 of eight channels to
output mixer U

Select channel 3 to PWM 3

0xAD

sel op1-8 and mix to V

Select 0 to 2 of eight channels to
output mixer V

Select channel 4 to PWM 4

0xAE

sel op1-8 and mix to W

Select 0 to 2 of eight channels to
output mixer W

Select channel 5 to PWM 5

0xAF

sel op1-8 and mix to X

Select 0 to 2 of eight channels to
output mixer X

Select channel 6 to PWM 6

0xB0

sel op1-8 and mix to Y

Select 0 to 3 of eight channels to
output mixer Y

Select channel 7 to PWM 7

0xB1

sel op1-8 and mix to Z

Select 0 to 3 of eight channels to
output mixer Z

Select channel 8 to PWM 8

0xB20xCE

RESERVED

0xCF

Volume biquad

All pass

0xD0

Vol, T and B slew rates

U (31:24), U (23:16), U (15:12)
VSR(11:8), TBSR(7:0)

0x00, 0x00, 0x01, 0x3F

0xD1

Ch1 volume

Channel 1 volume

0 dB

0xD2

Ch2 volume

Channel 2 volume

0 dB

0xD3

Ch3 volume

Channel 3 volume

0 dB

0xD4

Ch4 volume

Channel 4 volume

0 dB

0xD5

Ch5 volume

Channel 5 volume

0 dB

0xD6

Ch6 volume

Channel 6 volume

0 dB

0xD7

Ch7 volume

Channel 7 volume

0 dB

0xD8

Ch8 volume

Channel 8 volume

0 dB

0xD9

Master volume

Mute

OXDA

Bass filter set (1-5)

Bass filter set (all channels)

Filter set 3

0xDB

Bass filter index

Bass filter level (all channels)

0 dB

0xDC

Treble filter set (1-5)

Treble filter set (all channels)

Filter set 3

0xDD

Treble filter index

Treble filter level (all channels)

0 dB

0xDE

AM mode and tuned frequency
register

Set-up AM mode for AM-interference
reduction

AM mode disabled
Select sequence 1
IF frequency = 455 kHz
Use BCD-tuned frequency

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Serial Control Interface Register Definitions

Unless otherwise noted, the I

C register default values are in bold font.

Note that u indicates unused bits.

6.1

Clock Control Register (0x00)

Bit D1 is Don't Care.

Table 6-1. Clock Control Register

FUNCTION

32-kHz data rate

38-kHz data rate

44.1-kHz data rate

48-kHz data rate

88.2-kHz data rate

96-kHz data rate

176.4-kHz data rate

192-kHz data rate

MCLK frequency = 64

MCLK frequency = 128

MCLK frequency = 192

MCLK frequency = 256

MCLK frequency = 384

MCLK frequency = 512

MCLK frequency = 768

Reserved

Clock register is valid (read only)

Clock register is not valid (read only)

6.2

General Status Register 0 (0x01)

Table 6-2. General Status Register (0x01)

FUNCTION

Clip indicator

Bank switching busy

Identification code for TAS5518

6.3

Error Status Register (0x02)

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must

clear the register (write zeroes) and than read them to determine if there are any persistent errors.

Table 6-3. Error Status Register (0X02)

FUNCTION

PLL phase lock error

PLL auto lock error

SCLK error

LRCLK error

Frame slip

No errors

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.4

System Control Register 1 (0x03)

Bit D5, D2, D1, and D0 are Don't Care.

Table 6-4. System Control Register 1

FUNCTION

PWM high pass disabled

PWM high pass enabled

Soft unmute on recovery from clock error

Hard unmute on recovery from clock error

PSVC Hi-Z enable

PSVC Hi-Z disable

6.5

System Control Register 2 (0x04)

Bit D3 and D2 are Don't Care.

Table 6-5. System Control Register 2

FUNCTION

Reserved

PWM automute detection enabled

PWM automute detection disabled

8 Ch device input detection automute enabled

8 Ch device input detection automute disabled

Unmute threshold 6 dB over input threshold

Unmute threshold equal to input threshold

No de-emphasis

De-emphasis for Fs = 32 kHz

De-emphasis for Fs = 44.1 kHz

De-emphasis for Fs = 48 kHz

6.6

Channel Configuration Control Register (0x05-X0C)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into x05, x06, x07, x08, x09, x0A, x0B, and x0C.

Bit D0 is Don't Care.

Table 6-6. Channel Configuration Control Registers

FUNCTION

Disable backend reset sequence for a channel - BEErrorRecEn

Enable backend reset sequence for a channel

Valid does not have to be low for this channel to be reset BEValidRst

Valid must be low for this channel to be reset

Valid does not have to be low for this channel to be muted BEValidMute

Valid must be low for this channel to be muted

Normal BEPolarity

Switches PWM+ and PWM- and invert audio signal

Do not remap output to comply with 5182 interface

Remap output to comply with 5182 interface

Do not go to low low in mute - BELowMute

Go to low-low in Mute

Do not remap Hi-Z state to low-low state - BE5111BsMute

Remap Hi-Z state to low-low state

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.7

Headphone Configuration Control Register (0x0D)

Bit D0 is Don't Care.

Table 6-7. Headphone Configuration Control Register

FUNCTION

Disable backend reset sequence for a channel - BEErrorRecEn

Enable backend reset sequence for a channel

Valid does not have to be low for this channel to be reset BEValidRst

Valid must be low for this channel to be reset

Valid does not have to be low for this channel to be muted BEValidMute

Valid must be low for this channel to be muted

Normal BEPolarity

Switches PWM+ and PWM- and invert audio signal

Do not remap output to comply with 5182 interface

Remap output to comply with 5182 interface

Do not go to low low in mute - BELowMute

Go to low-low in Mute

Do not remap Hi-Z state to low-low state - BE5111BsMute

Remap Hi-Z state to low-low state

6.8

Serial Data Interface Control Register (0x0E)

Nine serial modes can be programmed I

Table 6-8. Serial Data Interface Control Register Format

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD LENGTHS

D7-D4

Right justified

0000

Right justified

0000

Right justified

0000

Left justified

0000

Left justified

0000

Left justified

0000

Illegal

0000

Illegal

0000

Illegal

0000

Illegal

0000

Illegal

0000

Illegal

0000

Illegal

0000

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.9

Soft Mute Register (0x0F)

Table 6-9. Soft Mute Register

Function

Soft Mute Channel 1

Soft Mute Channel 2

Soft Mute Channel 3

Soft Mute Channel 4

Soft Mute Channel 5

Soft Mute Channel 6

Soft Mute Channel 7

Soft Mute Channel 8

Unmute All Channels

6.10 Automute Control Register(0x14)

Table 6-10. Automute Control Register

FUNCTION

Set input automute and PWM automute delay to 1 ms

Set input automute and PWM automute delay to 2 ms

Set input automute and PWM automute delay to 3 ms

Set input automute and PWM automute delay to 4 ms

Set input automute and PWM automute delay to 5 ms

Set input automute and PWM automute delay to 10 ms

Set input automute and PWM automute delay to 20 ms

Set input automute and PWM automute delay to 30 ms

Set input automute and PWM automute delay to 40 ms

Set input automute and PWM automute delay to 50 ms

Set input automute and PWM automute delay to 60 ms

Set input automute and PWM automute delay to 70ms

Set input automute and PWM automute delay to 80 ms

Set input automute and PWM automute delay to 90 ms

Set input automute and PWM automute delay to 100 ms

Set input automute and PWM automute delay to 110 ms

Set input automute threshold less than Bit 1 (zero input signal), lowest automute

Set input automute threshold less than Bit 1 (zero input signal), lowest automute
threshold.

Set input automute threshold less than Bit 2

Set input automute threshold less than Bit 3

Set input automute threshold less than Bit 4

Set input automute threshold less than Bit 5

Set input automute threshold less than Bit 6

Set input automute threshold less than Bit 7

Set input automute threshold less than Bit 8

Set input automute threshold less than Bit 9

Set input automute threshold less than Bit 10

Set input automute threshold less than Bit 11

Set input automute threshold less than Bit 12

Set input automute threshold less than Bit 13

Set input automute threshold less than Bit 14

Set input automute threshold less than Bit 15

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.11 Automute PWM Threshold and Backend Reset Period (0x15)

Table 6-11. Automute PWM Threshold and Backend Reset Period

FUNCTION

Set PWM automute threshold equals input automute threshold

Set PWM automute threshold 1 bit more than input automute threshold

Set PWM automute threshold 2 bits more than input automute threshold

Set PWM automute threshold 3 bits more than input automute threshold

Set PWM automute threshold 4 bits more than input automute threshold

Set PWM automute threshold 5 bits more than input automute threshold

Set PWM automute threshold 6 bits more than input automute threshold

Set PWM automute threshold 7 bits more than input automute threshold

Set PWM automute threshold equals input automute threshold

Set PWM automute threshold 1 bit less than input automute threshold

Set PWM automute threshold 2 bits less than input automute threshold

Set PWM automute threshold 3 bits less than input automute threshold

Set PWM automute threshold 4 bits less than input automute threshold

Set PWM automute threshold 5 bits less than input automute threshold

Set PWM automute threshold 6 bits less than input automute threshold

Set PWM automute threshold 7 bits less than input automute threshold

Set backend reset period < 1 ms

Set backend reset period 1 ms

Set backend reset period 2 ms

Set backend reset period 3 ms

Set backend reset period 4 ms

Set backend reset period 5 ms

Set backend reset period 6 ms

Set backend reset period 7 ms

Set backend reset period 8 ms

Set backend reset period 9 ms

Set backend reset period 10 ms

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.12 Modulation Index Limit Register (0x16)

Table 6-12. Modulation Index Limit Register

LIMIT

[DCLKS]

MIN WIDTH

[DCLKS]

MODULATION INDEX

99.2%

98.4%

97.7%

96.9%

96.1%

95.3%

94.5%

93.8%

6.13 Interchannel Channel Delay Registers (0x1B - 0x22) and Offset Register (0x23)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22).

Bits D1 and D0 are Don't Care.

Table 6-13. Interchannel Channel Delay Registers

FUNCTION

Minimum absolute delay, 0 DCLK cycles, default for channel 1

Maximum positive delay, 31 x 4 DCLK cycles

Maximum negative delay, -32 x 4 DCLK cycles

Default value for Channel 1 -32

Default value for Channel 2 0

Default value for Channel 3 -16

Default value for Channel 4 16

Default value for Channel 5 -24

Default value for Channel 6 8

Default value for Channel 7 -8

Default value for Channel 8 24

The offset register is mapped into 0x23.

Table 6-14. Channel Offset Register

FUNCTION

Minimum absolute offset, 0 DCLK cycles default for channel 1

Maximum absolute delay, 255 DCLK cycles

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.14 Bank Switching Command (0x40)

Bits D31-D24, D22-D19 are Don't Care.

Table 6-15. Bank Switching Command

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Unused bits

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

Manual selection Bank 1

Manual selection Bank 2

Manual selection Bank 3

Automatic bank selection

Update the values in Bank 1

Update the values in Bank 2

Update the values in Bank 3

Update only the bank map

Update the bank map using values in
D15-D0

Do not update the bank map using
values in D15-D0

D15

D14

D13

D12

D11

D10

FUNCTION

32-kHz data rate Use Bank 1

38-kHz data rate Use Bank 1

44.1-kHz data rate Use Bank 1

48-kHz data rate Use Bank 1

88.2-kHz data rate Use Bank 1

96-kHz data rate Use Bank 1

176.4-kHz data rate Use Bank 1

192-kHz data rate Use Bank 1

Default

FUNCTION

32-kHz data rate Use Bank 2

38-kHz data rate Use Bank 2

44.1-kHz data rate Use Bank 2

48-kHz data rate Use Bank 2

88.2-kHz data rate Use Bank 2

96-kHz data rate Use Bank 2

176.4-kHz data rate Use Bank 2

192-kHz data rate Use Bank 2

Default

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.15 Input Mixer Registers (0x41 0x48, Channels 1 - 8)

Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and

0x48.

Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as

a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.

Bold indicates the one channel that is passed through the mixer.

Table 6-16. Input Mixer Registers Format (0x41 0x48, Channels 1 - 8)

SUBADDRESS

TOTAL

BYTES

REGISTER

FIELDS

DESCRIPTION OF CONTENTS

DEFAULT STATE

A_to_ipmix[1]

SDIN1-Left (Ch 1) A to Input Mixer 1 coefficient (default = 1)
U (31:28), A_1 (27:24), A_1 (23:16), A_1 (15:8), A_1 (7:0)

0x00, 0x80, 0x00, 0x00

B_to_ipmix[1]

SDIN1-Right (Ch 2) B to Input Mixer 1 coefficient (default = 0)
U (31:28), B_1 (27:24), B_1 (23:16), B_1 (15:8), B_1 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[1]

SDIN2-Left (Ch 3) C to Input Mixer 1 coefficient (default = 0)
U (31:28), C_1 (27:24), C_1 (23:16), C_1 (15:8), C_1 (7:0)

0x00, 0x00, 0x00, 0x00

0x41

D_to_ipmix[1]

SDIN2-Right (Ch 4) D to Input Mixer 1 coefficient (default = 0)
U (31:28), D_1 (27:24), D_1 (23:16), D_1 (15:8), D_1 (7:0)

0x00, 0x00, 0x00, 0x00

0x41

E_to_ipmix[1]

SDIN3-Left (Ch 5) E to Input Mixer 1 coefficient (default = 0)
U (31:28), E_1 (27:24), E_1 (23:16), E_1 (15:8), E_1 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[1]

SDIN3-Right (Ch 6) F to Input Mixer 1 coefficient (default = 0)
U (31:28), F_1 (27:24), F_1 (23:16), F_1 (15:8), F_1 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[1]

SDIN4-Left (Ch 7) G to Input Mixer 1 coefficient (default = 0)
U (31:28), G_1 (27:24), G_1 (23:16), G_1 (15:8), G_1 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[1]

SDIN4-Right (Ch 8) H to Input Mixer 1 coefficient (default = 0)
U (31:28), H_1 (27:24), H_1 (23:16), H_1 (15:8), H_1 (7:0)

0x00, 0x00, 0x00, 0x00

A_to_ipmix[2]

SDIN1-Left (Ch 1) A to Input Mixer 2 coefficient (default = 0)
U (31:28), A_2 (27:24), A_2 (23:16), A_2 (15:8), A_2 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[2]

SDIN1-Right (Ch 2) B to Input Mixer 2 coefficient (default = 1)
U (31:28), B_2 (27:24), B_2 (23:16), B_2 (15:8), B_2 (7:0)

0x00, 0x80, 0x00, 0x00

C_to_ipmix[2]

SDIN2-Left (Ch 3) C to Input Mixer 2 coefficient (default = 0)
U (31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)

0x00, 0x00, 0x00, 0x00

0x42

D_to_ipmix[2]

SDIN2-Right (Ch 4) D to Input Mixer 2 coefficient (default = 0)
U (31:28), D_2 (27:24), D_2 (23:16), D_2 (15:8), D_2 (7:0)

0x00, 0x00, 0x00, 0x00

0x42

E_to_ipmix[2]

SDIN3-Left (Ch 5) E to Input Mixer 2 coefficient (default = 0)
U (31:28), E_2 (27:24), E_2 (23:16), E_2 (15:8), E_2 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[2]

SDIN3-Right (Ch 6) F to Input Mixer 2 coefficient (default = 0)
U (31:28), F_2 (27:24), F_2 (23:16), F_2 (15:8), F_2 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[2]

SDIN4-Left (Ch 7) G to Input Mixer 2 coefficient (default = 0)
U (31:28), G_2 (27:24), G_2 (23:16), G_2 (15:8), G_2 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[2]

SDIN4-Right (Ch 8) H to Input Mixer 2 coefficient (default = 0)
U (31:28), H_2 (27:24), H_2 (23:16), H_2 (15:8), H_2 (7:0)

0x00, 0x00, 0x00, 0x00

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

SUBADDRESS

TOTAL

BYTES

REGISTER

FIELDS

DESCRIPTION OF CONTENTS

DEFAULT STATE

A_to_ipmix[3]

SDIN1-Left (Ch 1) A to Input Mixer 3 coefficient (default = 0)
U (31:28), A_3 (27:24), A_3 (23:16), A_3 (15:8), A_3 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[3]

SDIN1-Right (Ch 2) B to Input Mixer 3 coefficient (default = 0)
U (31:28), B_3 (27:24), B_3 (23:16), B_3 (15:8), B_3 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[3]

SDIN2-Left (Ch 3) C to Input Mixer 3 coefficient (default = 1)
U (31:28), C_3 (27:24), C_3 (23:16), C_3 (15:8), C_3 (7:0)

0x00, 0x80, 0x00, 0x00

0x43

D_to_ipmix[3]

SDIN2-Right (Ch 4) D to Input Mixer 3 coefficient (default = 0)
U (31:28), D_3 (27:24), D_3 (23:16), D_3 (15:8), D_3 (7:0)

0x00, 0x00, 0x00, 0x00

0x43

E_to_ipmix[3]

SDIN3-Left (Ch 5) E to Input Mixer 3 coefficient (default = 0)
U (31:28), E_3 (27:24), E_3 (23:16), E_3 (15:8), E_3 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[3]

SDIN3-Right (Ch 6) F to Input Mixer 3 coefficient (default = 0)
U (31:28), F_3 (27:24), F_3 (23:16), F_3 (15:8), F_3 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[3]

SDIN4-Left (Ch 7) G to Input Mixer 3 coefficient (default = 0)
U (31:28), G_3 (27:24), G_3 (23:16), G_3 (15:8), G_3 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[3]

SDIN4-Right (Ch 8) H to Input Mixer 3 coefficient (default = 0)
U (31:28), H_3 (27:24), H_3 (23:16), H_3 (15:8), H_3 (7:0)

0x00, 0x00, 0x00, 0x00

A_to_ipmix[4]

SDIN1-Left (Ch 1) A to Input Mixer 4 coefficient (default = 0)
U (31:28), A_4 (27:24), A_4 (23:16), A_4 (15:8), A_4 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[4]

SDIN1-Right (Ch 2) B to Input Mixer 4 coefficient (default = 0)
U (31:28), B_4 (27:24), B_4 (23:16), B_4 (15:8), B_4 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[4]

SDIN2-Left (Ch 3) C to Input Mixer 4 coefficient (default = 0)
U (31:28), C_4 (27:24), C_4 (23:16), C_4 (15:8), C_4 (7:0)

0x00, 0x00, 0x00, 0x00

0x44

D_to_ipmix[4]

SDIN2-Right (Ch 4) D to Input Mixer 4 coefficient (default = 1)
U (31:28), D_4 (27:24), D_4 (23:16), D_4 (15:8), D_4 (7:0)

0x00, 0x80, 0x00, 0x00

0x44

E_to_ipmix[4]

SDIN3-Left (Ch 5) E to Input Mixer 4 coefficient (default = 0)
U (31:28), E_4 (27:24), E_4 (23:16), E_4 (15:8), E_4 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[4]

SDIN3-Right (Ch 6) F to Input Mixer 4 coefficient (default = 0)
U (31:28), F_4 (27:24), F_4 (23:16), F_4 (15:8), F_4 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[4]

SDIN4-Left (Ch 7) G to Input Mixer 4 coefficient (default = 0)
U (31:28), G_4 (27:24), G_4 (23:16), G_4 (15:8), G_4 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[4]

SDIN4-Right (Ch 8) H to Input Mixer 4 coefficient (default = 0)
U (31:28), H_4 (27:24), H_4 (23:16), H_4 (15:8), H_4 (7:0)

0x00, 0x00, 0x00, 0x00

A_to_ipmix[5]

SDIN1-Left (Ch 1) A to Input Mixer 5 coefficient (default = 0)
U (31:28), A_5 (27:24), A_5 (23:16), A_5 (15:8), A_5 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[5]

SDIN1-Right (Ch 2) B to Input Mixer 5 coefficient (default = 0)
U (31:28), B_5 (27:24), B_5 (23:16), B_5 (15:8), B_5 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[5]

SDIN2-Left (Ch 3) C to Input Mixer 5 coefficient (default = 0)
U (31:28), C_5 (27:24), C_5 (23:16), C_5 (15:8), C_5 (7:0)

0x00, 0x00, 0x00, 0x00

0x45

D_to_ipmix[5]

SDIN2-Right (Ch 4) D to Input Mixer 5 coefficient (default = 0)
U (31:28), D_5 (27:24), D_5 (23:16), D_5 (15:8), D_5 (7:0)

0x00, 0x00, 0x00, 0x00

0x45

E_to_ipmix[5]

SDIN3-Left (Ch 5) E to Input Mixer 5 coefficient (default = 1)
U (31:28), E_5 (27:24), E_5 (23:16), E_5 (15:8), E_5 (7:0)

0x00, 0x80, 0x00, 0x00

F_to_ipmix[5]

SDIN3-Right (Ch 6) F to Input Mixer 5 coefficient (default = 0)
U (31:28), F_5 (27:24), F_5 (23:16), F_5 (15:8), F_5 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[5]

SDIN4-Left (Ch 7) G to Input Mixer 5 coefficient (default = 0)
U (31:28), G_5 (27:24), G_5 (23:16), G_5 (15:8), G_5 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[5]

SDIN4-Right (Ch 8) H to Input Mixer 5 coefficient (default = 0)
U (31:28), H_5 (27:24), H_5 (23:16), H_5 (15:8), H_5 (7:0)

0x00, 0x00, 0x00, 0x00

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

SUBADDRESS

TOTAL

BYTES

REGISTER

FIELDS

DESCRIPTION OF CONTENTS

DEFAULT STATE

A_to_ipmix[6]

SDIN1-Left (Ch 1) A to Input Mixer 6 coefficient (default = 0)
U (31:28), A_6 (27:24), A_6 (23:16), A_6 (15:8), A_6 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[6]

SDIN1-Right (Ch 2) B to Input Mixer 6 coefficient (default = 0)
U (31:28), B_6 (27:24), B_6 (23:16), B_6 (15:8), B_6 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[6]

SDIN2-Left (Ch 3) C to Input Mixer 6 coefficient (default = 0)
U (31:28), C_6 (27:24), C_6 (23:16), C_6 (15:8), C_6 (7:0)

0x00, 0x00, 0x00, 0x00

0x46

D_to_ipmix[6]

SDIN2-Right (Ch 4) D to Input Mixer 6 coefficient (default = 0)
U (31:28), D_6 (27:24), D_6 (23:16), D_6 (15:8), D_6 (7:0)

0x00, 0x00, 0x00, 0x00

0x46

E_to_ipmix[6]

SDIN3-Left (Ch 5) E to Input Mixer 6 coefficient (default = 0)
U (31:28), E_6 (27:24), E_6 (23:16), E_6 (15:8), E_6 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[6]

SDIN3-Right (Ch 6) F to Input Mixer 6 coefficient (default = 1)
U (31:28), F_6 (27:24), F_6 (23:16), F_6 (15:8), F_6 (7:0)

0x00, 0x80, 0x00, 0x00

G_to_ipmix[6]

SDIN4-Left (Ch 7) G to Input Mixer 6 coefficient (default = 0)
U (31:28), G_6 (27:24), G_6 (23:16), G_6 (15:8), G_6 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[6]

SDIN4-Right (Ch 8) H to Input Mixer 6 coefficient (default = 0)
U (31:28), H_6 (27:24), H_6 (23:16), H_6 (15:8), H_6 (7:0)

0x00, 0x00, 0x00, 0x00

A_to_ipmix[7]

SDIN1-Left (Ch 1) A to Input Mixer 7 coefficient (default = 0)

U (31:28), A_7 (27:24), A_7 (23:16), A_7 (15:8), A_7 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[7]

SDIN1-Right (Ch 2) B to Input Mixer 7 coefficient (default = 0)
U (31:28), B_7 (27:24), B_7 (23:16), B_7 (15:8), B_7 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[7]

SDIN2-Left (Ch 3) C to Input Mixer 7 coefficient (default = 0)
U (31:28), C_7 (27:24), C_7 (23:16), C_7 (15:8), C_7 (7:0)

0x00, 0x00, 0x00, 0x00

0x47

D_to_ipmix[7]

SDIN2-Right (Ch 4) D to Input Mixer 7 coefficient (default = 0)
U (31:28), D_7 (27:24), D_7 (23:16), D_7 (15:8), D_7 (7:0)

0x00, 0x00, 0x00, 0x00

0x47

E_to_ipmix[7]

SDIN3-Left (Ch 5) E to Input Mixer 7 coefficient (default = 0)
U (31:28), E_7 (27:24), E_7 (23:16), E_7 (15:8), E_7 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[7]

SDIN3-Right (Ch 6) F to Input Mixer 7 coefficient (default = 0)
U (31:28), F_7 (27:24), F_7 (23:16), F_7 (15:8), F_7 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[7]

SDIN4-Left (Ch 7) G to Input Mixer 7 coefficient (default = 1)
U (31:28), G_7 (27:24), G_7 (23:16), G_7 (15:8), G_7 (7:0)

0x00, 0x80, 0x00, 0x00

H_to_ipmix[7]

SDIN4-Right (Ch 8) H to Input Mixer 7 coefficient (default = 0)
U (31:28), H_7 (27:24), H_7 (23:16), H_7 (15:8), H_7 (7:0)

0x00, 0x00, 0x00, 0x00

A_to_ipmix[8]

SDIN1-Left (Ch 1) A to Input Mixer 8 coefficient (default = 0)
U (31:28), A_8 (27:24), A_8 (23:16), A_8 (15:8), A_8 (7:0)

0x00, 0x00, 0x00, 0x00

B_to_ipmix[8]

SDIN1-Right (Ch 2) B to Input Mixer 8 coefficient (default = 0)
U (31:28), B_8 (27:24), B_8 (23:16), B_8 (15:8), B_8 (7:0)

0x00, 0x00, 0x00, 0x00

C_to_ipmix[8]

SDIN2-Left (Ch 3) C to Input Mixer 8 coefficient (default = 0)
U (31:28), C_8 (27:24), C_8 (23:16), C_8 (15:8), C_8 (7:0)

0x00, 0x00, 0x00, 0x00

0x48

D_to_ipmix[8]

SDIN2-Right (Ch 4) D to Input Mixer 8 coefficient (default = 0)
U (31:28), D_8 (27:24), D_8 (23:16), D_8 (15:8), D_8 (7:0)

0x00, 0x00, 0x00, 0x00

0x48

E_to_ipmix[8]

SDIN3-Left (Ch 5) E to Input Mixer 8 coefficient (default = 0)
U (31:28), E_8 (27:24), E_8 (23:16), E_8 (15:8), E_8 (7:0)

0x00, 0x00, 0x00, 0x00

F_to_ipmix[8]

SDIN3-Right (Ch 6) F to Input Mixer 8 coefficient (default = 0)
U (31:28), F_8 (27:24), F_8 (23:16), F_8 (15:8), F_8 (7:0)

0x00, 0x00, 0x00, 0x00

G_to_ipmix[8]

SDIN4-Left (Ch 7) G to Input Mixer 8 coefficient (default = 0)
U (31:28), G_8 (27:24), G_8 (23:16), G_8 (15:8), G_8 (7:0)

0x00, 0x00, 0x00, 0x00

H_to_ipmix[8]

SDIN4-Right (Ch 8) H to Input Mixer 8 coefficient (default = 1)
U (31:28), H_8 (27:24), H_8 (23:16), H_8 (15:8), H_8 (7:0)

0x00, 0x80, 0x00, 0x00

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.16 Bass Management Registers (0x49 0x50)

Registers 0x49 0x50 provide configuration control for bass mangement.

Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as

a 32-bit word with the upper four bits not used.

Table 6-17. Bass Management Registers Format (0x49 0x50)

SUBADDRESS

TOTAL

BYTES

REGISTER

NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x49

ipmix_1_to_ch8

Input Mixer 1 to Ch 8 Mixer coefficient (default = 0)
U (31:28), ipmix18 (27:24), ipmix18 (23:16), ipmix18 (15:8),
ipmix18 (7:0)

0x00, 0x00, 0x00, 0x00

0x4A

ipmix_2_to_ch8

Input Mixer 1 to Ch 8 Mixer coefficient (default = 0)
U (31:28), ipmix28 (27:24), ipmix28 (23:16), ipmix28 (15:8),
ipmix28 (7:0)

0x00, 0x00, 0x00, 0x00

0x4B

ipmix_7_to_ch12 Input Mixer 7 to Ch 1 and Ch 2 Mixer coefficient (default = 0)

U (31:28), ipmix72 (27:24), ipmix72 (23:16), ipmix72 (15:8),
ipmix72 (7:0)

0x00, 0x00, 0x00, 0x00

0x4C

Ch7_bp_bq2

Ch 7 Biquad-2 By-pass coefficient (default = 0)
U (31:28), ch7_bp_bq2 (27:24), ch7_bp_bq2 (23:16),
ch7_bp_bq2 (15:8), ch7_bp_bq2 (7:0)

0x00, 0x00, 0x00, 0x00

0x4D

Ch7_bq2

Ch 7 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch6_bq2 (27:24), ch6_bq2 (23:16), ch6_bq2 (15:8),
ch6_bq2 (7:0)

0x00, 0x80, 0x00, 0x00

0x4E

ipmix_8_to_ch12 Ch 8 Biquad-2 Output to Ch1 Mixer and Ch2 Mixer coefficient

(default = 0)
U (31:28), ipmix8_12 (27:24), ipmix8_12 (23:16), ipmix8_12
(15:8), ipmix8_12 (7:0)

0x00, 0x00, 0x00, 0x00

0x4F

Ch8_bp_bq2

Ch 8 Biquad-2 By-pass coefficient (default = 0)
0U (31:28), ch8_bp_bq2 (27:24), ch8_bp_bq2 (23:16),

ch8_bp_bq2 (15:8), ch8_bp_bq2 (7:0)

0x00, 0x00, 0x00, 0x00

0x50

Ch8_bq2

Ch 8 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch7_bq2 (27:24), ch7_bq2 (23:16), ch7_bq2 (15:8),
ch7_bq2 (7:0)

0x00, 0x80, 0x00, 0x00

6.17 Biquad Filters Register (0x51 0x88)

Table 6-18. Biquad Filters Registers Format (0x51 0x88)

SUBADDRESS

TOTAL

BYTES

REGISTER NAME

DESCRIPTION OF CONTENTS

DEFAULT

STATE

0x51 0x57

20/Reg.

Ch1_bq[1] [7]

Ch 1 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x58 0x5E

20/Reg.

Ch2_bq[1] [7]

Ch 2 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x5F 0x65

20/Reg.

Ch3_bq[1] [7]

Ch 3 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x66 0x6C

20/Reg.

Ch4_bq[1] - [7]

Ch 4 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x6D 0x73

20/Reg.

Ch5_bq[1] - [7]

Ch 5 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x74 0x7A

20/Reg.

Ch6_bq[1] - [7]

Ch 6 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x7B 0x81

20/Reg.

Ch7_bq[1] - [7]

Ch 7 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

0x82 0x88

20/Reg.

Ch8_bq[1] - [7]

Ch 8 Biquads 1 7. See Table 6-19 for bit definition.

See Table 6-19

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as

a 32-bit word with the upper four bits not used.

Table 6-19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass)

DESCRIPTION

REGISTER FIELD CONTENTS

DEFAULT GAIN COEFFICIENT VALUES

DESCRIPTION

REGISTER FIELD CONTENTS

DECIMAL

HEX

Coefficient

U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)

1.0

0x00, 0x80, 0x00, 0x00

Coefficient

U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

6.18 Bass and Treble Bypass Register (0x89 0x90, Channels 1 - 8)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C,0x8D, 0x8E, 0x8F, and

0x90. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x800000

is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.

Table 6-20. Bass and Treble Bypass Register Format (0x89-0x90)

REGISTER NAME

TOTAL BYTES

CONTENTS

INITIALIZATION VALUE

Channel bass and
treble bypass

U 31:28), Bypass (27:24), Bypass (23:16), Bypass (15:8), Bypass (7:0)

0x00, 0x80, 0x00, 0x00

Channel bass and
treble inline

U (31:28), Inline (27:24), Inline (23:16), Inline (15:8), Inline (7:0)

0x00, 0x00, 0x00, 0x00

6.19 Loudness Registers (0x91 0x95)

Table 6-21. Loudness Registers Format (0x91 0x95)

SUBADDRESS

TOTAL

BYTES

REGISTER NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x91

Loudness Log2 Gain (LG)

U (31:28), LG (27:24), LG (23:16), LG (15:8), LG
(7:0)

0xFF, 0xC0, 0x00, 0x00

0x92

Loudness Log2 Offset
(LO)

U (31:24), U (23:16), LO (15:8), LO (7:0)

0x00, 0x00, 0x00, 0x00,

0x92

Loudness Log2 LO

LO (31:24), LO (23:16), LO (15:8), LO (7:0)

0x00, 0x00, 0x00, 0x00,

0x93

Loudness Gain (G)

U (31:28), G (27:24), G (23:16), G (15:8), G (7:0)

0x00, 0x00, 0x00, 0x00,

0x94

Loudness Offset Upper 16
bits (O)

U (31:24), U (23:16), O (15:8), O (7:0)

0x00, 0x00, 0x00, 0x00,

0x94

Loudness O Offset Lower
32 bits (O)

O (31:24), O (23:16), O (15:8), O (7:0)

0x00, 0x00, 0x00, 0x00,

Loudness Biquad (b0)

U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)

0x00, 0x00, 0xD5, 0x13,

Loudness Biquad (b1)

U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)

0x00, 0x00, 0x00, 0x00,

0x95

Loudness Biquad (b2)

U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)

0x0F, 0xFF, 0x2A, 0xED,

0x95

Loudness Biquad (a1)

U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)

0x00, 0xFE, 0x50, 0x45,

Loudness Biquad (a2)

U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)

0x0F, 0x81, 0xAA, 0x27

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.20 DRC1 Control (0x96, Channels 1-7)

Bits D31 D14 are Don't Care.

Table 6-22. DCR1 Control (0x96, Channels 1-7)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Unused bits

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

Unused bits

D15

D14

D13

D12

D11

D10

FUNCTION

Channel 1 (node j): No DRC

Channel 1 (node j): Pre-volume DRC

Channel 1 (node j): Post-volume DRC

Channel 1 (node j): No DRC

Channel 2 (node I): No DRC

Channel 2 (node I): Pre-volume DRC

Channel 2 (node I): Post-volume DRC

Channel 2 (node i): No DRC

Channel 3 (node m): No DRC

Channel 3 (node m): Pre-volume DRC

Channel 3 (node m): Post-volume DRC

Channel 3 (node m): No DRC

FUNCTION

Channel 4 (node n): No DRC

Channel 4 (node n): Pre-volume DRC

Channel 4 (node n): Post-volume DRC

Channel 4 (node n): No DRC

Channel 5 (node o): No DRC

Channel 5 (node o): Pre-volume DRC

Channel 5 (node o): Post-volume DRC

Channel 5 (node o): No DRC

Channel 6 (node p): No DRC

Channel 6 (node p): Pre-volume DRC

Channel 6 (node p): Post-volume DRC

Channel 6 (node p): No DRC

Channel 7 (node q): No DRC

Channel 7 (node q): Pre-volume DRC

Channel 7 (node q): Post-volume DRC

Channel 7 (node q): No DRC

6.21 DRC2 Control (0x97, Channel 8)

Table 6-23. DRC2 Control (0x97, Channel 8)

D31 D2

FUNCTION

Channel 8 (node r): No DRC

Channel 8 (node r): Pre-volume DRC

Channel 8 (node r): Post-volume DRC

Channel 8 (node r): No DRC

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.22 DRC1 Data Registers (0x98 0x9C)

DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7.

Table 6-24. DRC1 Data Registers

SUBADDRESS

TOTAL

BYTES

REGISTER NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x98

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Energy

U (31:28), E (27:24), E (23:16), E (15:8), E (7:0)

0x00, 0x00, 0x88, 0x3F

0x98

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1- Energy)

U (31:28), 1-E (27:24), 1-E (23:16), 1-E (15:8),
1-E (7:0)

0x00, 0x7F, 0x77, 0xC0

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Upper 16 bits
(T1)

U (31:24), U (23:16), T1 (15:8), T1 (7:0)

0x00, 0x00, 0x00, 0x00

0x99

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Lower 32 bits
(T1)

T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)

0x0B, 0x20, 0xE2, 0xB2

0x99

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Upper 16 bits (T2)

U (31:24), U (23:16), T2 (15:8), T2 (7:0)

0x00, 0x00, 0x00, 0x00

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Lower 32 bits (T2)

T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)

0x06, 0xF9, 0xDE, 0x58

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k0)

U (31:28), k0 (27:24), k0 (23:16), k0 (15:8),
k0 (7:0)

0x00, 0x40, 0x00, 0x00

0x9A

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k1)

U (31:28), k1 (27:24), k1 (23:16), k1 (15:8),
k1 (7:0)

0x0F, 0xC0, 0x00, 0x00

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k2)

U (31:28), k2 (27:24), k2 (23:16), k2 (15:8),
k2 (7:0)

0x0F, 0x90, 0x00, 0x00

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Upper 16 bits
(O1)

U (31:24), U (23:16), O1 (15:8), O1 (7:0)

0x00, 0x00, 0xFF, 0xFF

0x9B

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Lower 32 bits
(O1)

O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)

0xFF, 0x82, 0x30, 0x98

0x9B

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Upper 16 bits
(O2)

U (31:24), U (23:16), O2 (15:8), O2 (7:0)

0x00, 0x00, 0x00, 0x00

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Lower 32 bits
(O2)

O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)

0x01, 0x95, 0xB2, 0xC0

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Attack

U (31:28), A (27:24), A (23:16), A (15:8), A (7:0)

0x00, 0x00, 0x88, 0x3F

0x9C

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1- Attack)

U (31:28), 1-A (27:24), 1-A (23:16), 1-A (15:8),
1-A (7:0)

0x00, 0x7F, 0x77, 0xC0

0x9C

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Decay

U (31:28), D (27:24), D (23:16), D (15:8), D (7:0)

0x00, 0x00, 0x00, 0xAE

Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1- Decay)

U (31:28), 1-D (27:24), 1-D (23:16), 1-D (15:8),
1-D (7:0)

0x00, 0x7F, 0xFF, 0x51

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.23 DRC2 Data Registers (0x9D 0xA1)

DRC2 applies to channel 8.

Table 6-25. DRC2 Data Registers

SUBADDRESS

TOTAL

BYTES

REGISTER NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

Channel 8 DRC2 Energy

U (31:28), E (27:24), E (23:16), E (15:8), E (7:0)

0x00, 0x00, 0x88, 0x3F

0x9D

Channel 8 DRC2 (1- Energy)

U (31:28), 1-E (27:24), 1-E (23:16), 1-E (15:8),
1-E (7:0)

0x00, 0x7F, 0x77, 0xC0

Channel 8 DRC2 Threshold
Upper 16 bits (T1)

U (31:24), U (23:16), T1 (15:8), T1 (7:0)

0x00, 0x00, 0x00, 0x00

0x9E

Channel 8 DRC2 Threshold
Lower 32 bits (T1)

T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)

0x0B, 0x20, 0xE2, 0xB2

0x9E

Channel 8 DRC2 Threshold
Upper 16 bits (T2)

U (31:24), U (23:16), T2 (15:8), T2 (7:0)

0x00, 0x00, 0x00, 0x00

Channel 8 DRC2 Threshold
Lower 32 bits (T2)

T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)

0x06, 0xF9, 0xDE, 0x58

Channel 8 DRC2 slope (k0)

U (31:28), k0 (27:24), k0 (23:16), k0 (15:8),
k0 (7:0)

0x00, 0x40, 0x00, 0x00

0x9F

Channel 8 DRC2 slope (k1)

U (31:28), k1 (27:24), k1 (23:16), k1 (15:8),
k1 (7:0)

0x0F, 0xC0, 0x00, 0x00

Channel 8 DRC2 slope (k2)

U (31:28), k2 (27:24), k2 (23:16), k2 (15:8),
k2 (7:0)

0x0F, 0x90, 0x00, 0x00

Channel 8 DRC2 Offset 1
Upper 16 bits (O1)

U (31:24), U (23:16), O1 (15:8), O1 (7:0)

0x00, 0x00, 0xFF, 0xFF,

0xA0

Channel 8 DRC2 Offset 1
Lower 32 bits (O1)

O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)

0xFF, 0x82, 0x30, 0x98

0xA0

Channel 8 DRC2 Offset 2
Upper 16 bits (O2)

U (31:24), U (23:16), O2 (15:8), O2 (7:0)

0x00, 0x00, 0x00, 0x00

Channel 8 DRC2 Offset 2
Lower 32 bits (O2)

O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)

0x01, 0x95, 0xB2, 0xC0

Channel 8 DRC2 Attack

U (31:28), A (27:24), A (23:16), A (15:8), A (7:0)

0x00, 0x00, 0x88, 0x3F

0xA1

Channel 8 DRC2 (1- Attack)

U (31:28), 1-A (27:24), 1-A (23:16), 1-A (15:8),
1-A (7:0)

0x00, 0x7F, 0x77, 0xC0

0xA1

Channel 8 DRC2 Decay

U (31:28), D (27:24), D (23:16), D (15:8), D (7:0)

0x00, 0x00, 0x00, 0xAE

Channel 8 DRC2 (1- Decay)

U (31:28), 1-D (27:24), 1-D (23:16), 1-D (15:8),
1-D (7:0)

0x00, 0x7F, 0xFF, 0x51

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.24 DRC Bypass Registers (0xA2 0xA9)

DRC bypass/inline for channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xA2, 0xA3, 0xA4,

0xA5,0xA6, 0xA7, 0xA8, and 0xA9. 8-bytes are written for each channel. Each gain coefficient is in 28-bit

(5.23) format so 0x00800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper 4

bits not used.

To enable DRC for a given channel (with unity gain), bypass = 0x00000000 and inline = 0x00800000.

To disable DRC for a given channel, bypass = 0x00800000 and inline = 0x00000000.

Table 6-26. DRC Bypass Registers Format (0xA2-0xA9)

REGISTER NAME

TOTAL

BYTES

CONTENTS

INITIALIZATION

VALUE

Channel bass DRC bypass

U (31:28), bypass (27:24), bypass (23:16), bypass (15:8), bypass (7:0) 0x00, 0x80, 0x00, 0x00

Channel DRC inline

U (31:28), inline (27:24), inline (23:16), inline (15:8), inline (7:0)

0x00, 0x00, 0x00, 0x00

6.25 8x2 Output Mixer Registers (0xAA 0xAF)

Output mixers for channels 16 map to registers 0xAA 0xAF.

Total data per register is 8 bytes.

Table 6-27. Output Mixer Control Register Format (Upper 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-28. Output Mixer Control (Lower 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

6.26 8x3 Output Mixer Registers (0xB0 0xB1)

Output mixers for channels 7 and 8 map to registers 0xB0 and 0xB1.

Total data per register is 12 bytes.

Table 6-29. Output Mixer Control (Upper 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-30. Output Mixer Control (Middle 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

Table 6-31. Output Mixer Control (Lower 4 Bytes)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Select channel 1 to output mixer

Select channel 2 to output mixer

Select channel 3 to output mixer

Select channel 4 to output mixer

Select channel 5 to output mixer

Select channel 6 to output mixer

Select channel 7 to output mixer

Select channel 8 to output mixer

G27

G26

G25

G24

Selected channel gain (upper 4 bits)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

G23

G22

G21

G20

G19

G18

G17

G16

Selected channel gain (continued)

D15

D14

D13

D12

D11

D10

FUNCTION

G15

G14

G13

G12

G11

G10

Selected channel gain (continued)

FUNCTION

Selected channel gain (lower 8 bits)

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.27 Volume Biquad Register (0xCF)

Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as

a 32-bit word with the upper four bits not used.

Table 6-32. Volume Biquad Register Format (Default = All-pass)

DESCRIPTION

REGISTER FIELD CONTENTS

DEFAULT GAIN COEFFICIENT VALUES

DESCRIPTION

REGISTER FIELD CONTENTS

DECIMAL

HEX

Coefficient

0U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)

1.0

0x00, 0x80, 0x00, 0x00

Coefficient

U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

0U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

Coefficient

U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)

0.0

0x00, 0x00, 0x00, 0x00

6.28 Volume Treble and Bass Slew Rates (0xD0)

Table 6-33. Volume Gain Update Rate (Slew Rate)

D31-D10

FUNCTION

512 step update at 4 Fs, 42.6 ms at 48 kHz

1024 step update at 4 Fs, 85.3 ms at 48 kHz

2048 step update at 4 Fs, 170 ms at 48 kHz

Table 6-34. Treble and Bass Gain Step Size (Slew Rate)

FUNCTION

No operation

Minimum rate Updates every 0.083 ms (every LRCLK at 48 kHz)

Update ever 0.67 ms (32 LRCLKs at 48 kHz)

Default rate - Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the
maximum constant time that can be set for all sample rates.

Minimum rate Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)

6.29 Volume Registers (0xD1 - 0xD9)

Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and

0xD8.

Master volume is mapped into register 0xD9.

Bits D31 - D12 are Don't Care.

Table 6-35. Volume Registers

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Unused bits

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

Unused bits

D15

D14

D13

D12

D11

D10

FUNCTION

V11

V10

Volume

FUNCTION

Volume

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-36. Master and Individual Volume Controls

VOLUME INDEX (H)

GAIN/INDEX

EXPECTED

ACTUAL

001

17.75

17.81

002

17.5

17.56

003

17.25

17.31

004

17.06

005

16.75

16.81

006

16.5

16.56

007

16.25

16.31

008

16.05

009

15.75

15.8

00A

15.5

15.55

00B

15.25

15.3

00C

15.05

00D

14.75

14.8

00E

14.5

14.55

00F

14.25

14.3

010

14.05

044

045

0.75

046

0.5

047

0.25

048

049

-0.25

04A

-0.5

04B

-0.75

04C

-1

240

-126

-126.43

241

-126.25

-126.68

-126.99

242

-126.5

-126.93

-126.99

243

-126.75

-127.19

-127.59

244

-127

-127.44

-127.59

245

Mute

3FF

Mute

6.30 Bass Filter Set Register (0xDA)

Bits D31-D27, D23-D19, D15-D11, and D7-D3 are Don't Care.

Table 6-37. Channel 8 Sub Woofer

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

No change

Bass filter set 1

Bass filter set 2

Bass filter set 3

Bass filter set 4

Bass filter set 5

Illegal

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-38. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and

Left Surround in Eight Channel Configuration)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

No change

Bass filter set 1

Bass filter set 2

Bass filter set 3

Bass filter set 4

Bass filter set 5

Illegal

Table 6-39. Channel 4 and 3 (Right and Left Rear)

D15

D14

D13

D12

D11

D10

FUNCTION

No change

Bass filter set 1

Bass filter set 2

Bass filter set 3

Bass filter set 4

Bass filter set 5

Illegal

Table 6-40. Channel 7, 2, 1 (Center, Right Front, and Left Front)

FUNCTION

No change

Bass filter set 1

Bass filter set 2

Bass filter set 3

Bass filter set 4

Bass filter set 5

Illegal

6.31 Bass Filter Index Register (0xDB)

Index values above 0x24 are invalid.

Table 6-41. Bass Filter Index Register

C SUBADDRESS

TOTAL BYTES

REGISTER NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0xDB

Bass filter index
(BFI)

Ch8_BFI (31:24), Ch65_BFI (23:16), Ch43_BFI
(15:8), Ch721_BFI (7:0)

0x12, 0x12, 0x12, 0x12,

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-42. Bass Filter Index Table

TREBLE INDEX

VALUE

ADJUSTMENT

(DB)

TREBLE INDEX

VALUE

ADJUSTMENT

(DB)

0x00

+18

0x13

-1

0x01

+17

0x14

-2

0x02

+16

0x15

-3

0x03

+15

0x16

-4

0x04

+14

0x17

-5

0x05

+13

0x18

-6

0x06

+12

0x19

-7

0x07

+11

0x1A

-8

0x08

+10

0x1B

-9

0x09

0x1C

-10

0x0A

0x1D

-11

0x0B

0x1E

-12

0x0C

0x1F

-13

0x0D

0x20

-14

0x0E

0x21

-15

0x0F

0x22

-16

0x10

0x23

-17

0x11

0x24

-18

0x12

6.32 Treble Filter Set Register (0xDC)

Bits D31-D27 are Don't Care.

Table 6-43. Channel 8 Sub Woofer

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

No change

Treble filter set 1

Treble filter set 2

Treble filter set 3

Treble filter set 4

Treble filter set 5

Illegal

Table 6-44. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right

and Left Surround in Eight Channel Configuration)

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

No change

Treble filter set 1

Treble filter set 2

Treble filter set 3

Treble filter set 4

Treble filter set 5

Illegal

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

Table 6-45. Channel 4 and 3 (Right and Left Rear)

D15

D14

D13

D12

D11

D10

FUNCTION

No change

Treble filter set 1

Treble filter set 2

Treble filter set 3

Treble filter set 4

Treble filter set 5

Illegal

Table 6-46. Channel 7, 2, 1 (Center, Right Front, and Left Front)

FUNCTION

No change

Treble filter set 1

Treble filter set 2

Treble filter set 3

Treble filter set 4

Treble filter set 5

Illegal

6.33 Treble Filter Index (0xDD)

Index values above 0x24 are invalid.

Table 6-47. Treble Filter Index Register

SUBADDRESS

TOTAL BYTES

REGISTER

NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0xDD

Treble filter index (TFI)

Ch8_TFI (31:24), Ch65_TFI (23:16), Ch43_TFI (15:8),
Ch721_TFI (7:0)

0x12,0x12,0x12,0x12

Table 6-48. Treble Filter Index

TREBLE INDEX VALUE

ADJUSTMENT (DB)

TREBLE INDEX VALUE

ADJUSTMENT (DB)

0x00

+18

0x13

-1

0x01

+17

0x14

-2

0x02

+16

0x15

-3

0x03

+15

0x16

-4

0x04

+14

0x17

-5

0x05

+13

0x18

-6

0x\06

+12

0x19

-7

0x07

+11

0x1A

-8

0x08

+10

0x1B

-9

0x09

0x1C

-10

0x0A

0x1D

-11

0x0B

0x1E

-12

0x0C

0x1F

-13

0x0D

0x20

-14

0x0E

0x21

-15

0x0F

0x22

-16

0x10

0x23

-17

0x11

0x24

-18

0x12

Serial Control Interface Register Definitions

SLES115 -- August 2004

TAS5518

6.34 AM Mode Register (0xDE)

Bits D31-D21 are Don't Care.

Table 6-49. AM Mode Register

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Unused bits

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

AM mode disabled

AM mode enabled

Select sequence 1

Select sequence 2

Select sequence 3

Select sequence 4

IF frequency 455

IF frequency 262.5

Use BCD tuned frequency

Use binary tuned frequency

Table 6-50. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)

D15

D14

D13

D12

D11

D10

FUNCTION

BCD frequency (1000s kHz)

BCD frequency (100s kHz)

Default value

FUNCTION

BCD frequency (10s kHz)

BCD frequency (1s kHz)

Default value

Table 6-51. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)

D15

D14

D13

D12

D11

D10

FUNCTION

B10

Binary frequency (upper 3 bits)

Default value

FUNCTION

Binary frequency (lower 8 bits)

Default value

6.35 PSVC Range Register (0xDF)

Bits D31-D2 are zero.

Table 6-52. PSVC Range Register

D31 D2

FUNCTION

12.04-dB control range for PSVC

18.06-dB control range for PSVC

24.08-dB control range for PSVC

Ignore - retain last value

RIGHT BACK
SURROUND
SPEAKER
OUTPUT

LEFT BACK
SURROUND
SPEAKER
OUTPUT

SUBWOOFER
SPEAKER
OUTPUT

CENTER
SPEAKER
OUTPUT

RIGHT
SURROUND
SPEAKER
OUTPUT

LEFT
SURROUND
SPEAKER
OUTPUT

LEFT
SPEAKER
OUTPUT

TAS5518 Example Application Schematic

RIGHT
SPEAKER
OUTPUT

(Circuit is Subject To Change Without Notice)

LINE OUTPUT

HEADPHONE OUTPUT

CH1 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH4 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH7 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH5 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH8 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

PSU and Interface Logic

+3.

3
V

+5.

0
V

GVDD

V-

HBRIDGE

/RESET

PSVC_MCPU

/RESET_5518

/OTW_TAS5121

/OTW

/BKND_ERR

/SD1_TAS5121

/SD1

CONF_SEL

/VALID

/VALID_CH5+CH6

/LINE_OUT_ENABLE

/SD2

/SD2_TAS5121

PSVC

CH3 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH2 TAS5121 H-Bridge Output Stage

/SHUTDOWN_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

CH6 TAS5121 H-Bridge Output Stage

/SD1_TAS5121

PWM_P

PWM_M

/VALID

OUT_1

OUT_2

GVDD

V-HBRIDGE

/TEMP_WARNING

Left + Right Line Out

2 Channel Line Out (TLV272)

+3.3V

+5.0V

PWM_P_L

PWM_M_L

PWM_P_R

PWM_M_R

OUT_L

OUT_R

/OE

Left + Right Headphone

2 Channel Headphone Design (TPA112)

PWM_HPP_R

PWM_HPM_R

OUT_L

OUT_R

+5.0V

PWM_HPP_L

PWM_HPM_L

OUT_GND

+3.3V

GND

+3.3V

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

V-HBRIDGE

GVDD

+3.3V

GND

+3.3V

GND

GVDD

V-HBRIDGE

+5.0V +3.3V

GND

+5.0V

GND

+3.3V

C25

220nF

J600

R21

C14

100nF

C13

10nF

C17

100nF

C20

100nF

R13

3.30R

X10

13.5MHz

J100

J400

J700

J800

C15

100nF

R12

C11

100nF

C10

10nF

C29

100nF

R18

J500

R20

22.0R

R10

200R

C28

15pF

R11

200R

C27

15pF

J300

C23

10uF

C21

100nF

C18

1nF

C26

10uF

C16

10uF

C12

100nF

J200

C24

100nF

TAS5518

VRA_PLL

PLL_FLT_RET

PLL_FLTM

PLL_FLTP

AVSS

VRD_PLL

AVSS_PLL

AVDD_PLL

VBGAP

RESET

HP_SEL

PDN

MUTE

DVDD

DVSS

VR_DPLL

OSC_CAP

XTL_O

XTL_I

RESERVED

SDA

SCL

LRCLK

SCLK

SDIN4

SDIN3

SDIN2

SDIN1

PSVC

VR_PWM

PWM_P_4

PWM_M_4

PWM_P_3

PWM_M_3

PWM_P_2

PWM_M_2

PWM_P_1

PWM_M_1

VAILD

DVSS

BKND_ERR

DVDD

DVSS

VR_DIG

RESERVED

MCL

M_HPPR

HPMR

M_HPPL

HPML

M_P_6

M_P_5

DVDD_PW

DVSS_PW

M_P_8

M_P_7

RESERVED

R14

C22

470nF

C19

10uF

J950

Phono socket

J951

Phono socket

J900

Mini-Jack (3.5mm)

/VALID_CH5+CH6

/VALID

/RESET_5518

/RESET

/BKND_ERR

/OTW_TAS5121

/OTW

/SD1_TAS5121

/SD1

/SD2_TAS5121

/SD2

/VALID_CH5+CH6

/VALID

CONF_SEL

/VALID_CH5+CH6

/SD1_TAS5121

/OTW_TAS5121

/SD1_TAS5121

/OTW_TAS5121

/SD2_TAS5121

/OTW_TAS5121

/SD2_TAS5121

/OTW_TAS5121

/SD1_TAS5121

/OTW_TAS5121

/SD2_TAS5121

/OTW_TAS5121

/SD2_TAS5121

/OTW_TAS5121

/SD2_TAS5121

/OTW_TAS5121

PSVC

PSVC_MCPU

/LINE_OUT_ENABLE

/BKND_ERR

/HP_SEL

/PDN

/VALID

/MUTE

MCLK

/RESET_5518

SCL

PSVC

SDA

LRCLK

SDIN4

SCLK

SDIN3

SDIN2

SDIN1

/LINE_OUT_ENABLE

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TAS5518

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TAS5518