TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
QUAD DIFFERENTIAL PECL RECEIVERS
FEATURES
D
Low-Voltage Functional Replacements for
the Agere BRF1A, BRF2A, BRS2A, and
BRS2B
D
Pin-Equivalent to General Trade 26LS32
Devices
D
High-Input Impedance Approximately 8 k
D
3.5-ns Maximum Propagation Delay
D
TB3R1 Provides 50-mV Hysteresis
D
TB3R2 With -125-mV Threshold Offset for
Preferred State Output
D
-0.5 V to 5.2 V Common Mode Range
D
Single 3.3 V
10% Supply
D
Slew Rate Limited (0.5 ns min 80% to 20%)
D
TB3R2 Output Defaults to Logic 1 When
Inputs Left Open or Shorted to V
CC
or GND
D
ESD Protection HBM > 3 kV, CDM > 2 kV
D
Operating Temperature Range: -40
5
C to 85
5
C
D
Available SOIC (D) Package
APPLICATIONS
D
Digital Data or Clock Transmission Over
Balanced Lines
DESCRIPTION
These quad differential receivers accept digital data over
balanced transmission lines. They translate differential
input logic levels to TTL output logic levels.
The TB3R1 is a pin- and function-compatible replacement
for the Agere Systems BRF1A and BRF2A; it includes
3-kV HBM and 2-kV CDM ESD protection.
The TB3R2 is a pin- and function-compatible replacement
for the Agere Systems BRS2A and BRS2B and
incorporates a -125-mV receiver input offset, preferred
state output, 3-kV HBM and 2-kV CDM ESD protection.
The TB3R2 preferred state feature places the output in the
high state when the inputs are open, shorted to ground, or
shorted to the power supply.
The power-down loading characteristics of the receiver
input circuit are approximately 8 k
relative to the power
supplies; hence they do not load the transmission line
when the circuit is powered down.
The package for these differential line receivers is the
16-pin SOIC (D) package.
The enable inputs of this device include internal pullup
resistors of approximately 40 k
that are connected to V
CC
to ensure a logical high level input if the inputs are open
circuited.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI
AI
AO
E1
BO
BI
BI
GND
VCC
DI
DI
DO
E2
CO
CI
CI
D PACKAGE
(TOP VIEW)
FUNCTIONAL DIAGRAM
AI
AO
BO
CO
DO
AI
AI
BI
BI
C1
C1
D1
D1
D1
E2
E1
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright
2003, Texas Instruments Incorporated
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
2
These devices have limited built-in ESD protection. The
leads should be shorted together or the device placed in
conductive foam during storage or handling to prevent
electrostatic damage to the MOS gates.
Table 1. Enable Truth Table
E1
E2
CONDITION
0
0
Active
1
0
Active
0
1
Disabled
1
1
Disabled
ORDERING INFORMATION
PART NUMBER
PART MARKING
PACKAGE
STATUS
TB3R1D
TB3R1
SOIC
Production
TB3R2D
TB3R2
SOIC
Production
POWER DISSIPATION RATINGS
PACKAGE
CIRCUIT
BOARD MODEL
POWER RATING
TA
25
C
THERMAL RESISTANCE,
JUNCTION-TO-AMBIENT
WITH NO AIR FLOW
DERATING
FACTOR(1)
TA
25
C
POWER RATING
TA = 85
C
D
Low-K(2)
763 mW
131.1
C/W
7.6 mW/
C
305 mW
D
High-K(3)
1190 mW
84.1
C/W
11.9 mW/
C
475 mW
DW
Low-K(2)
831 mW
120.3
C/W
8.3 mW/
C
332 mW
DW
High-K(3)
1240 mW
80.8
C/W
12.4 mW/
C
494 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
(2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
PACKAGE
VALUE
UNIT
JB
Junction-to-Board
D
47.5
C/W
JB
Junction-to-Board
Thermal Resistance
DW
53.7
C/W
JC
Junction-to-Case
D
44.2
C/W
JC
Junction-to-Case
Thermal Resistance
DW
47.1
C/W
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VCC
0 V to 6 V
Magnitude of differential bus (input) voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI|
6.5 V
ESD
Human Body Model(2)
All pins
3 kV
ESD
Charged-Device Model(3)
All pins
2 kV
Continuous power dissipation
See Dissipation Rating Table
Storage temperature, Tstg
-65
C to 150
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
3
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
Bus pin input voltage, VAI, VAI, VBI, VBI, VCI, VCI, VDI, VDI
-0.6(1)
5.3
V
Magnitude of differential input voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI|
0.1
5
V
Operating free-air temperature, TA
-40
85
C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise
noted.
DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC
Supply current(1)
Outputs disabled
34
mA
ICC
Supply current(1)
Outputs enabled
32
mA
(1) Current is dc power draw as measured through GND pin and does not include power delivered to load.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOL
Output low voltage
VCC = 3 V,
IOL = 8 mA
0.4
V
VOH
Output high voltage
VCC = 3 V,
IOH = 400
A
2.4
V
VIL
Low level enable input voltages(1)
VCC = 3.6 V
0.8
V
VIH
High level enable input voltages(1)
VCC = 3.6 V
2
V
VIK
Enable input clamp voltage
VCC = 3 V,
II = 5 mA
1(4)
V
VTH+
Positive-going differential input threshold voltage(1),
x = A, B, C, or D
TB3R1
100
mV
VTH+
Positive-going differential input threshold voltage(1),
(Vxl - Vxl)
x = A, B, C, or D
TB3R2(2)
-50
mV
VTH-
Negative-going differential input threshold voltage(1),
x = A, B, C, or D
TB3R1
100(4)
mV
VTH-
Negative-going differential input threshold voltage(1),
(Vxl - Vxl)
x = A, B, C, or D
TB3R2(2)
200(4)
mV
VHYST
Differential input threshold voltage hysteresis,
(VTH+ - VTH_)
TB3R1
50
mV
IOZL
Output off-state current, (High-Z)
VCC = 3.6 V
VO = 0.4 V
20(4)
A
IOZH
Output off-state current, (High-Z)
VCC = 3.6 V
VO = 2.4 V
20
A
IOS
Output short circuit current(3)
VCC = 3.6 V
100(4)
mA
IIL
Enable input low current
VCC = 3.6 V,
VIN = 0.4 V
400(4)
A
IIH
Enable input high current
VCC = 3.6 V
VIN = 2.7 V
20
A
IIH
Enable input reverse current
VCC = 3.6 V
VIN = 3.6 V
100
A
IIL
Differential input low current
VCC = 3.6V,
VIN = 1.2 V
2(4)
mA
IIH
Differential input high current
VCC= 3.6V,
VIN = 5.3 V
1
mA
RO
Output resistance
20
(1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(2) Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs be tied to the
positive power supply. No external series resistor is required.)
(3) Test must be performed one lead at a time to prevent damage to the device.
(4) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data
sheet.
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
4
SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
CL = 0 pF(1), See Figure 2 and Figure 4
1.8
3.5
ns
tPHL
Propagation delay time, high-to-low-level output
CL = 0 pF(1), See Figure 2 and Figure 4
1.8
3.5
ns
tPLH
Propagation delay time, low-to-high-level output
CL = 15 pF, See Figure 2 and Figure 4
2.3
4
ns
tPHL
Propagation delay time, high-to-low-level output
CL = 15 pF, See Figure 2 and Figure 4
2.3
4
ns
tPHZ
Output disable time,
high-level-to-high-impedance output(3)
CL = 5 pF See Figure 3 and Figure 5
4.4
12
ns
tPLZ
Output disable time, low-level-to-high-impedance
output(3)
CL = 5 pF See Figure 3 and Figure 5
3.3
12
ns
tskew1
Pulse width distortion, |tPHL - tPLH|
CL = 10 pF,
See Figure 2 and Figure 4
0.7
ns
tskew1
Pulse width distortion, |tPHL - tPLH|
CL = 150 pF,
See Figure 2 and Figure 4
4
ns
tskew1p-p Part-to-part output waveform skew(2)
CL = 10 pF, TA = 75
C,
See Figure 2 and Figure 4
0.8
1.4
ns
tskew1p-p Part-to-part output waveform skew(2)
CL = 10 pF, TA = -40
C to 85
C,
See Figure 2 and Figure 4
1.5
ns
tskew
Same part output waveform skew(2)
CL = 10 pF, See Figure 2 and Figure 4
0.3
ns
tPZH
Output enable time, high-impedance-to-high-level
output(3)
CL = 10 pF, See Figure 3 and Figure 4
6
12
ns
tPZL
Output enable time, high-impedance-to-low-level
output(3)
CL = 10 pF, See Figure 3 and Figure 4
4
12
ns
tTLH
Rise time (20%-80%)
CL = 10 pF, See Figure 2 and Figure 4
0.5
2
ns
tTHL
Fall time (80%-20%)
CL = 10 pF, See Figure 2 and Figure 4
0.5
2
ns
(1) The propagation delay values with a 0 pF load are based on design and simulation.
(2) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the same
test circuits.
(3) See Table 1.
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
5
TYPICAL CHARACTERISTICS
0
2
4
6
8
0
50
100
150
200
t pd
- Propagation Delay T
ime - ns
TYPICAL PROPAGATION DELAY
vs
LOAD CAPACITANCE
CL - Load Capacitance - pF
tPHL
tPLH
TA = 25
5
C
VCC = 3.3 V
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0 pF load condition.
The incremental increase in delay between the 0 pF load condition and the actual total load capacitance represents the extrinsic, or external
delay contributed by the load.
Figure 1. Typical Propagation Delay vs Load Capacitance at 25
5
C
OUTPUT
3.7 V
2.7 V
3.2 V
VOH
V OL
1.5 V
tTHL
tPHL
tPLH
tTLH
20%
80%
20%
80%
INPUT
INPUT
Figure 2. Receiver Propagation Delay Times
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
6
OUTPUT
2.4 V
0.4 V
1.5 V
t
PHZ
tPZH
tPLZ
tPZL
0.2 V
0.2 V
0.2 V
0.2 V
0.4 V
2.4 V
1.5 V
E1(1)
E1(2)
VOH
VOL
(1) E2 = 1 while E1 changes states.
(2) E1 = 0 while E2 changes states.
Figure 3. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the
data transmission driver devices are measured with the following output load circuits.
TO OUTPUT
C
L
OF DEVICE
UNDER TEST
C
L
includes test-fixture and probe capacitance.
Figure 4. Receiver Propagation Delay Time and Enable Time (t
PZH
, t
PZL
) Test Circuit
TO OUTPUT
OF DEVICE
UNDER TEST
C
L
500
W
1.5 V
C
L
includes test-fixture and probe capacitance.
Figure 5. Receiver Disable Time (t
PHZ
, t
PLZ
) Test Circuit
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
7
TYPICAL CHARACTERISTICS
Figure 6
1
2
3
4
5
-50
0
50
100
150
Max
Nom
Min
- Low-to-High Propagation Delay - ns
LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
t PLH
TA
- Free-Air Temperature -
5
C
VCC = 3.3 V
Figure 7
1
2
3
4
5
-50
0
50
100
150
- High to Low Propagation Delay - ns
HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
t
PHL
VCC = 3.3 V
Nom
Min
Max
TA - Free-Air Temperature -
5
C
Figure 8
0
0.5
1
1.5
2
2.5
3
3.5
-50
0
50
100
150
MINIMUM V
OH
AND MAXIMUM V
OL
vs
FREE-AIR TEMPERATURE
VCC = 3.3 V
VOH min
VOL max
- Output V
oltage - V
V
O
TA - Free-Air Temperature -
C
Figure 9
15
20
25
30
35
-50
0
50
100
150
TYPICAL AND MAXIMUM I
CC
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature -
5
C
I CC
- Supply Current - mA
ICC max at VCC = 3.6 V
ICC Typical at VCC = 3.3 V
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
8
APPLICATION INFORMATION
POWER DISSIPATION
The power dissipation rating, often listed as the package
dissipation rating, is a function of the ambient temperature,
T
A
, and the airflow around the device. This rating
correlates with the device's maximum junction
temperature, sometimes listed in the absolute maximum
ratings tables. The maximum junction temperature
accounts for the processes and materials used to fabricate
and package the device, in addition to the desired life
expectancy.
There are two common approaches to estimating the
internal die junction temperature, T
J
. In both of these
methods, the device internal power dissipation P
D
needs
to be calculated This is done by totaling the supply
power(s) to arrive at the system power dissispation:
V
Sn
I
Sn
and then subtracting the total power dissipation of the
external load(s):
(V
Ln
I
Ln
)
The first T
J
calculation uses the power dissipation and
ambient temperature, along with one parameter:
JA
, the
junction-to-ambient thermal resistance, in degrees
Celsius per watt.
The product of P
D
and
JA
is the junction temperature rise
above the ambient temperature. Therefore:
T
J
+
T
A
)
P
D
Q
JA
Note that
JA
is highly dependent on the PCB on which the
device is mounted, and on the airflow over the device and
PCB. JEDEC/EIA has defined standardized test
conditions for measuring
JA
. Two commonly used
conditions are the low-K and the high-K boards, covered
by EIA/JESD51-3 and EIA/JESD51-7 respectively.
Figure 10 shows the low-K and high-K values of
JA
versus air flow for this device and its package options.
40
60
80
100
120
140
0
100
200
300
400
500
The
r
m
a
l
Impe
da
nc
e
-
C
/
W
D, Low-K
D, High-K
DW, High-K
DW, Low-K
Figure 10. Thermal Impedance vs Air Flow
The standardized
JA
values may not accurately
represent the conditions under which the device is used.
This can be due to adjacent devices acting as heat sources
or heat sinks, to nonuniform airflow, or to the system PCB
having significantly different thermal characteristics than
the standardized test PCBs. The second method of
system thermal analysis is more accurate. This calculation
uses the power dissipation and ambient temperature,
along with two device and two system-level parameters:
D
JC
, the junction-to-case thermal resistance, in
degrees Celsius per watt
D
JB
, the junction-to-board thermal resistance, in
degrees Celsius per watt
D
CA
, the case-to-ambient thermal resistance, in
degrees Celsius per watt
D
BA
, the board-to-ambient thermal resistance, in
degrees Celsius per watt.
In this analysis, there are two parallel paths, one through
the case (package) to the ambient, and another through
the device to the PCB to the ambient. The system-level
junction-to-ambient thermal impedance,
JA(S)
, is the
equivalent parallel impedance of the two parallel paths:
T
J
+
T
A
)
P
D
Q
JA(S)
where
Q
JA(S)
+
Q
JC
)Q
CA
Q
JB
)Q
BA
Q
JC
)Q
CA
)Q
JB
)Q
BA
TB3R1
TB3R2
SLLS587 - NOVEMBER 2003
www.ti.com
9
The device parameters
JC
and
JB
account for the
internal structure of the device. The system-level
parameters
CA
and
BA
take into account details of the
PCB construction, adjacent electrical and mechanical
components, and the environmental conditions including
airflow. Finite element (FE), finite difference (FD), or
computational fluid dynamics (CFD) programs can
determine
CA
and
BA
. Details on using these programs
are beyond the scope of this data sheet, but are available
from the software manufacturers.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
PDF 
ZIP