TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D AUGUST 1987 REVISED OCTOBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Reliable Silicon-Gate CMOS Technology
D
Low Power Consumption
Operating Mode . . . 80 mW
Power-Down Mode . . . 5 mW
D
-Law Coding
D
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
D
No External Components Needed for
Sample, Hold, and Autozero Functions
D
Precision Internal Voltage Reference
D
Single Chip Contains A/D, D/A, and
Associated Filters
description
The TCM29C18, TCM29C19, TCM129C18, and
TCM129C19 are low-cost single-chip PCM
codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices
incorporate both the A/D and D/A functions, an
antialiasing filter (A/D), and a smoothing filter
(D/A). They are ideal for use with the TMS320
DSP family members, particularly those featuring
a serial port such as the TMS32020, TMS32011,
and TMS320C25.
Primary applications include:
Digital encryption systems
Digital voice-band data storage systems
Digital signal processing
These devices are designed to perform encoding of analog input signals (A/D conversion) and decoding of
digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital
signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding,
and smoothing after decoding.
The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of 0
C to 70
C.
The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of
40
C to 85
C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VBB
PWRO +
PWRO
PDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLG IN
ANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLK
DW OR N PACKAGE
(TOP VIEW)
FEATURES TABLE
Number of Pins:
16
Fixed Mode:
2.048 MHz (TCM29C18, TCM129C18),
1.536 MHz (TCM29C19, TCM129C19)
Coding Law:
-Law
Variable Mode:
64 kHz to 2.048 MHz
8-Bit Resolution
12-Bit Dynamic Range
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D AUGUST 1987 REVISED OCTOBER 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Buffer
PWRO+
PWRO
GSX
ANLG IN
Transmit Section
Receive Section
Control Section
PDN
Control
Logic
DCLKR
PCM IN
Register
Input
Digital-
to-Analog
Control
Logic
Reference
Sample
and Hold
and DAC
Analog-
to-Digital
Control
Logic
Gain
Set
Filter
Reference
FSX/TSXE
Autozero
Output
Register
TSX/
DCLKX
PCM OUT
Approximation
Successive
Comparator
Sample
and Hold
and DAC
Filter
CLK
FSR/TSRE
ANLG
GND
DGTL
GND
VBB
VCC
+
11
14
15
7
2
3
11
12
10
9
4
6
5
13
8
1
16
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D AUGUST 1987 REVISED OCTOBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ANLG IN
14
I
Inverting analog input to uncommitted transmit operational amplifier.
ANLG GND
13
Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND.
CLK
9
I
Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate
mode. CLK is used for both the transmit and receive sections.
DCLKR
5
I
Fixed-data-rate mode -- variable-data-rate mode select. When DCLKR is connected to VBB, the device operates
in the fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate
mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz.
DGTL GND
8
Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND.
FSR/TSRE
7
I
Frame-synchronization clock input /time-slot enable for the receive channel. In the variable-data-rate mode, this
signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR
is TTL low for 30 ms.
FSX/TSXE
10
I
Frame-synchronization clock input /time-slot enable for transmit channel. FSX/TSXE operates independently of,
but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300
ms.
GSX
15
O
Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit
filter.
PCM IN
6
I
Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock,
which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.
PCM OUT
11
O
Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit
data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
PDN
4
I
Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and
active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be
connected to a TTL high level.
PWRO +
2
O
Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly
in either a differential or single-ended configuration.
PWRO
3
O
Inverting output of power amplifier. PWRO is functionally identical to PWRO +.
TSX/DCLKX
12
I/O
Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain
output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the
transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.
VBB
1
Negative supply voltage. Input is 5 V
5%.
VCC
16
Positive supply voltage. Input is 5 V
5%.
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D AUGUST 1987 REVISED OCTOBER 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital ground voltage range
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TCM29C18, TCM29C19
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . .
TCM129C18, TCM129C19
40
C to 85
C
. . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package
260
C
. . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VBB.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
Supply voltage (see Note 3)
4.75
5
5.25
V
VBB
Supply voltage
4.75
5
5.25
V
DGTL GND voltage with respect to ANLG GND
0
V
VIH
High-level input voltage, all inputs except ANLG IN
2.2
V
VIL
Low-level input voltage, all inputs except ANLG IN
0.8
V
VI(PP) Peak-to-peak analog input voltage (see Note 4)
4.2
V
RL
Load resistance
GSX
10
k
RL
Load resistance
PWRO + and/or PWRO
300
CL
Load capacitance
GSX
50
pF
CL
Load capacitance
PWRO + and/or PWRO
100
pF
TA
Operating free air temperature
TCM29C18 or TCM29C19
0
70
C
TA
Operating free-air temperature
TCM129C18 or TCM129C19
40
85
C
NOTES:
2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
3. Voltages at analog inputs and outputs and VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced
to DGTL GND unless otherwise noted.
4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct A/D conversion. The digital
code representing values higher than 4.2 V is 10 000 000. For values more negative than 4.2 V, the code is 0000000.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, f
DCLK
= 2.048 MHz, outputs not loaded
PARAMETER
TEST CONDITIONS
TCM29Cxx
TCM129Cxx
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Operating
10
14
ICC
Supply current from VCC
Standby
FSX or FSR at VIL after 300 ms
1.2
1.5
mA
CC
y
CC
Power down
PDN at VIL after 10
s
1
1.2
Operating
10
14
IBB
Supply current from VBB
Standby
FSX or FSR at VIL after 300 ms
1.2
1.5
mA
Power down
PDN at VIL after 10
s
1
1.2
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D AUGUST 1987 REVISED OCTOBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ground terminals
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC resistance between ANLG GND and DGTL GND
34
digital interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High level output voltage at PCM OUT
IOH = 9.6 mA
2.4
V
VOH
High-level output voltage at PCM OUT
IOH = 0.1 mA
3.5
V
VOL
Low-level output voltage at TSX
IOL = 3.2 mA
0.5
V
IIH
High-level input current, any digital input
VI = 2.2 V to VCC
12
A
IIL
Low-level input current, any digital input
VI = 0 to 0.8 V
12
A
Ci
Input capacitance
5
10
pF
Co
Output capacitance
5
pF
All typical values are at VBB = 5 V, VCC = 5 V, and TA = 25
C.
transmit side (A/D) characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage at ANLG IN
VI = 2.17 V to 2.17 V
25
mV
Input offset current at ANLG IN
VI = 2.17 V to 2.17 V
1
pA
Input bias current
VI = 2.17 V to 2.17 V
100
nA
Open-loop voltage amplification at GSX
5000
Unity-gain bandwidth at GSX
1
MHz
Input resistance at ANLG IN
10
M
Gain-tracking error with sinusoidal input
3
dBm0 input level
40 dBm0,
Ref level = 10 dBm0
0.5
dB
g
(see Notes 5, 6, and 7)
40 > dBm0 input level
50 dBm0,
Ref level = 10 dBm0
25
dB
Transmit gain tolerance
VI = 1.06 V,
f = 1.02 kHz
0.95
1.19
Vrms
Noise
Ref max output level: 200 Hz to 3 kHz
70
dB
Supply-voltage rejection ratio,
VCC to VBB
f = 0 Hz to 30-kHz (measured at PCM OUT) idle channel,
Supply signal = 200 mV peak to peak
20
dB
Crosstalk attenuation, transmit to
receive (single ended)
ANLG IN = 0 dBm,
PCM IN = lowest decode level,
f = 1-kHz, unity gain,
Measured at PWRO +
62
dB
Si
l t di t ti
ti
i
id l
0 dBm0
ANLG IN
30 dBm0
33
Signal-to-distortion ratio, sinusoidal
input (see Note 8)
30 dBm0 > ANLG IN
40 dBm0
27
dB
in ut (see Note 8)
40 dBm0 > ANLG IN
45 dBm0
22
Absolute delay time to PCM OUT
Fixed-data rate,
Input to ANLG IN = 1 kHz at 0 dB
fCLKX = 2.048 MHz,
245
s
All typical values are at VBB = 5 V, VCC = 5 V, and TA = 25
C.
NOTES:
5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point
of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave
through an ideal encoder.
7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO + and PWRO to 0 dBM. All
output levels are (sin x)/x corrected.
8. CCITT G.712 Method 2
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