Number of Pins:
24
X
20
X
16
X
X
-Law/A-Law Coding:
-Law
X
X
X
A-Law
X
X
Gain Timing Rates:
Variable Mode
64 kHz to 2.048 MHz
X
X
X
X
Fixed Mode
1.536 MHz
X
X
1.544 MHz
X
X
2.048 MHz
X
X
X
X
Loopback Test Capability
X
8th-Bit Signaling
X
FEATURES TABLE
FEATURE
29C13A
129C13A
29C14A
129C14A
29C16A
129C16A
29C17A
129C17A
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E AUGUST 1989 REVISED OCTOBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Replace Use of TCM2910A and TCM2911A
in Tandem With TCM2912B/C
D
Reliable Silicon-Gate CMOS Technology
D
Low Power Consumption:
Operating Mode . . . 80 mW Typical
Power-Down Mode . . . 5 mW Typical
D
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
D
No External Components Needed for
Sample, Hold, and Autozero Functions
D
Precision Internal Voltage References
D
Improved Version of TCM29C13 Series
and TCM129C13 Series
description
The TCM29C13A, TCM29C14A, TCM29C16A,
TCM29C17A, TCM129C13A, TCM129C14A,
TCM129C16A, and TCM129C17A are single-chip PCM codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices provide all the functions required to interface a full-duplex (4-wire)
voice telephone circuit with a time-division-multiplexed (TDM) system. These devices are intended to replace
the TCM2910A or TCM2911A in tandem with the TCM2912C. Primary applications include:
Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone
systems
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data storage systems
Digital signal processing
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VBB
PWRO +
PWRO
PDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLG IN
ANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
TCM29C16, TCM29C16A,
TCM129C16, TCM129C17A
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VBB
PWRO +
PWRO
GSR
PDN
CLKSEL
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLG IN
ANLG IN +
ANLG GND
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
TCM29C13A, TCM129C13A
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VBB
PWRO +
PWRO
GSR
PDN
CLKSEL
ANLG LOOP
SIGR
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLG IN
ANLG IN +
ANLG GND
NC
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKX
CLKR
TCM29C14A, TCM129C14A
DW PACKAGE
(TOP VIEW)
NC No internal connection
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E AUGUST 1989 REVISED OCTOBER 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are
intended to be used at the analog termination of a PCM line or trunk.
The TCM29C13A, TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A,
and TCM129C17A provide the band-pass filtering of the analog signals prior to encoding and after decoding.
These combination devices perform the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information. These devices contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below 55 dBm0.
The TCM29C13A, TCM29C14A, TCM29C16A, and TCM29C17A are characterized for operation from 0
C to
70
C. The TCM129C13A, TCM129C14A, TCM129C16A, and TCM129C17A are characterized for operation
from 40
C to 85
C.
functional block diagram
Successive
Approximation
Buffer
PWRO+
PWRO
GSR
GSX
ANLG IN
ANLG IN+
Transmit Section
Receive Section
SIGR
Control
Section
PDN
Control
Logic
DCLKR
PCM IN
Input
Register
Digital-
to-Analog
Control
Logic
Reference
Sample
and Hold
and DAC
Analog-
to-Digital
Control
Logic
Gain
Set
Filter
Reference
FSX/TSXE
Autozero
Output
Register
TSX/DCLKX
PCM OUT
Comparator
Sample
and Hold
and DAC
Filter
SIGX/ASEL
CLKX
CLKSEL
ANLG
LOOP
FSR/TSRE
CLKR
ANLG
GND
DGTL
GND
VBB
VCC
TCM29C14A and TCM129C14A only.
TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and TCM129C17A only
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E AUGUST 1989 REVISED OCTOBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
NAME
TCM29C13A
TCM129C13A
TCM29C14A
TCM129C14A
TCM29C16A
TCM29C17A
TCM129C16A
TCM129C17A
I/O
DESCRIPTION
ANLG GND
16
20
13
Analog ground return for all internal voice circuits. ANLG GND is
internally connected to DGTL GND.
ANLG IN +
17
21
I
Noninverting analog input to uncommitted transmit operational
amplifier. ANLG IN + is internally connected to ANLG GND on
TCM29C16A, TCM129C16A, TCM29C17A, and TCM129C17A.
ANLG IN
18
22
14
I
Inverting analog input to uncommitted transmit operational amplifier.
ANLG LOOP
7
I
Provides loopback test capability. When ANLG LOOP is high,
PWRO + is internally connected to ANLG IN.
CLKR
11
13
9
I
Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. CLKR and
CLKX are internally connected together for the TCM29C13A,
TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and
TCM129C17A.
CLKSEL
6
6
I
Clock-frequency selection. CLKSEL must be connected to VBB,
VCC, or GND to reflect the master clock frequency. When tied to VBB,
CLK is 2.048 MHz. When tied to GND, CLK is 1.544 MHz.
When tied to VCC, CLK is 1.536 MHz.
CLKX
11
14
9
I
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. CLKR and
CLKX are internally connected for the TCM29C13A, TCM29C16A,
TCM29C17A, TCM129C13A, TCM129C16A, and TCM129c17A.
DCLKR
7
9
5
I
Selects fixed- or variable-data-rate operation. When DCLKR is
connected to VBB, the device operates in the fixed-data-rate mode.
When DCLKR is not connected to VBB, the device operates in the
variable-data-rate mode and DCLKR becomes the receiver data
clock, which operates at frequencies from 64 kHz to 2.048 MHz.
DGTL GND
10
12
8
Digital ground for all internal logic circuits. DGTL GND is internally
connected to ANLG GND.
FSR/TSRE
9
11
7
I
Frame-synchronization clock input/time-slot enable for receive
channel. In the fixed-data-rate mode, FSR distinguishes between
signaling and nonsignaling frames by a double- or single-length
pulse, respectively. In the variable-data-rate mode, this signal must
remain high for the duration of the time slot. The receive channel
enters the standby state when FSR is TTL low for 300 ms.
FSX/TSXE
12
15
10
I
Frame-synchronization clock input/time-slot enable for transmit
channel. FSX/TSXE operates independently of, but in an analagous
manner to, FSR/TSRE. The transmit channel enters the standby
state when FSX is low for 300 ms.
GSR
4
4
I
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending
upon the voltage at GSR.
GSX
19
23
15
O
Output terminal of internal uncommitted operational amplifier.
Internally, this is the voice signal input to the transmit filter.
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E AUGUST 1989 REVISED OCTOBER 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NO.
NAME
TCM29C13A
TCM129C13A
TCM29C14A
TCM129C14A
TCM29C16A
TCM29C17A
TCM129C16A
TCM129C17A
I/O
DESCRIPTION
PCM IN
8
10
6
I
Receive PCM input. PCM data is clocked in on PCM IN on eight
consecutive negative transitions of the receive data clock, which is
CLKR in fixed-data-rate timing and DCLKR in variable-data-rate
timing.
PCM OUT
13
16
11
O
Transmit PCM output. PCM data is clocked out on PCM OUT on eight
consecutive positive transitions of the transmit data clock, which is
CLKX in fixed-data-rate timing and DCLKX in variable-data-rate
timing.
PDN
5
5
4
I
Power-down select. The device is inactive with a TTL low-level input
to this PDN and active with a TTL high-level input to this PDN.
PWRO +
2
2
2
O
Noninverting output of power amplifier. PWRO + drives transformer
hybrids or high-impedance loads directly in either a differential or a
single-ended configuration.
PWRO
3
3
3
O
Inverting output of power amplifier. PWRO is functionally identical
with and complementary to PWRO +.
SIGR
8
O
Signaling bit output, receive channel. In the fixed-data-rate mode,
SIGR outputs the logical state of the 8th bit (LSB) of the PCM word
in the most recent signaling frame.
SIGX/ASEL
15
18
I
A-law and
-law operation select. When connected to VBB, A-law is
selected. When connected to VCC or GND,
-law is selected. When
not connected to VBB, it is a TTL-level input that is transmitted as the
eighth bit (LBS) of the PCM word during signaling frames on PCM
OUT (TCM29C14A and TCM129C14A only). SIGX/ASEL is
internally connected to provide
-law operational for TCM29C16A
and TCM129C16A and A-law operation for TCM29C17A and
TCM129C17A.
TSX/DCLKX
14
17
12
I/O
Transmit channel time-slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, TSX/DCLKX is an
open-drain output to be used as an enable signal for a 3-state output
buffer. In the variable-data-rate mode, DCLKX becomes the transmit
data clock, which operates at a TTL level from 64 kHz to 2.048 MHz.
VBB
1
1
1
Most negative supply voltage. Input is 5 V
5%.
VCC
20
24
16
Most positive supply voltage. Input is 5 V
5%.
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030E AUGUST 1989 REVISED OCTOBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital ground voltage range
0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation at (or below) 25
C free-air temperature
1375 mW
. . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TCM29CxxA 0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCM129CxxA 40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package
260
C
. . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VBB.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
Supply voltage (see Note 3)
4.75
5
5.25
V
VBB
Supply voltage
4.75
5
5.25
V
Digital ground voltage, with respect to ANLG GND
0
V
VIH
High-level input voltage, all inputs except CLKSEL
2.2
V
VIL
Low-level input voltage, all inputs except CLKSEL
0.8
V
2.048 MHz
VBB
VBB +0.5
VI
CLKSEL input voltage
1.544 MHz
0
0.5
V
1.536 MHz
VCC 0.5
VCC
RL
Load resistance
GSX
10
k
RL
Load resistance
PWRO + and/or PWRO
300
CL
Load capacitance
GSX
50
pF
CL
Load capacitance
PWRO + and/or PWRO
100
pF
TA
Operating free air temperature
TCM29CxxA
0
70
C
TA
Operating free-air temperature
TCM129CxxA
40
85
C
NOTES:
2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
3. Voltage is at analog inputs and outputs. VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced
to DGTL GND unless otherwise noted.
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