TSB43CA43A/TSB43CB43A/TSB43CA42
iceLynx-Micro
IEEE 1394a-2000
Consumer Electronics Solution
ABBREVIATED DATA MANUAL
SLLS546F September 2004
Texas Instruments Incorporated, Copyright 2004
For more information and/or a complete data manual on this product, contact the
Texas Instruments Product Information Center (PIC). Local PIC contact numbers
are listed on http://www.ti.com/corp/technical_support.htm
TSB43Cx43A/
TI iceLynx-MicroTM IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F March 2004 Revised September 2004
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
T
EXAS
I
NSTRUMENTS
Copyright
2004, Texas Instruments Incorporated
M
ARCH
12,
2004
POST
OFFICE
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655303
DALLAS,
TEXAS
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Copyright 2004, Texas Instruments Incorporated
TSB43Cx43A/
TI iceLynx-MicroTM IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F March 2004 Revised September 2004
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
T
EXAS
I
NSTRUMENTS
Copyright
2004, Texas Instruments Incorporated
M
ARCH
12,
2004
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
3
Table of Contents
1
Hardware IC Characteristics.................................................................................................................. 8
1.1
Feature List ................................................................................................................................... 8
1.1.1
1394 Features ......................................................................................................................... 8
1.1.2
DTLA Encryption Support for MPEG2-DVB, DSS, DV, and Audio (TSB43CA43A and
TSB43CA42 Only) ................................................................................................................... 8
1.1.3
High Speed Data Interface (HSDI).......................................................................................... 9
1.1.4
External CPU Interface............................................................................................................ 9
1.1.5
Internal ARM7.......................................................................................................................... 9
1.1.6
Data Buffers............................................................................................................................. 9
1.1.7
Hardware Packet Formatting for the Following Standards ..................................................... 9
1.1.8
Additional Features ................................................................................................................. 9
1.2
Application Diagram.................................................................................................................... 10
1.3
Block Diagram............................................................................................................................. 11
1.3.1
TSB43Cx43A Block Diagram ................................................................................................ 11
1.3.2
TSB43CA42 Block Diagram .................................................................................................. 12
1.4
Pin Out ........................................................................................................................................ 13
1.4.1
TSB43CA43A/TSB43CB43A Plastic Quad Flat Pack (PQFP).............................................. 13
1.4.2
TSB43CA43A/TSB43CB43A Micro-Star Ball Grid Array (
*BGA)........................................14
1.4.3
TSB43CA42 Plastic Quad Flat Pack (PQFP)........................................................................ 15
1.4.4
TSB43CA42 Micro-Star Ball Grid Array (
*BGA)..................................................................16
1.5
Pin Description............................................................................................................................ 17
1.6
Memory Map ............................................................................................................................... 26
1.7
DTCP Encryption Hardware Implementation (TSB43CA43A and TSB43CA42 Only) ............ 27
1.8
Program Memory ........................................................................................................................ 27
1.8.1
Overview/Description ............................................................................................................ 27
1.8.2
External CPU (Parallel Mode) ............................................................................................... 27
1.9
External CPU Interface ............................................................................................................... 27
1.9.1
Overview/Description ............................................................................................................ 27
1.9.2
Endian Setting (Parallel and Memory Accesses) .................................................................. 29
1.9.3
Ex-CPU Access..................................................................................................................... 30
1.9.4
Ex-CPU Timing...................................................................................................................... 33
1.9.5
LEB Encryption...................................................................................................................... 52
1.10
Integrated CPU ........................................................................................................................... 53
1.10.1
Description/Overview ............................................................................................................ 53
1.10.2
Interaction With External CPU............................................................................................... 53
1.10.3
External Interrupts ................................................................................................................. 53
1.10.4
Timer ..................................................................................................................................... 54
1.11
High Speed Data Interface ......................................................................................................... 54
1.11.1
Overview/Description ............................................................................................................ 54
1.11.2
Frame Sync Detection Circuit................................................................................................ 56
1.11.3
HSDI Pass-Through Function ............................................................................................... 56
1.11.4
HSDI Maximum Clock Rates and Throughput ...................................................................... 57
1.11.5
HSDI Mode Settings.............................................................................................................. 57
1.11.6
HSDI Transmit Modes ........................................................................................................... 59
1.11.7
HSDI Receive Modes ............................................................................................................ 62
1.11.8
Audio Interface on HSDI........................................................................................................66
1.12
UART Interface ........................................................................................................................... 70
1.12.1
UART Registers..................................................................................................................... 70
1.12.2
UART Baud Rate................................................................................................................... 71
1.13
JTAG Boundary Scan and ARM .............................................................................................. 72
1.14
Integrated 3-Port PHY ................................................................................................................ 72
TSB43Cx43A/
TI iceLynx-MicroTM IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F March 2004 Revised September 2004
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
T
EXAS
I
NSTRUMENTS
Copyright
2004, Texas Instruments Incorporated
M
ARCH
12,
2004
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TEXAS
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1.14.1
3-Port PHY ............................................................................................................................ 72
1.14.2
PHY Registers ....................................................................................................................... 72
1.14.3
Port Status Page Register..................................................................................................... 75
1.14.4
Vendor Identification Page Register...................................................................................... 77
1.14.5
PHY Application Information ................................................................................................. 77
1.14.6
PHY Reference Documents .................................................................................................. 79
1.15
Power Management.................................................................................................................... 79
1.15.1
PU to A (Power-Up State to Active State)............................................................................. 81
1.15.2
A to LP1 (Active State to Low Power 1 State)....................................................................... 81
1.15.3
LP1 to A (Low Power 1 State to Active State)....................................................................... 81
1.15.4
A to LP2 (Active State to Low Power 2 State)....................................................................... 81
1.15.5
LP2 to A (Low Power 2 State to Active State)....................................................................... 82
1.15.6
A to LP4 (Low Power 3 State to Active State)....................................................................... 82
1.15.7
LP4 to A (Low Power 3 State to Active State)....................................................................... 82
1.16
16.5K Byte Memory - FIFO......................................................................................................... 83
1.16.1
Overview/Description ............................................................................................................ 83
1.16.2
Isochronous FIFOs 0 and 1................................................................................................... 83
1.16.3
Asynchronous/Asynchronous Stream FIFOs ........................................................................ 84
1.16.4
Broadcast Receive FIFO ....................................................................................................... 85
1.16.5
FIFO Priority .......................................................................................................................... 85
1.16.6
FIFO Monitoring..................................................................................................................... 85
1.17
GPIO Configurations................................................................................................................... 86
1.17.1
GPIO Setup ........................................................................................................................... 86
1.18
IEEE 1394a-2000 Requirements ................................................................................................ 86
1.18.1
Features ................................................................................................................................ 86
1.18.2
Cycle Master.......................................................................................................................... 87
2
Appendix A: Configuration Registers................................................................................................... 88
2.1
Configuration Registers .............................................................................................................. 88
2.2
Description Notes........................................................................................................................ 88
2.3
CFR Address Ranges (Offset from CFR Base Address)............................................................ 88
2.4
Register Access .......................................................................................................................... 89
3
General Information ............................................................................................................................. 90
3.1
Package Size .............................................................................................................................. 90
3.2
Operating Voltage....................................................................................................................... 90
3.3
Operating Temperature .............................................................................................................. 90
4
Absolute Maximum Ratings Over Operating Temperature Ranges .................................................. 90
4.1
Recommended Operating Conditions (Analog IEEE 1394 I/F) .................................................. 91
4.2
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)........................................................................................................... 92
4.3
Electrical Characteristics Over Recommended Ranges of Operating Conditions
(Unless Otherwise Noted)........................................................................................................... 92
4.3.1
Device.................................................................................................................................... 92
4.3.2
Driver ..................................................................................................................................... 92
4.3.3
Receiver ................................................................................................................................ 93
4.4
Thermal Characteristics.............................................................................................................. 93
4.5
Switching Characteristics for PHY Port Interface ....................................................................... 93
4.6
Operating, Timing, and Switching Characteristics of XI ............................................................. 93
5
Reset Power States ............................................................................................................................. 94
6
Configuration Register Map ................................................................................................................. 94
7
Mechanical Data .................................................................................................................................. 95
7.1
PQFP Package Information ........................................................................................................ 95
7.2
*BGA Package Dimensions...................................................................................................... 96
7.3
ZGW Package Dimensions......................................................................................................... 97
TSB43Cx43A/
TI iceLynx-MicroTM IEEE 1394a-2000
TSB43CA42
Consumer Electronics Solution
TEXAS INSTRUMENTS
SLLS546F March 2004 Revised September 2004
PRODUCTION DATA information is current as of public
date. Products conform to specifications per the terms of
Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
T
EXAS
I
NSTRUMENTS
Copyright
2004, Texas Instruments Incorporated
M
ARCH
12,
2004
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
5
List Of Figures
Figure 1. TSB43Cx43 Typical Application .................................................................................................. 10
Figure 2. TSB43Cx43 System Block Diagram ............................................................................................ 11
Figure 3. TSB43CA42 System Block Diagram ........................................................................................... 12
Figure 4. TSB43CA43A Plastic QFP Pin Out ............................................................................................. 13
Figure 5. TSB43CA43A
*BGA Pin Out .....................................................................................................14
Figure 6. TSB43CA42 Plastic QFP Pin Out................................................................................................ 15
Figure 7. TSB43CA42
*BGA Pin Out........................................................................................................16
Figure 8. TSB43Cx43 Memory Map ........................................................................................................... 26
Figure 9. Ex-CPU Access ........................................................................................................................... 30
Figure 10. I/O Type-0 68K + Wait Read ..................................................................................................... 33
Figure 11. I/O Type-0 68K + Wait Write...................................................................................................... 35
Figure 12. I/O Type-1 SH3 Read ................................................................................................................ 37
Figure 13. I/O Type-1 SH3 Write ................................................................................................................ 39
Figure 14. I/O Type-2 M16C SRAM-Like + Wait Read ...............................................................................41
Figure 15. I/O Type-2 M16C SRAM-Like + Wait Write ............................................................................... 43
Figure 16. I/O Type-3 MPC850 Read ......................................................................................................... 45
Figure 17. I/O Type-3 MPC850 Write ......................................................................................................... 47
Figure 18. Memory Type ............................................................................................................................. 49
Figure 19. Memory Write............................................................................................................................. 51
Figure 20. Watchdog Timer Waveform ....................................................................................................... 54
Figure 21. Example for Data Pass-Through Function ................................................................................ 57
Figure 22. MPEG2 Serial Burst I/F (TX Mode 1) ........................................................................................ 59
Figure 23. MPEG2 Serial Video Burst I/F With Frame Sync Detect Circuit (TX Mode 2)........................... 60
Figure 24. MPEG2 Serial Video Burst I/F Clock Active Only When Data Is Valid (TX Mode 3)................. 60
Figure 25. MPEG2 Serial Video Burst I/F With Data Valid (TX Mode 4) .................................................... 60
Figure 26. MPEG2 Parallel Burst Video I/F (TX Mode 5) ........................................................................... 61
Figure 27. MEPG2 Parallel Video Burst I/F With Frame Sync Detect Circuit (TX Mode 6)........................ 61
Figure 28. MPEG2 Parallel Video Burst I/F With Data Valid (TX Mode 7) ................................................. 61
Figure 29. MPEG2 I/F (TX Mode 8) ............................................................................................................ 62
Figure 30. DV I/F (TX Mode 9).................................................................................................................... 62
Figure 31. MPEG2 Serial Burst Video I/F (RX Mode 1).............................................................................. 63
Figure 32. MPEG2 Parallel Burst Video I/F (RX Mode 2)........................................................................... 63
Figure 33. MPEG2 Parallel Burst Video I/F (RX Mode 3)........................................................................... 63
Figure 34. DV Parallel Burst Video I/F (RX Mode 4) .................................................................................. 64
Figure 35. Transmit HSDI AC Timing ......................................................................................................... 64
Figure 36. Receive HSDI AC Timing .......................................................................................................... 65
Figure 37. Example 1 Sampling Frequency (fs): 192 kHz, Master Clock Frequency: 256fs ...................... 68
Figure 38. Example 2 Sample Frequency (fs): 48 kHz, Master Clock Frequency: 768fs........................... 68
Figure 39. AC Timing Characteristic on Receiving ..................................................................................... 69
Figure 40. AC Timing Characteristic on Transmitting ................................................................................. 69
Figure 41. TPBP and TPBN Connection..................................................................................................... 77
Figure 42. TPAP, TPAN, and TPBIAS Connection..................................................................................... 78
Figure 43. R0 and R1 Connection .............................................................................................................. 78
Figure 44. FILTER0 and FILTER1 Connection........................................................................................... 78
Figure 45. TPB, TPA, and TPBIAS Connection for Terminated Port (Port is not used)............................. 79
Figure 46. Isochronous FIFOs .................................................................................................................... 84
Figure 47. Asynchronous/ Asynchronous Stream FIFOs ........................................................................... 84
Figure 48. Broadcast Receive FIFO ........................................................................................................... 85
Figure 49. Test Load Diagram .................................................................................................................... 93
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