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FEATURES
APPLICATIONS
DESCRIPTION
TVP7000
SLES143 SEPTEMBER 2005
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
LCD TV/Monitors/Projectors
Analog Channels
DLP TV/Projectors
-6 dB to 6 dB Analog Gain
PDP TV/Monitors
Analog Input MUXs
PCTV Set-Top Boxes
Auto Video Clamp
Digital Image Processing
Three Digitizing Channels, Each With
Video Capture/Video Editing
Independently Controllable Clamp, PGA,
Scan Rate/Image Resolution Converters
and ADC
Video Conferencing
Clamping: Selectable Clamping Between
Video/Graphics Digitizing Equipment
Bottom Level and Mid-level
Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
TVP7000 is a complete solution for digitizing video
PGA: 8-Bit Programmable Gain Amplifier
and graphic signals in RGB or YPbPr color spaces.
ADC: 8/10-Bit 150/110 MSPS A/D Converter
The device supports pixel rates up to 150 MHz.
Automatic Level Control Circuit
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of SXGA (1280
1024)
Composite Sync: Integrated Sync-on-Green
resolution at 75 Hz screen refresh rate, and in video
Extraction From GreenLuminance Channel
environments for the digitizing of digital TV formats,
Support for DC and AC-Coupled Input
including HDTV up to 1080p. TVP7000 can be used
Signals
to digitize CVBS and S-Video signal with 10-bit
PLL
ADCs.
Fully Integrated Analog PLL for Pixel Clock
The TVP7000 is powered from 3.3-V and 1.8-V
Generation
supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,
12-150 MHz Pixel Clock Generation From
independently programmable for each channel. The
HSYNC Input
clamping timing window is provided by an external
Adjustable PLL Loop Bandwidth for
pulse or can be generated internally. The TVP7000
Minimum Jitter
includes analog slicing circuitry on the Y or G input to
5-Bit Programmable Subpixel Accurate
support sync-on-luminance or sync-on-green extrac-
Positioning of Sampling Phase
tion. In addition, TVP7000 can extract discrete
HSYNC and VSYNC from composite sync using a
Output Formatter
sync slicer.
Support for RGB/YCbCr 4:4:4 and YCbCr
TVP7000 also contains a complete analog PLL block
4:2:2 Output Modes to Reduce Board Traces
to generate a pixel clock from the HSYNC input. Pixel
Dedicated DATACLK Output for Easy
clock output frequencies range from 12 MHz to 150
Latching of Output Data
MHz.
System
All programming of the part is done via an indus-
Industry-Standard Normal/Fast I
2
C Interface
try-standard I
2
C interface, which supports both read-
With Register Readback Capability
ing and writing of register settings. The TVP7000 is
Space-Saving TQFP-100 Pin Package
available in a space-saving TQFP 100-pin PowerPAD
package.
Thermally-Enhanced PowerPADTM Package
for Better Heat Dissipation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
TVP7000
SLES143 SEPTEMBER 2005
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ANALOG VIDEO
Analog video input for R/Pr 1
RIN_1
11
I
Analog video input for R/Pr 2
RIN_2
10
I
Analog video input for R/Pr 3
RIN_3
9
I
Analog video input for G/Y 1
GIN_1
2
I
Analog video input for G/Y 2
GIN_2
100
I
Analog video input for G/Y 3
GIN_3
98
I
Analog video input for G/Y 4
GIN_4
96
I
Analog video input for B/Pb 1
BIN_1
18
I
Analog video input for B/Pb 2
BIN_2
17
I
Analog video input for B/Pb 3
BIN_3
16
I
The inputs must be AC coupled. The recommended coupling capacitor is 0.1
F. Unused analog
inputs should be connected to ground using a 10 nF capacitor.
CLOCK SIGNALS
DATACLK
28
O
Data clock output
EXT_CLK
80
I
External clock input for free running mode
TEST
22
O
Internal 5 MHz clock output, coast output, high-Z, or SOG output
DIGITAL VIDEO
ROUT [9:0]
5559, 6165
O
Digital video output of R/Cr, ROUT [9] is MSB.
GOUT [9:0]
43-52
O
Digital video output of G/Y, GOUT [9] is MSB.
BOUT [9:0]
29-38
O
Digital video output of B/Cb, BOUT [9] is MSB. For a 4:2:2 mode BOUT outputs CbCr data.
Unused outputs can be left unconnected.
MISCELLANEOUS SIGNALS
PWDN
70
I
Power down input. 1: Power down 0: Normal mode
RESETB
71
I
Reset input, active low
Test Mode Select input. Used to enable JTAG test mode. Active high. Normal mode, this terminal
TMS
72
I
should be connected to a ground.
FILT1
87
O
External filter connection for PLL. The recommended capacitor is 0.1
F. see
Figure 4
FILT2
88
O
External filter connection for PLL. The recommended capacitor is 4.7 nF. See
Figure 4
HOST INTERFACE
I
2
C A
73
I
I
2
C Address input
SCL
74
I
I
2
C Clock input
SDA
75
I/O
I
2
C Data bus
POWER SUPPLIES
NSUB
21, 91
I
Substrate ground. Connect to analog ground.
A33VDD
13, 14, 93, 94
I
Analog power. Connect to 3.3 V.
A33GND
12, 15, 92, 95
I
Analog 3.3 V return. Connect to Ground.
A18GND
3, 5, 8, 20
I
Analog 1.8V return. Connect to Ground
A18VDD
4, 6, 7, 19
I
Analog power. Connect to 1.8 V.
PLL_A18VDD
84, 85
I
PLL analog power. Connect to 1.8 V.
PLL_F
89
I
PLL filter internal supply connection
PLL_A18GND
83, 86, 90
I
PLL analog power return. Connect to Ground.
GND
40, 68
I
Digital return. Connect to Ground.
DVDD
39, 69
I
Digital power. Connect to 1.8 V
27, 42, 54, 60,
Digital power return. Connect to Ground.
IOGND
I
67
IOVDD
26, 41, 53, 66
I
Digital power. Connect to 3.3 V or less for reduced noise.
SYNC SIGNALS
CLAMP
76
I
External Clamp input. Unused inputs can be connected to ground.
COAST
77
I
External PLL COAST signal input. Unused inputs can be connected to ground
4
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TVP7000
SLES143 SEPTEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
VSYNC_A
78
I
Vertical sync input A
VSYNC_B
79
I
Vertical sync input B. Unused inputs can be connected to ground.
HSYNC_A
81
I
Horizontal Sync input A
HSYNC_B
82
I
Horizontal Sync input B. Unused inputs can be connected to ground.
SOGIN1
1
I
Sync-on-green input 1
SOGIN2
99
I
Sync-on-green input 2
SOGIN3
97
i
Sync-on-green input 3. Unused inputs should be connected to ground using a 10 nF capacitor.
VSOUT
23
O
Vertical sync output
HSOUT
24
O
Horizontal sync output
SOGOUT
25
O
Sync-on-green slicer output
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
IOVDD to IOGND
0.5 V to 4.5 V
DVDD to GND
0.5 V to 2.3 V
Supply voltage range
PLL_A18VDD to PLL_A18GND and A18VDD to A18GND
0.5 V to 2.3 V
A33VDD to A33GND
0.5 V to 4.5 V
Digital input voltage range
VI to GND
0.5 V to 4.5 V
Analog input voltage range
AI to A33GND
0.2 V to 2.3 V
Digital output voltage range
VO to GND
0.5 V to 4.5 V
TA
Operating free-air temperature
0
C to 70
C
Tstg
Storage temperature
65
C to 150
C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
over operating free-air temperature range, T
A
= 0
C to 70
C (unless otherwise noted)
MIN
NOM
MAX
UNIT
IOVDD
Digital I/O supply voltage
3.0
3.3
3.6
V
DVDD
Digital supply voltage
1.70
1.8
1.9
V
PLL_A18VDD
Analog PLL supply voltage
1.70
1.8
1.9
V
A18VDD
Analog supply voltage
1.70
1.8
1.9
V
A33VDD
Analog supply voltage
3.0
3.3
3.6
V
V
I(PP)
Analog input voltage (accoupling necessary)
0.5
2.0
V
V
IH
Digital input voltage high
0.7 IOVDD
V
V
IL
Digital input voltage low
0.3 IOVDD
V
I
OH
Highlevel output current
2
mA
I
OL
Lowlevel output current
2
mA
I
OH_DATACLK
DATACLK highlevel output current
4
mA
I
OL_DATACLK
DATACLK lowlevel output current
4
mA
T
A
Operating freeair temperature
0
70
C
5
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