Voltage-to-Frequency
and Frequency-to-Voltage
CONVERTER
FEATURES
q
HIGH LINEARITY: 12 to 14 bits
0.005% max at 10kHz FS
0.03% max at 100kHz FS
0.1% typ at 1MHz FS
q
V/F OR F/V CONVERSION
q
6-DECADE DYNAMIC RANGE
q
GAIN DRIFT: 20ppm/
C max
q
OUTPUT TTL/CMOS COMPATIBLE
APPLICATIONS
q
INEXPENSIVE A/D AND D/A CONVERTER
q
DIGITAL PANEL METERS
q
TWO-WIRE DIGITAL TRANSMISSION WITH
NOISE IMMUNITY
q
FM MOD/DEMOD OF TRANSDUCER
SIGNALS
q
PRECISION LONG TERM INTEGRATOR
q
HIGH RESOLUTION OPTICAL LINK FOR
ISOLATION
q
AC LINE FREQUENCY MONITOR
q
MOTOR SPEED MONITOR AND CONTROL
Comparators
7.5V Ref
Flip-
flop
Common
f
OUT
f
IN
One-shot
V
OUT
+V
CC
In
+In
V
CC
C
1
DESCRIPTION
The VFC320 monolithic voltage-to-frequency and frequency-to-
voltage converter provides a simple low cost method of convert-
ing analog signals into digital pulses. The digital output is an
open collector and the digital pulse train repetition rate is propor-
tional to the amplitude of the analog input voltage. Output pulses
are compatible with TTL, and CMOS logic families.
High linearity (0.005%, max at 10kHz FS) is achieved with
relatively few external components. Two external resistors and
two external capacitors are required to operate. Full scale fre-
quency and input voltage are determined by a resistor in series
with In and two capacitors (one-shot timing and input amplifier
integration). The other resistor is a non-critical open collector
pull-up (f
OUT
to +V
CC
). The VFC320 is available in two perfor-
mance grades. The VFC320 is specified for the 25
C to +85
C,
range.
VFC320
SBVS017A AUGUST 2001
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1982, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VFC320
VFC320
2
SBVS017A
Specification the same as for VFC320BP.
ELECTRICAL CHARACTERISTICS
At T
A
= +25
C and
15VDC power supply, unless otherwise noted.
NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by R
IN
and full scale current range
constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between
the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity
error determines the final accuracy. (6) For e
1
= 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components' drift.
(8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature.
(10) One pulse of new frequency plus 50ns typical.
VFC320BP
VFC320CP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V/F CONVERTER f
OUT
= V
IN
/7.5 R
1
C
1
, Figure 4
INPUT TO OP AMP
Voltage Range
(1)
Fig. 4 with e
2
= 0
>0
Note 2
V
Fig. 4 with e
1
= 0
<0
10
V
Current Range
(1)
I
IN
= V
IN
/R
IN
+0.25
+750
A
Bias Current
Inverting Input
4
8
nA
Noninverting Input
10
30
nA
Offset Voltage
(3)
0.15
mV
Offset Voltage Drift
5
V/
C
Differential Impedance
300 || 5
650 || 5
k
|| pF
Common-Mode
Impedance
300 || 3
500 || 3
k
|| pF
ACCURACY
Linearity Error
(1) (4) (5)
Fig. 4 with e
2
= 0
(6)
0.01Hz
f
OUT
10kHz
0.004
0.005
0.0015
0.002
% FSR
0.1Hz
f
OUT
100kHz
0.008
0.030
% FSR
1Hz
f
OUT
1MHz
0.1
% FSR
Offset Error Input
Offset Voltage
(3)
15
ppm FSR
Offset Drift
(7)
0.5
ppm FSR/
C
Gain Error
(3)
5
10
% FSR
Gain Drift
(7)
f = 10kHz
50
20
ppm FSR/
C
Full Scale Drift
f = 10kHz
50
20
ppm FSR/
C
(Offset Drift and Gain Drift)
(7)(8)(9)
Power Supply Sensitivity
V
CC
= 14VDC to 18VDC
0.015
% FSR%
DYNAMIC RESPONSE
Full Scale Frequency
C
LOAD
50pF
1
MHz
Dynamic Range
6
Decades
Settling Time
(V/F) to Specified Linearity
For a Full Scale Input Step
Note 10
Overload Recovery
<50% Overload
Note 10
OPEN COLLECTOR OUTPUT
Voltage, Logic "0"
I
SINK
= 8mA, max
0.4
V
Leakage Current, Logic "1"
V
O
= 15V
0.01
1.0
A
Voltage, Logic "1"
External Pull-up Resistor
Required (See Figure 4)
V
PU
V
Duty Cycle at FS
For Best Linearity
25
%
Fall Time
I
OUT
= 5mA, C
LOAD
= 500pF
100
ns
F/V CONVERTER V
OUT
= 7.5 R
1
C
1
f
IN
, Figure 9
INPUT TO COMPARATOR
Impedance
50 || 10
150 || 10
k
|| pF
Logic "1"
+1.0
+V
CC
V
Logic "0"
V
CC
0.05
V
Pulse-width Range
0.25
s
OUTPUT FROM OP AMP
Voltage
I
O
= 6mA
0 to +10
V
Current
V
O
= 7VDC
+10
mA
Impedance
Closed-Loop
0.1
Capacitive Load
Without Oscillation
100
pF
POWER SUPPLY
Rated Voltage
15
V
Voltage Range
13
20
V
Quiescent Current
6.5
7.5
mA
TEMPERATURE RANGE
Specification
B and C Grades
25
+85
C
S Grade
55
+125
C
Operating
B and C Grades
40
+85
C
S Grade
55
+125
C
Storage
65
+150
C
VFC320
3
SBVS017A
PACKAGE
SPECIFIED
DRAWING
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
DESIGNATOR
RANGE
MARKING
NUMBER
(1)
MEDIA
VFC320BP
DIP-14
010
N
40
C to +85
C
VFC320CP
DIP-14
010
N
40
C to +85
C
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "VFC320BP/2K5" will get a single 2500-piece Tape and Reel.
Top View
DIP
+V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
V
CC
f
OUT
In
NC
One-Shot
Capacitor
V
OUT
Common
+In
NC
NC
Comparator
Input
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...................................................................................
20V
Output Sink Current at f
OUT
............................................................... 50mA
Output Current at V
OUT
................................................................... +20mA
Input Voltage, Input ..........................................................................
V
CC
Input Voltage, +Input ..........................................................................
V
CC
Storage Temperature Range .......................................... 65
C to +150
C
Lead Temperature (soldering, 10s) ............................................... +300
C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
VFC320
4
SBVS017A
DISCUSSION OF
SPECIFICATIONS
LINEARITY
Linearity is the maximum deviation of the actual transfer
function from a straight line drawn between the end points
(100% full scale input or frequency and 0.1% of full scale
called zero.) Linearity is the most demanding measure of
voltage-to-frequency converter performance, and is a func-
tion of the full scale frequency. Refer to Figure 1 to deter-
mine typical linearity error for your application. Once the
full scale frequency is chosen, the linearity is a function of
operating frequency as it varies between zero and full scale.
Examples for 10kHz full scale are shown in Figure 2. Best
linearity is achieved at lower gains (
f
OUT
/
VIN
) with opera-
tion as close to the chosen full scale frequency as possible
The high linearity of the VFC320 makes the device an
excellent choice for use as the front end of Analog-to-Digital
(A/D) converters with 12- to 14-bit resolution, and for
highly accurate transfer of analog data over long lines in
noisy environments (2-wire digital transmission.)
Figure
Figure
Figure 1. Linearity Error vs Full Scale Frequency.
Figure 2. Linearity Error vs Operating Frequency.
0
2k
4k
6k
8k
10k
Operating Frequency (Hz)
0.003
0.002
0.001
0
0.001
0.002
0.003
Typical Linearity jErrorf (% of FSR)
1k
3k
5k
7k
9k
B Grade
C Grade
f
FULL SCALE
= 10kHz
Typical, T
A
= +25C
FREQUENCY STABILITY VS TEMPERATURE
The full scale frequency drift of the VFC320 versus tem-
perature is expressed as parts per million of full scale range
per
C. As shown in Figure 3, the drift increases above
10kHz. To determine the total accuracy drift over tempera-
ture, the drift coefficients of external components (espe-
cially R
1
and C
1
) must be added to the drift of the VFC320.
RESPONSE
Response of the VFC320 to changes in input signal level is
specified for a full scale step, and is 50ns plus 1 pulse of the
new frequency. For a 10V input signal step with the VFC320
operating at 100kHz full scale, the settling time to within
0.01% of full scale is 10
s.
THEORY OF OPERATION
The VFC320 monolithic voltage-to-frequency converter pro-
vides a digital pulse train output whose repetition rate is
directly proportional to the analog input voltage. The circuit
shown in Figure 4 is composed of an input amplifier, two
comparators and a flip-flop (forming a on-shot), two switched
current sinks, and an open collector output transistor stage.
Essentially the input amplifier acts as an integrator that
produces a two-part ramp. The first part is a function of the
input voltage, and the second part is dependent on the input
voltage and current sink. When a positive input voltage is
applied at V
IN
, a current will flow through the input resistor,
causing the voltage at V
OUT
to ramp down toward zero,
according to dV/dt = V
IN
/R
1
C
1
. During this time the con-
stant current sink is disabled by the switch. Note, this period
is only dependent on V
IN
and the integrating components.
When the ramp reaches a voltage close to zero, comparator
A sets the flip-flop. This closes the current sink switches as
well as changing f
OUT
from logic 0 to logic 1. The ramp now
begins to ramp up, and 1mA charges through C
1
until V
C1
=
7.5V. Note this ramp period is dependent on the 1mA
current sink, connected to the negative input of the op amp,
as well as the input voltage. At this 7.5V threshold point
C
1
, comparator B resets the flip-flop, and the ramp voltage
Figure 3. Full Scale Drift vs Full Scale Frequency.
1k
1M
Full Scale Frequency (Hz)
1000
10
Typical Full Scale Temp Drift
(ppm of FSR/
C)
10k
100k
100
C Grade
B and S Grades
1k
1M
Full Scale Frequency (Hz)
0.10
0.001
Typical Linearity Error (% of FSR)
10k
100k
0.01
D
FS
= 0.25
T
A
= +25C
VFC320
5
SBVS017A
(8)
In the time t
1
+ t
2
the integrator capacitor C
2
charges and
discharges but the net voltage change is zero.
Thus
Q = 0 = I
IN
t
1
+ (I
IN
I
A
) t
2
So that I
IN
(t
1
+ t
2
) = I
A
t
2
But since t
1
+ t
2
= and I
IN
=
f
OUT
=
In the time t
1
, I
B
charges the one-shot capacitor C
1
until its
voltage reaches 7.5V and trips comparator B.
Thus t
2
=
Using
in
yield f
V
R C
I
I
OUT
IN
B
A
( )
( )
.
7
6
7 5
1
1
=
Since I
A
= I
B
the result is
f
OUT
=
Since the integrating capacitor, C
2
, affects both the rising
and falling segments of the ramp voltage, its tolerance and
temperature coefficient do not affect the output frequency. It
should, however, have a leakage current that is small com-
pared to I
IN
, since this parameter will add directly to the gain
error of the VFC. C
1
, which controls the one-shot period,
should be very precise since its tolerance and temperature
coefficient add directly to the errors in the transfer function.
begins to ramp down again before the input amplifier has a
chance to saturate. In effect the comparators and flip-flop
form a one-shot whose period is determined by the internal
reference and a 1mA current sink plus the external capacitor,
C
1
. After the one-shot resets, f
OUT
changes back to logic 0
and the cycle begins again.
The transfer function for the VFC320 is derived for the
circuit shown in Figure 4. Detailed waveforms are shown in
Figure 5.
f
OUT
=
1
t
1
+ t
2
0V
7.5V
V
OUT
t
1
t
2
VFC Output
f
OUT
One-shot
V
C1
Integrator Output
V
OUT
FIGURE 5. Integrator and VFC Output Timing.
(1)
FIGURE 4. Functional Block Diagram of the VFC320.
f
OUT
V
IN
1
R
1
I
A
R
2
R
2
V
IN
C
IN
7.5
I
B
7.5 R
1
C
1
V
IN
(3)
(2)
(4), (5)
(6)
(7)
(9)
Comparators
Flip-
flop
Common
f
OUT
f
IN
One-shot
V
OUT
1
5
4
11
I
A
I
IN
e
1
e
2
Switch
C
1
One-shot
Capacitor
V
CC
12
+V
CC
7
Pull-up
Resitor
R
2
10
13
Input
Amp
Constant
Current Sinks
(1mA)
7.5V
Ref
B
Integrating
Capacitor
R
1
Input Resistor
Q
1
C
2
I
B
A
For Postive Input Voltages use e
1
, short e
2
.
For Negative Input Voltages use e
2
, short e
1
.
For Differental Input Voltages use e
1 and
e
2
.
V
IN:
f
OUT
=
V
IN
7.5 R
1
C
1
+V
PULL-UP
(V
PU
)
(5V to 15V Typically)
14
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