TE
CH
tm
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 1
Publication Date: SEP. 2001
to change products or specifications without notice.
Revision: G
SRAM
32K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
High speed access time: 7/8/10/12/15ns(max.)
Low power consumption : Active 300 mW (typ.)
Single + 5 power supply
Fully static operation No clock or refreshing
required
All inputs and outputs directly TTL compatible
Common I/O capability
Available packages : 28-pin 300 mil SOJ and
TSOP-I (forward type ).
Output enable (
OE
) available for very fast
access
Mix-mode Outputs
PIN CONFIGURATION
A12
A14
A7
A6
A5
A3
A4
A2
A1
A0
I/O1
I/O2
I/O3
Vss
28
27
26
25
23
24
22
21
20
19
18
17
16
15
1
2
3
4
6
5
7
8
9
10
11
12
13
14
Vcc
A13
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
WE
OE
CS
SOJ
GENERAL DESCRIPTION
The T14M256A is a high speed, low power
CMOS static RAM organized as 32,768 x 8 bits
that operates on a single 5-volt power supply.
This device is packaged in a standard 28-pin 300
mil SOJ or TSOP-I forward.
BLOCK DIAGRAM
DECODER
CONTROL
V
SS
Vcc
DATA I/O
CORE
ARRAY
I/O 1
.
.
.
I/O 8
.
.
.
A 0
A 14
CS
OE
WE
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A14
Address Inputs
I/O1 - I/O8
Data Inputs/Outputs
CS
Chip Select Inputs
WE
Write Enable
OE
Output Enable
Vcc
Power Supply
Vss
Ground
PART NUMBER EXAMPLES
PACKAGE SPEED
T14M256A-8J SOJ 8ns
T14M256A-8P TSOP-I
8ns
TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
TE
CH
tm
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 2
Publication Date: SEP. 2001
to change products or specifications without notice.
Revision: G
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
Supply Voltage to Vss Pote ntial
-0.5 to + 6
V
Inputs to Vss Potential
-0.5 to Vcc +0.5
V
Power Dissipation
1.0
W
Storage Temperature
-60 to +150
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYM
MIN
TYP
MAX
UNIT
Supply Voltage
Vcc
Typ-5%
5
Typ+5%
V
Input Voltage, low
V
IL
-0.3
-
0.8
V
Input Voltage, high
V
IH
2.2
-
Vcc+0.3
V
Ambient Temperature
T
A
0
-
70
C
Note:
V
IL
(min.) = -2.0V for pulse width
20ns,
V
IH
(max.) = +7.0V for pulse width
20ns.
TRUTH TABLE
CS
OE
WE
MODE
I/O1- I/O8
Vcc
H
X
X
Not Selected
High-Z
I
SB,
I
SB1
L
H
H
Output Disable
High-Z
Icc
L
L
H
Read
Data Out
Icc
L
X
L
Write
Data In
Icc
OPERATING CHARACTERISTICS
(Vcc = 5V
5%, Vss = 0V, Ta = 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Input Leakage Current
I
LI
Vin=Vss to Vcc
-10
-
+10
uA
Output Leakage Current
I
LO
V
I/O
=Vss to Vcc ,
CS
=
V
IH
or
OE
=
V
IH
or
WE
= V
IL
-10
-
+10
uA
Output Low Voltage
V
OL
I
OL
= + 8.0mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= - 4.0mA
2.4
-
-
V
-7
-
-
125
mA
-8
-
-
120
mA
-10
-
-
110
mA
-12
-
-
100
mA
Operating Power
Supply Current
Icc
CS =
V
IL
, I/O=0mA
Cycle = MIN.
Duty = 100%
-15
-
-
90
mA
I
SB
CS
=
V
IH
, Cycle=MIN, Duty=100%
-
-
15
mA
Standby Power
Supply Current
I
SB1
CS
Vcc
-0.2V
-
-
2
mA
Note: Typical characteristics are at Vcc = 5V, Ta = 25
C
TE
CH
tm
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 3
Publication Date: SEP. 2001
to change products or specifications without notice.
Revision: G
CAPACITANCE
(Vcc = 5V, Ta = 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/ Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3 ns
Input and Output Timing Reference Level
1.5V
Output Load
C
L
=30pF,
I
OH
/
I
OL
= -4mA/8mA
AC TEST LOADS AND WAVEFORM
R1 480 ohm
5V
OUTPUT
30pF
Including
Jig and
Scope
R2
255 ohm
R1 480 ohm
5V
OUTPUT
5pF
Including
Jig and
Scope
R2
255
ohm
3.0V
0 V
90%
90%
10%
10%
3ns
3ns
(For T
CLZ
, T
OLZ
, T
CHZ
, T
OHZ
, T
WHZ
, T
OW
)
DQ
Fig.1
Z0 = 50 ohm
50
ohm
30 pF
Vt =1.73V
DQ
Fig.3
Z0 = 50
ohm
50
ohm
5 pF
Vt =1.73V
Fig.2
Fig.4
Fig.5
TE
CH
tm
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date: SEP. 2001
to change products or specifications without notice.
Revision: G
AC CHARACTERISTICS
(
Vcc
=5V
5%, Vss = 0V, Ta = 0 to 70
C)
(1) READ CYCLE
-7
-8
-10
-12
-15
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
t
RC
7
-
8
-
10
-
12
-
15
-
ns
Address Access Time
t
AA
-
7
-
8
-
10
-
12
-
15 ns
Chip Select Access Time
t
ACS
-
7
-
8
-
10
-
12
-
15 ns
Output Enable to Output Valid
t
AOE
- 3.5
-
5
-
6
-
7
-
7 ns
Chip Selection to Output in Low Z
t
CLZ*
2
-
3
-
3
-
3
-
3
-
ns
Output Enable to Output in Low Z
t
OLZ
0
-
0
-
0
-
0
-
0
-
ns
Chip Deselection to Output in High Z
t
CHZ*
- 3.5
-
4
-
5
-
6
0
7 ns
Output Disable to Output in High Z
t
OHZ
- 3.5
-
4
-
5
-
6
0
7 ns
Output Hold from Address Change
t
OH
2
-
2.5
-
3
-
3
-
3
-
ns
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
-7
-8
-10
-12
-15
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
t
WC
7
-
8
-
10
-
12
-
15
-
ns
Chip Selection to End of Write
t
CW
5
-
6
-
8
-
10
-
11
-
ns
Address Valid to End of Write
t
AW
5
-
6
-
8
-
10
-
11
-
ns
Address Setup Time
t
AS
0
-
0
-
0
-
0
-
0
-
ns
Write Pulse Width
t
WP
5
-
6
-
8
-
10
-
11
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
0
-
0
-
ns
Data Valid to End of Write
t
DW
3.5
-
5
-
6
-
8
-
8
-
ns
Data Hold from End of Write
t
DH
0
-
0
-
0
-
0
-
0
-
ns
Write to Output in High Z
t
WHZ
-
3
-
4
-
5
-
6
-
6
ns
Output Disable to Output in High Z
t
OHZ
-
3.5
-
4
-
5
-
6
-
7
ns
Output Active from End of Write
t
OW
0
-
0
-
0
-
0
-
0
-
ns
* These parameters are sampled but not 100% tested.
TE
CH
tm
T14M256A
Taiwan Memory Technology, Inc. reserves the right
P. 5
Publication Date: SEP. 2001
to change products or specifications without notice.
Revision: G
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
t R C
A d d r e s s
t O H
t A A
D O U T
t OH
READ CYCLE 2
(Chip Select Controlled)
t A C S
C S
t C H Z
t C L Z
D O U T
READ CYCLE 3
(Output Enable Controlled)
DON 'T CAR E
UN DEF IN ED
t R C
t C L Z
t C H Z
D O U T
t OH Z
t OH
t A C S
t OL Z
t A OE
t A A
A d d r e s s
C S
O E
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