ChipFind - документация

Электронный компонент: T15V2M08A-70P

Скачать:  PDF   ZIP
TE
CH
tm
Preliminary T15V2M08A
Taiwan Memory Technology, Inc. reserves the right
P. 1
Publication Date: MAR. 2001
to change products or specifications without notice.
Revision:0.A
SRAM
256K X 8 LOW POWER
CMOS STATIC RAM
FEATURES
Low-power consumption
- Active: 40mA at 55ns
- Stand-by: 5uA (CMOS input/output)
55/70/100 ns access time
Equal access and cycle time
Single +2.7V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
Automatic power-down when deselected
Available in 32-pin TSOP-I (8x20mm) ,
TSOP-I(8x13.4mm) , 48-pin CSP packages
PART NUMBER EXAMPLES
PART NO.
PACKAGE CODE
T15V2M08A-55H
T15V2M08A-70P
T15V2M08A-100C
H = TSOP-I(8x20)
P= TSOP-I(8x13.4)
C = CSP
GENERAL DESCRIPTION
The T15V2M08A is a very Low Power
CMOS Static RAM organized as 262,144 words by
8 bits . This device is fabricated by high
performance CMOS technology. It can be
operated under wide power supply voltage range
from +2.7V to +3.6V.
The T15V2M08A inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 2V.
BLOCK DIAGRAM
DECODER
A0
A17
I/O8
Vcc
.
.
.
.
.
DATA I/O
CORE
ARRAY
Vss
I/O1
WE
OE
CE1
CONTROL
CIRCUIT
CE2
TE
CH
tm
Preliminary T15V2M08A
Taiwan Memory Technology, Inc. reserves the right
P. 2
Publication Date: MAR. 2001
to change products or specifications without notice.
Revision:0.A
PIN CONFIGURATIONS

T S O P - I
( 8 x 2 0 m m )
&
( 8 x 1 3 . 4 m m )
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
A 1 1
A 9
A 8
A 1 3
W E
C E 2
A 1 5
V D D
A 1 7
A 1 6
A 1 4
A 1 2
A 7
A 6
A 5
A 4
O E
A 1 0
C E 1
I / O 8
I / O 7
I / O 6
I / O 5
I / O 4
V S S
I / O 3
I / O 2
I / O 1
A 0
A 1
A 2
A 3

A 0
A 1
I / O 5
V D D
V S S
I / O 6
I / O 7
I / O 8
A 9
A 1 0
N C
O E
A 1 7
C E 1
A 1 6
A 1 1
A 1 2
A 1 5
A 1 3
A 1 4
I / O 4
I / O 3
A 5
A 8
V D D
V S S
A 2
I / O 2
I / O 1
C E 2
A 3
A 6
A 7
A 4
W E
N C
A
6
5
4
3
2
1
H
G
F
E
D
C
B
4 8 - C S P
T O P V I E W

PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A17 Address inputs
OE
Output enable input
I/O0~I/O8 Data inputs/outputs
V
DD
Power supply
CE1
,
CE2 Chip enable
V
SS
Ground
WE
Write enable input
NC
No connection
TE
CH
tm
Preliminary T15V2M08A
Taiwan Memory Technology, Inc. reserves the right
P. 3
Publication Date: MAR. 2001
to change products or specifications without notice.
Revision:0.A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYM
MIN.
MAX.
UNIT
Voltage on Any Pin Relative to Gnd
V
R
-0.5
+4.6 V
V
Power Dissipation
P
D
-
0.7
W
Storage Temperature
T
STG
-55
+150
C
Temperature Under Bias
I
BIAS
-40
+85
C
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
CE 1
CE2
WE
OE
DATA
MODE
H
X
X
X
High-Z
Standby
X
L
X
X
High-Z
Standby
L
H
H
L
Data Out
Active, Read
L
H
H
H
High-Z
Active, Output Disable
L
H
L
X
Data In
Acitve, Write
*Note: X = Don't Care, L = Low, H = High
TE
CH
tm
Preliminary T15V2M08A
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date: MAR. 2001
to change products or specifications without notice.
Revision:0.A
OPERATING CHARACTERISTICS
(Vcc = 2.7 to 3.6V, Gnd = 0V, Ta = -40
C to 85
C)
-55
-70
-100
PARAMETER SYM.
TEST CONDITIONS
Min
Max
Min
Max
Min
Max
UNIT
Input Leakage
Current
I
LI
Vcc = Max,
V
IN
= Gnd to Vcc
-
1
-
1
-
1
uA
Output Leakage
Current
I
LO
CE1
= V
IH
or CE2= V
IL
or OE= V
IH
or
WE
= V
IL
V
OUT
= Gnd to Vcc
-
1
-
1
-
1
uA
Operating Power
Supply Current
I
CC
CE1
= V
IL
,CE2= V
IH,
WE
=V
IH,
OE
= V
IH
,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
-
2
-
2
-
2
mA
I
CC1
Cycle time=1us,
100% duty, I
OUT
=0mA,
CE1
0.2V,
CE2
V
CC
-0.2V,
V
IN
0.2V
-
3
-
3
-
3
mA
Average Operating
Current
I
CC2
Cycle time=min,
100% duty, I
OUT
=0mA,
CE1
= V
IL
,CE2= V
IH ,
V
IN
= V
IH
or V
IL
-
40
-
35
-
25
mA
Standby Power
Supply Current
(TTL Level)
I
SB
CE1
=
V
IH
CE2= V
IL
-
0.5
-
0.5
-
0.5
mA
Standby Power
Supply Current
(CMOS Level)
I
SB1
CE1
Vcc-0.2V,
CE2
V
CC
-0.2V
or CE2
0.2V
V
IN
0.2V or
V
IN
Vcc-0.2V
-
5
-
5
-
5
uA
Output Low Voltage
V
OL
I
OL
= 2.0mA
-
0.4
-
0.4
-
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0 mA
2.2
-
2.2
-
2.2
-
V
TE
CH
tm
Preliminary T15V2M08A
Taiwan Memory Technology, Inc. reserves the right
P. 5
Publication Date: MAR. 2001
to change products or specifications without notice.
Revision:0.A
RECOMMENDED OPERATING CONDITIONS
(Ta = -40
C to 85
C**)
PARAMETER
SYM
MIN
TYP
MAX
UNIT
Vcc
2.7
3.0
3.6
V
Supply Voltage
Gnd
0.0
0.0
0.0
V
V
IH
2.1
-
Vcc+0.3
V
Input Voltage
V
IL
-0.3
-
0.6
V

CAPACITANCE
(f = 1 MHz, Ta = 25
C,)
PARAMETER
SYMBOL
CONDITION
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/ Output Capacitance
C
I/O
V
IN
=
V
OUT
= 0V
8
pF
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0.6V to 2.1V
Input Rise and Fall Times
3.0 ns
Input and Output Timing Reference Level
1.4V
C
L
=30pF+1TTL Load(55ns/70ns)
Output Load
C
L
=100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
D Q
Z
0
= 5 0 o h m
5 0 o h m
3 0 p F
V t = 1 . 4 V
F i g . A * I n c l u d i n g S c o p e a n d J i g C a p a c i t a n c e
T T L
C
L
*
F i g . B O u t p u t L o a d E q u i v a l e n t
R
L
C
L