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Электронный компонент: T221160A

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TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 1
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
DRAM
64K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
High speed access time : 25/30/35/40 ns
Industry-standard x 16 pinouts and timing
functions.
Single 5V (
10%) power supply.
All device pins are TTL- compatible.
256-cycle refresh in 4ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Conventional FAST PAGE MODE access cycle.
BYTE WRITE and BYTE READ access cycles.

PART NUMBER EXAMPLES
PART NUMBER
ACCESS TIME PACKAGE
T221160A-30J
30ns SOJ
T221160A-30S
30ns TSOP-II
T221160A-35J
35ns SOJ
T221160A-35S
35ns TSOP-II

GENERAL DESCRIPTION
The T221160A is a randomly accessed solid state
memory containing 1,048,551 bits organized in a
x16 configuration. The T221160A has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The
T221160A
CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (IO1~IO8), and CASH
transiting low will write data into the upper byte
(IO9~16).
PIN ASSIGNMENT ( Top View )
I/01
V cc
I/02
I/03
I/04
I/05
V cc
I/06
I/07
I/08
N C
N C
N C
A 0
A 1
V cc
A 2
A 3
W E
R AS
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/016
Vss
I/015
I/014
I/013
I/012
Vss
I/011
I/010
I/09
N C
N C
A7
A6
VS S
A5
A4
C AS L
C AS H
O E
SOJ
I/01
V cc
I/02
I/03
I/04
I/05
V cc
I/06
I/07
I/08
N C
N C
N C
A 0
A 1
V cc
A 2
A 3
W E
R A S
4 0
3 9
3 8
3 7
3 5
3 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
1
2
3
4
6
5
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
I/01 6
V ss
I/01 5
I/01 4
I/01 3
I/01 2
V ss
I/01 1
I/01 0
I/09
N C
N C
A 7
A 6
V S S
A 5
A 4
C A S L
C A S H
O E
T S O P (II)
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 2
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
FUNCTIONAL BLOCK DIAGRAM
NO.2 CLOCK
GENERATOR
COLUM N.
ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW .
ADDRESS
BUFFERS(8)
NO.1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
DATA-
OUT
BUFFER
COLUM N
DECODER
RO
W
DE
CO
DE
R
256 x 256 x 16
M EM ORY
ARRA
Y
SENSE AM PLIFIERS
VO GATING
16
256 x 16
256
A0
A1
A2
A3
A4
A5
A6
A7
256
RAS
CAS
DQ01
.
.
DQ16
OE
16
8
8
8
8
8
8
8
CASH
CASL
W E
Vcc
Vss
PIN DESCRIPTIONS
PIN NO.
SYM.
TYPE
DESCRIPTION
16~19,22~25 A0-A7
Input
Address
Input
14
RAS
Input
Row Address Strobe
28
CASH
Input
Column Address Strobe /Upper Byte Control
29
CASL
Input
Column Address Strobe /Lower Byte Control
13
WE
Input Write
Enable
27
OE
Input Output
Enable
2~5,6~10,31~34,36~39
I/O1 - I/O16 Input/ Output Data Input/ Output
1,6,20 Vcc
Supply
Power,
5V
21,35,40 Vss
Ground
Ground
11,12,15,30 NC -
No
Connect
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 3
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS... ... -1V to 7V
Operating Temperature, Ta (ambient)..0
C to +70
C
Storage Temperature (plastic)....... -55
C to +150
C
Power Dissipation ........................................... 1.0W
Short Circuit Output Current.......................... 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
C
Ta
70
C; VCC = 5V
10 % unless otherwise noted)
DESCRIPTION CONDITIONS
SYM.
MIN
MAX
UNITS
NOTES
Supply Voltage
Vcc
4.5
5.5
V
1
Supply Voltage
Vss
0
0
V
Input High (Logic) voltage
VIH 2.4 Vcc+1 V 1
Input Low (Logic) voltage
VIL -1.0 0.8
V
1
Input Leakage Current
0V
VIN
7V
ILI -10 10 uA
Output Leakage Current
0V
VOUT
7V
Output(s) disabled
ILO -10 10 uA
Output High Voltage
IOH = -5 mA
VOH 2.4
-
V
Output Low Voltage
IOL = 4.2 mA
VOL - 0.4 V
Note: 1.All Voltages referenced to Vss
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 4
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
DC CHARACTERISTICS
(Ta = 0 to 70
C, Vcc = 5V
10%, Vss = 0V)
-25 -30 -35 -40
Parameter
Symbol
Min Max Min Max Min Max Min Max
Unit
Test Condition
Operating Current
Icc1 - 170 - 150 - 130 - 120 mA
RAS , CAS cycling
tRC=min
Standby Current
Icc2 - 4 - 4 - 4 - 4 mA
TTL interface,
RAS , CAS =VIH,
DOUT=High-Z
Standby Current
Icc3 - 2 - 2 - 2 - 2 mA
CMOS interface,
RAS , CAS > Vcc-0.2V
Fast Page Mode Current
Icc4 - 170
- 150
- 130
- 120
mA
RAS =VIL, CAS
cycling, tPC= min
RAS -only refresh
Current
Icc5 - 170
- 150
- 130
- 120
mA
CAS =VIH, RAS
cycling, tRC= min
CAS Before RAS
Refresh Current
Icc6 - 170
- 150
- 130
- 120
mA
RAS , CAS cycling,
tRC= min
Note: Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25
C, Vcc =5V, f = 1M HZ)
Parameter Symbol
Typ
Max
Unit
Input Capacitance
(address)
CI1 - 5 pF
Input Capacitance
( RAS , CAS , WE , OE )
CI2 - 7 pF
Output Capacitance
(data-in/out)
CI/O - 10 pF
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 5
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
AC CHARACTERISTICS
(note 1,2,3) (Ta = 0 to 70
C)
AC TEST CONDITIONS:
Vcc=5V
10%, input pulse level = 0 to 3V
Input rise and fall times: 2ns
Output Load: 2TTL gate + CL (50pF)
-25 -30 -35 -40
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Notes
Read or Write Cycle Time
tRC 43 55 65 75 ns
Read-Modify-Write Cycle Time
tRWC 65 85 95 105 ns
Fast-Page-Mode Read or Write Cycle Time
tPC 15 20 23 25 ns
Fast-Page-Mode Read-Write Cycle Time
tPCM 37 42 49 52 ns
Access Time From RAS
tRAC 25 30 35 40 ns
4
Access Time From CAS
tCAC 7 8 9 10
ns
5
Access Time From OE
tOAC 7 8 9 10
ns
13
Access Time From Column Address
tAA 12 16 18 20 ns
8
Access Time From CAS Precharge
tACP 14 18 20 22 ns
RAS Pulse Width
tRAS 25 10K 30 10K 35 10K 40 10K ns
RAS Pulse Width
tRASC 25
100K
30
100K
35
100K
40
100K
ns
RAS Hold Time
tRSH 7 8 9 10 ns
RAS Precharge Time
tRP 15 20 23 25 ns
CAS Pulse Width
tCAS 4 10K 6 10K 8 10K 10 10K ns
CAS Hold Time
tCSH 21 26 30 35 ns
CAS Precharge Time
tCP 3 3 4 5 ns
RAS to CAS Delay Time
tRCD 10 17 10 21 10 25 10 29 ns
7
CAS to RAS Precharge Time
tCRP 3 3 3 5 ns
Row Address Setup Time
tASR 0 0 0 0 ns
Row Address Hold Time
tRAH 5 5 5 5 ns
RAS to Column Address Delay Time
tRAD 8 13 8 14 8 16 8 18 ns
8
Column Address Setup Time
tASC 0 0 0 0 ns
Column Address Hold Time
tCAH 4 4 4 5 ns
Column Address Hold Time (Reference to
RAS )
tAR 22 26 30 34
ns
Column Address to RAS Lead Time
tRAL 12 14 16 18 ns
Read Command Setup Time
tRCS 0 0 0 0 ns
14
Read Command Hold Time Reference to CAS tRCH 0 0 0 0 ns
9,14
Read Command Hold Time Reference to RAS
tRRH 0 0 0 0 ns
9
CAS to Output in Low-Z
tCLZ 3 3 3 3 ns
Output Buffer Turn-off Delay From CAS or
RAS
tOFF1 3 15 3 15 3 15 3 15
ns
10,16
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 6
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
AC CHARACTERISTICS
(continued)
-25 -30 -35 -40
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX MIN MAX UNIT
Notes
Output Buffer Turn-off OE to
tOFF2
- 6 - 8 - 8 - 8 ns
16
Write Command Setup Time
tWCS 0 0 0 0 ns
11,14
Write Command Hold Time
tWCH 4 4 4 6 ns
Write Command Hold Time (Reference
to RAS )
tWCR 22 26 30 34 ns
14
Write Command Pulse Width
tWP 4 4 4 6 ns
14
Write Command to RAS Lead Time
tRWL 5 6 7 9 ns
14
Write Command to CAS Lead Time
tCWL 5 6 7 8 ns
14
Data-in Setup Time
tDS 0 0 0 0 ns
12
Data-in Hold Time
tDH 4 4 4 5 ns
12
Data-in Hold Time (Reference to RAS )
tDHR 22 26 30 34 ns
RAS to WE Delay Time
tRWD 34 46 51 56 ns
11
Column Address to WE Delay Time
tAWD
21 29 31 35 ns
11
CAS to WE Delay Time
tCWD
17 24 25 27 ns
11
Transition Time (rise or fall)
tT
1.5 50 1.5 50 2.5 50 2.5 50 ns
2,3
Refresh Period (256 cycles)
tREF 4 4 4 4 ms
RAS to CAS Precharge Time
tRPC 10 10 10 10 ns
CAS Setup Time (CBR REFRESH)
tCSR 5 10 10 10 ns
6
CAS Hold Time (CBR REFRESH)
tCHR 7 10 10 10 ns
6
OE Hold Time From WE During Read-
Modify-Write Cycle
tOEH 4 4 4 5 ns
15
OE Setup Prior to RAS During Hidden
Refresh Cycle
tORD 0 0 0 0 ns











TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 7
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
Notes:
1. An initial pause of 200us is required after
power-up followed by eight RAS refresh
cycles ( RAS only or CBR) before proper
device operation is assured. The eight RAS
cycle wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
2. VIH(2.4V) and VIL(0.8V) are reference levels
for measuring timing of input signals.
Transition times are measured between
VIH(2.4V) and VIL(0.8V).
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that tRCD < tRCD(max). If tRCD is
greater than the maximum recommended value
shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
5. Assume that tRCD
tRCD(max) .
6. Enables on-chip refresh and address counters.
7. Operation within the tRCD(max) limit ensures
that tRAC(max) can be met. tRCD(max) is
specified as a reference point only; if tRCD is
greater than the specified tRCD(max) limit,
access time is controlled by tCAC.
8. Operation within the tRAD limit ensures that
tRAC(max) can be met. tRAD(max) is
specified as a reference point only; if tRAD is
greater than the specified tRAD(max) limit,
access time is controlled by tAA.
9. Either tRCH or tRRH must be satisfied for a
READ cycle.
10. tOFF1(max) defines the time at which the
output achieves the open circuit condition; it is
not a reference to VOH or VOL.
11. tWCS, tRWD, tAWD and tCWD are
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If tWCS
tWCS(min), the cycle is an
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If tRWD
tRWD(min), tAWD
tAWD(min) and tCWD
tCWD(min), the
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until CAS and
RAS or OE go back to VIH) is indeterminate.
OE held high and WE taken low after CAS
goes low result in a LATE WRITE ( OE -
controlled) cycle.
12. These parameters are referenced to CAS
leading edge in EARLY WRITE cycles and
WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
13. During a READ cycle, if OE is low then
taken HIGH before CAS goes high, I/O goes
open, if OE is tied permanently low, a LATE
WRITE or READ-MODIFY-WRITE
operation is not possible.
14. WRITE command is defined as WE going
low.
15. LATE WRITE and READ-MODIFY-WRITE
cycles must have both tOFF2 and tOEH met
( OE high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.
16. The I/Os open during READ cycles once
tOFF1 or tOFF2 occur.

TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 8
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
READ CYCLE
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
ADDR
V
IH
V
IL
WE
V
IOH
V
IOL
I/O
V
IH
V
IL
OE
CAS
VAILD DATA
COLUMN
ROW
ROW
t
RC
t
RAS
t
RP
t
RRH
t
CSH
t
RSH
t
CAS
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
t
AR
t
RCH
t
RCS
t
AA
t
RAC
t
CAC
t
CLZ
t
OFF1
NOTE1
t
OFF2
t
OAC
OPEN
OPEN
t
CRP

EARLY WRITE CYCLE
V
IH
V
IL
RAS
V
IH
V
IL
V
IH
V
IL
ADDR
V
IH
V
IL
WE
V
IOH
V
IOL
I/O
V
IH
V
IL
OE
VAILD DATA
COLUMN
ROW
ROW
tRC
tRAS
tRP
tRSH
tCSH
tCAS
tRCD
tCRP
tASR
tRAH
tRAD
tASC
tAR
tRAL
tCSH
tWP
tWCH
tWCS
tWCR
tRWL
tDHR
tDH
tDS
DON'T CARE
UNDEFINED
tCWL
tCRP
RAS
Note: t
OFF1
is referenced from the rising edge of
RAS
or
CAS
, whichever occurs last.
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 9
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
ROW
COLUMN
ROW
VAILD D
IN
VAILD D
OUT
V
IH
V
IL
RAS
V
IH
V
IL
CAS
V
IH
V
IL
ADDR
V
IH
V
IL
WE
V
IOH
V
IOL
I/O
V
IH
V
IL
OE
tRWC
tRAS
tRP
tCSH
tRSH
tCAS
tRCD
tCRP
tASR
tRAH
tRAD
tAR
tASC
tCAH
tRAL
tCWL
tRWL
tWP
tRWD
tCWD
tAWD
tRCS
tAA
tRAC
tCAC
tCLZ
tOAC
tOFF2
tOEH
tDH
tDS
tCRP
FAST-PAGE-MODE READ CYCLE
t R A S C
t C R P
t C S H
t R C D
t C A S
t P C
t C P
t C A S
t C P
t C A S
t R S H
t R P
t C P N
t A S R
t R A H
t A S C
t
R A D
t
A R
t C A H
t A S C
t C A H
t C A H
t A S C
t
R A L
R O W
C O L U M N
C O L U M N
C O L U M N
R O W
V
I H
V
I L
R A S
V
I H
V
I L
C A S
V
I H
V
I L
A D D R
V
I H
V
I L
W E
V
I O H
V
I O L
I / O
V
I H
V
I L
O E
t R C S
t R R H
t R C H
t O F F 1
t C L Z
t C A C
t A C P
t A A
t A A
t A C P
t C A C
t C L Z
t C A C
t R A C
t A A
t O A C
t
O A C
t
O F F 2
V A I L D
D A T A
V A I L D
D A T A
V A I L D
D A T A
O P E N
O P E N
D O N ' T C A R E
U N D E F I N E D
t C R P
t O F F 1
t O F F 1
t C L Z
t
O A C
t
O F F 2
t
O F F 2
Note: 1. t
OFF1
is referenced from the rising edge of RAS or CAS , whichever occurs last.
2. t
PC
can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of
CAS to rising edge of CAS . Both measurements must meet the t
PC
specification.
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 10
Publication Date:FEB. 2002
to change products or specifications without notice.
Revision:A
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
RASC
t
CRP
t
CSH
t
RCD
t
CAS,
t
CLCH
t
PC
t
CP
t
CAS,
t
CLCH
t
CP
t
CAS,
t
CLCH
t
RSH
t
RP
t
CPN
t
ASR
t
RAH
t
ASC
t
RAD
t
AR
t
CAH
t
ASC
t
CAH
t
CAH
t
ASC
t
RAL
t
WCS
t
CWL
t
WCH
t
WP
t
WCS
t
CWL
t
WCH
t
WP
t
WCS
t
CWL
t
WCH
t
WP
t
RWL
t
DH
t
DS
t
DS
t
DH
t
DH
t
DS
t
WCR
t
DHR
ROW
COLUMN
COLUMN
COLUMN
ROW
VALID DATA
VALID DATA
VALID DATA
V
IH
V
IL
RAS
V
IH
V
IL
CAS
V
IH
V
IL
ADDR
V
IH
V
IL
WE
V
IOH
V
IOL
I/O
V
IH
V
IL
OE
t
CRP
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRASC
tCRP
tCSH
tRCD
tCAS,tCLCH
tPCM
tCP
tCAS,tCLCH
tCP
tCAS,tCLCH
tRSH
tRP
tCPN
tASR
tRAH
tASC
tRAD
t
AR
tCAH
tASC
tCAH
tCAH
tASC
tRAL
ROW
COLUMN
COLUMN
COLUMN
ROW
V
IH
V
IL
RAS
V
IH
V
IL
CAS
V
IH
V
IL
ADDR
V
IH
V
IL
WE
V
IOH
V
IOL
I/O
V
IH
V
IL
OE
tRWD
tRCS
tCWL
tWP
tAWD
tCWD
tAWD
tWP
tCWL
tCWD
tCWD
tWP
tCWL
tRWL
tAA
tRAC
tCAC
tCLZ
tDS
tDH
tAA
tACP
tCAC
tCLZ
tCLZ
tCAC
tACP
tDS
tDH
tAA
tDH
tDS
tOAC
tOFF2
tOAC
tOFF2
tOAC
tOFF2
tOEH
DON'T CARE
UNDEFINED
VAILD
D OUT
VAILD
D IN
VAILD
D OUT
VAILD
D IN
VAILD
D OUT
VAILD
D IN
tCRP
Note: t
PC
can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of
CAS . Both measurements must meet the t
PC
specification.
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 11
Publication Date:FEB. 2002
to change products or specifications without notice.
Revision:A
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tR A S C
tC R P
tC S H
tR C D
tC A S
tP C
tC P
tC A S
tC P
tC A S
tR S H
tR P
tC P
tA S R
tR A H
tA S C
t
R A D
tA R
tC A H
tA S C
tC A H
tC A H
tA S C
t
R A L
R O W
C O L U M N
C O L U M N
C O L U M N
R O W
V
IH
V
IL
R A S
V
IH
V
IL
C A S
V
IH
V
IL
A D D R
V
IH
V
IL
W E
V
IO H
V
IO L
I /O
V
IH
V
IL
O E
tP C
tR C S
t
R C H
tW C S
tW C H
t
A A
tR A C
tC A C
tA C P
tC A C
tA A
tD H
tD S
t
O A C
O P E
N
tC R P
tO F F 1
t
C L Z
t
O F F 1
V A IL D
D A T A (A )
V A IL D
D A T A (B )
V A IL D
D A T A IN


RAS
ONLY REFRESH CYCLE
(ADDR=A0-A7 ;
OE
,
WE
=DON`T CARE)
V
IH
V
IL
RAS
V
IH
V
IL
CAS
V
IH
V
IL
ADDR
V
OH
V
OL
I/O
OPEN
ROW
ROW
tASR
tRAH
tCRP
tRPC
tRP
tRAS
tRC
DON'T CARE
UNDEFINED
tOFF
Note1:Do not drive data prior to tristate.
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 12
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
CBR REFRESH CYCLE
(A0-A7 ;
OE
=DON`T CARE)
V
IH
V
IL
RAS
V
IH
V
IL
I/O
V
IH
V
IL
WE
CAS
t
RP
t
RAS
t
RP
t
RAS
t
CHR
t
CSR
t
RPC
t
CHR
t
CSR
t
CPN
t
RPC
OPEN
t
OFF
t
RC

HIDDEN REFRESH CYCLE
(
WE
=HIGH ;
OE
=LOW)
V
I H
V
I L
R A S
V
I H
V
I L
V
I H
V
I L
A D D R
V
I O H
V
I O L
I / O
V
I H
V
I L
O E
C A S
V A I L D D A T A
R O W
C O L U M N
t R A S
t R P
t R A S
t C H R
t R S H
t R C D
t C R P
t A S R
t R A H
t R A D
t A R
t R A L
t A S C
t C A H
t A A
t R A C
t C A C
t C L Z
t O A C
t O R D
t O F F 2
t O F F 1
N O T E 1
O P E N
O P E N
D O N ' T C A R E
U N D E F I N E D
t R P
( R E F R E S H )
t R C
( R E A D )
t R C
Note: 1. t
OFF1
is referenced from the rising edge of
RAS
or
CAS
, whichever occurs last.
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 13
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
PACKAGE DIMENSIONS
40-LEAD SOJ DRAM (400 mil)

1
20
21
40
C
y
J
B
A
D
Seating
Plane
F
E
10X(MAX
)
I
H
L
K
G

SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
A 1.025
0.010 26.035
0.254
B 0.400
0.005 10.160
0.127
C 0.045(MAX)
1.143(MAX)
D 0.050
0.006 1.27
0.152
E 0.019
0.003 0.483
0.08
F 0.026
0.003 0.661
0.080
G 0.440
0.010 11.176
0.254
H 0.011
0.003 0.280
0.080
I 0.025(MIN)
0.635(MIN)
J 0.364
0.020 9.246
0.508
K 0.047
0.006 1.194
0.152
L 0.150(MAX)
3.810(MAX)
y 0.004(MAX)
0.102(MAX)
TE
CH
tm
T221160A
Taiwan Memory Technology, Inc. reserves the right P. 14
Publication Date: FEB. 2002
to change products or specifications without notice.
Revision:A
PACKAGE DIMENSIONS
40-LEAD TSOP II DRAM (400 mil)
S E A T IN G P L A N E
E E 1
D
b
e
A
A 2
A 1
L 1
L
y
1
2 0
2 1
4 0
SYMBOL
DIMENSIONS IN INCHES
DIMENSIONS IN MM
A 0.047(max)
1.20(max)
A1 0.0040.002
0.100.05
A2 0.0390.002
1.000.05
b 0.014(typ.)
0.35(typ.)
e 0.0315(typ.)
0.80typ.)
D 0.7250.004
18.410.10
E 0.4630.008
11.760.20
E1 0.4000.004
10.160.10
L1 0.031
0.80
L 0.0200.004
0.5000.10
y 0.004(max)
0.10(max)
0
~5
0
~5