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Электронный компонент: T2316162A-60

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TE
CH
tm
T2316162A
TM Technology Inc. reserves the right P. 1
Publication Date: APR. 2002
to change products or specifications without notice.
Revision:E
DRAM
1024K x 16 DYNAMIC RAM
EDO PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (
10%) power supply.
All device pins are TTL- compatible.
1K-cycle refresh in 16ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE access
cycle.
BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING MARKING
45ns
-45
50ns -50
60ns
-60
PACKAGE
42-pin SOJ
J
44/50-pin
TSOPII
S
GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The
T2316162A
CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (DQ0~DQ7), and CASH
transiting low will write data into the upper byte
(DQ8~DQ15).
PIN ASSIGNMENT ( Top View )
DQ1
V
DD
46
45
44
43
41
42
40
36
35
34
33
32
31
30
29
1
2
3
4
6
5
7
8
9
11
15
16
17
18
19
20
DQ11
DQ10
DQ9
A8
A7
A9
10
21
22
47
48
49
50
DQ2
DQ3
A0
A1
DQ15
DQ14
DQ8
Vss
23
24
25
28
27
26
V
DD
DQ0
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
WE
RAS
NC
NC
A2
A3
V
DD
DQ13
DQ12
Vss
NC
NC
OE
CASL
CASH
Vss
A6
A5
A4
40
39
38
37
35
36
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
6
5
7
8
9
11
12
13
14
15
16
17
18
19
20
10
21
41
42
22
DQ1
V
DD
DQ2
DQ3
A0
A1
V
DD
DQ0
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A2
A3
V
DD
DQ11
DQ10
DQ9
A8
A7
A9
DQ15
DQ14
DQ8
Vss
DQ13
DQ12
Vss
NC
OE
CASL
CASH
Vss
A6
A5
A4
TE
CH
tm
T2316162A
TM Technology Inc. reserves the right P. 2
Publication Date: APR. 2002
to change products or specifications without notice.
Revision:E
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTIONS
SYM. TYPE
DESCRIPTION
A0-A9 Input
Address
Input
RAS
Input
Row Address Strobe
CASH
Input
Column Address Strobe /Upper Byte Control
CASL
Input
Column Address Strobe /Lower Byte Control
WE
Input Write
Enable
OE
Input Output
Enable
DQ0 DQ15
Input/ Output Data Input/ Output
Vcc Supply
Power,
5V
Vss Ground
Ground
NC -
No
Connect
NO.2 CLOCK
GENERATOR
COLUMN.
ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW.
ADDRESS
BUFFERS(10)
NO.1 CLOCK
GENERATOR
CONTROL
LOGIC
DATA-IN BUFFER
DATA-OUT
BUFFER
COLUMN
DECODER
ROW
DECODER
1024x 1024 x 16
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
16
1024x 16
1024
A0
A1
A2
A3
A4
A5
A6
A7
A8
1024
RAS
CAS
DQ0
.
.
DQ15
OE
1
6
16
10
10
10
10
10
CASH
CASL
WE
Vcc
Vss
A9
TE
CH
tm
T2316162A
TM Technology Inc. reserves the right P. 3
Publication Date: APR. 2002
to change products or specifications without notice.
Revision:E
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS.... -1V to +7V
Operating Temperature, Ta (ambient).....
.........0
C to +70
C
Storage Temperature (plastic)...... -55
C to +150
C
Power Dissipation ........................................ 1.2W
Short Circuit Output Current........................ 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
C
Ta
70
C; VCC = 5V
10 % unless otherwise noted)
DESCRIPTION CONDITIONS
SYM.
MIN
MAX
UNITS
NOTES
Supply Voltage
Vcc
4.5
5.5
V
1
Supply Voltage
Vss
0
0
V
Input High (Logic) voltage
VIH 2.4 Vcc+1 V 1
Input Low (Logic) voltage
VIL -1.0 0.8
V
1
Input Leakage Current
0V
VIN
7V
ILI -10 10 uA
Output Leakage Current
0V
VOUT
7V
Output(s) disabled
ILO -10 10 uA
Output High Voltage
IOH = -5 mA
VOH 2.4 Vcc
V
Output Low Voltage
IOL = 4.2 mA
VOL 0 0.4 V
Note: 1.All Voltages referenced to Vss
MAX
DESCRIPTION CONDITIONS
SYM.
-45
-50
-60
UNITS
NOTES
Operating Current
RAS , CAS cycling , tRC = min
Icc1 190 180 170 mA 1,2
TTL Standby Current
TTL interface, RAS ,
CAS =VIH, DOUT=High-Z
Icc2 2 2 2 mA
RAS -only refresh Current tRC = min
Icc3 190 180 170 mA
2
EDO Page Mode Current
tPC = min
Icc4 150 140 130 mA 1,3
CAS Before RAS Refresh
Current
tRC = min
Icc5 190 180 170
mA
CMOS Standby Current
CMOS interface, RAS , CAS >Vcc-
0.2V
Icc6 1.0 1.0 1.0 mA
1
Note: 1. Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition.
2. Address can be changed twice or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
TE
CH
tm
T2316162A
TM Technology Inc. reserves the right P. 4
Publication Date:APR. 2002
to change products or specifications without notice.
Revision:E
CAPACITANCE
(Ta =25
C, Vcc =5V
10 %)
Parameter Symbol
Typ
Max
Unit
Notes
Input Capacitance (address)
CI1 - 5 pF 1
Input Capacitance (clocks)
CI2 - 7 pF 1
Output Capacitance (data-in, data-out)
CDQ - 10 pF 1
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
AC ELECTRICAL CHARACTERISTICS
(note 14)
(Ta =0 to 70
C, Vcc=5V
10 %, Vss=0V)
Test Conditions (note 29)
-45
-50 -60
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX
UNIT Notes
Read or Write Cycle Time
tRC 80 84 110 ns
Read Write Cycle Time
tRWC
105 113 140 ns
EDO-Page-Mode Read or Write Cycle Time
tPC 16 20 25 ns
22
EDO-Page-Mode Read-Write Cycle Time
tPCM 46 58 70 ns
22
Access Time From RAS
tRAC 45 50 60 ns
4
Access Time From CAS
tCAC 11 13 15 ns
5,20
Access Time From OE
tOAC 11 13 15 ns
13,20
Access Time From Column Address
tAA 19 25 30 ns
Access Time From CAS Precharge
tACP 22 27 35 ns
20
RAS Pulse Width
tRAS 45 10K 50 10K 60 10K ns
RAS Pulse Width (EDO Page Mode)
tRASC 45 100K 50 100K 60 100K ns
RAS Hold Time
tRSH 11 13 15 ns
27
RAS Precharge Time
tRP 28 30 40 ns
CAS Pulse Width
tCAS 6 10K 8 10K 15 10K ns 26
CAS Hold Time
tCSH 40 40 60 ns
19
CAS Precharge Time (EDO Page Mode)
tCP 5 6 10 ns
23
RAS to CAS Delay Time
tRCD 10 34 12 37 20 45 ns 7,18
CAS to RAS Precharge Time
tCRP 5 5 5 ns
19
Row Address Setup Time
tASR 0 0 0 ns
Row Address Hold Time
tRAH 5 8 10 ns
RAS to Column Address Delay Time
tRAD 8 26 10 28 12 30 ns 8
Column Address Setup Time
tASC 0 0 0 ns
18
Column Address Hold Time
tCAH 6 8 10 ns
18
Column Address Hold Time (Reference to
RAS )
tAR 35 38 45 ns
Column Address to RAS Lead Time
tRAL 19 23 30 ns
TE
CH
tm
T2316162A
TM Technology Inc. reserves the right P. 5
Publication Date:APR. 2002
to change products or specifications without notice.
Revision:E
AC ELECTRICAL CHARACTERISTICS
(
continued
)
-45
-50 -60
AC CHARACTERISTICS
PARAMETER
SYM
MIN MAX MIN MAX MIN MAX
UNIT Notes
Read Command Setup Time
tRCS 0 0 0 ns
15,18
Read Command Hold Time Reference to CAS tRCH 0 0 0 ns
9,15,19
Read Command Hold Time Reference to RAS tRRH 0 0 0 ns
9
CAS to Output in Low-Z
tCLZ 3 3 3 ns
20
Output Buffer Turn-off Delay From CAS or
RAS
tOFF1 3 15 3 15 3 15 ns
10,17,
20
Output Buffer Turn-off to OE
tOFF2 8 8 15 ns
17,28
Write Command Setup Time
tWCS 0 0 0 ns
11,15,1
8
Write Command Hold Time
tWCH 6 8 10 ns
15,27
Write Command Hold Time (Reference to
RAS )
tWCR 35 38 45 ns
15
Write Command Pulse Width
tWP 6 8 15 ns
15
Write Command to RAS Lead Time
tRWL 9 9 10 ns
15
Write Command to CAS Lead Time
tCWL 8 8 10 ns
15,19
Data-in Setup Time
tDS 0 0 0 ns
12,20
Data-in Hold Time
tDH 6 8 10 ns
12,20
Data-in Hold Time (Reference to RAS )
tDHR 35 38 45 ns
RAS to WE Delay Time
tRWD 61 64 85 ns
11
Column Address to WE Delay Time
tAWD 35 39 55 ns
11
CAS to WE Delay Time
tCWD 27 27 40 ns
11,18
Transition Time (rise or fall)
tT
2.5 50 2.5 50 2.5 50 ns 2,3
Refresh Period (1024 cycles)
tREF 16 16 16 ms
RAS to CAS Precharge Time
tRPC 10 10 10 ns
CAS Setup Time (CBR REFRESH)
tCSR 10 10 10 ns
1,18
CAS Hold Time (CBR REFRESH)
tCHR 10 10 10 ns
1,19
OE Hold Time From WE During Read-
Modify-Write Cycle
tOEH 6 10 15 ns
16
OE Low to CAS High Setup Time
tOES 5 5 5 ns
OE High Hold Time From CAS High
tOEHC
3 5 10 ns
OE High Pulse Width
tOEP 2 5 10 ns
OE Setup Prior to CAS During Hidden
Refresh Cycle
tORD 0 0 0 ns
Last CAS Going Low to First CAS
Returning High
tCLCH 6 10 10 ns
21
Data Output Hold After CAS Returning Low
tCOH 4 5 5 ns
Output Disable Delay From WE
tWHZ 3 7 3 10 3 15 ns