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TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 1
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision: A
SYNCHRONOUS
BURST SRAM
64K x 32 SRAM
3.3V supply, fully registered inputs and
outputs, burst counter
FEATURES
E
Fast Access times: 4.5, 5, 6, 7, and 8ns
E
Fast clock speed: 125,100, 83, 66, and 50 MHz
E
Provide high performance 3-1-1-1 access rate
E
Fast
OE
access times: 4.5, 5 and 6ns
E
Single 3.3V +10%/-5% power supply
E
Common data inputs and data outputs
E
BYTE WRITE ENABLE and GLOBAL WRITE
control
E
Three chip enables for depth expansion and
address pipelining
E
Address, control, input, and output pipelined
registers
E
Internally self-timed WRITE CYCLE
E
WRITE pass-through capability
E
Burst control pins ( interleaved or linear burst
sequence)
E
High density, high speed packages
E
Low capacitive bus loading
E
High 30pF output drive capability at rated access
time
E
SNOOZE MODE for reduced power standby
E
Single cycle disable ( Pentium
TM
BSRAM
compatible )
OPTIONS
TIMING
MARKING
4.5ns access/8ns cycle
-4.5
5ns access/10ns cycle
-5
6ns access/12ns cycle
-6
7ns access/15ns cycle
-7
8ns access/20ns cycle
-8
Package
100-pin QFP
Q
100-pin TQFP
T
Part Number Examples
PART NO.
Pkg. BURST SEQUENCE
T35L6432A-5Q Q
Interleaved
(MODE=NC or VCC)
T35L6432A-5T
T
Linear (MODE=GND)
PIN ASSIGNMENT (Top View)
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC
NC
DQ1
DQ2
VCCQ
VSSQ
DQ3
DQ4
DQ5
DQ6
VSSQ
VCCQ
DQ7
DQ8
ZZ
VCC
NC
VSS
DQ9
DQ10
VCCQ
VSSQ
DQ11
DQ12
DQ13
DQ14
VSSQ
VCCQ
DQ15
DQ16
NC
1
11
10
9
8
7
6
5
4
3
2
18
17
16
15
14
13
12
28
27
26
25
24
23
22
21
20
19
30
29
31
41
40
39
38
37
36
35
34
33
32
49
48
47
46
45
44
43
42
50
60
59
58
57
56
55
54
53
52
51
70
69
68
67
66
65
64
63
62
61
80
79
78
77
76
75
74
73
72
71
95
96
88 87 86 85 84 83 82 81
90
91
92
93
94
89
100 99 98 97
A7
A6
BWE
GW
CLK
VSS
VCC
CE2
BW1
BW2
BW3
BW4
CE2
CE
ADV
ADSP
ADSC
OE
A9
A8
NC
VCC
NC
NC
A10
A0
NC
VSS
A11
A12
A13
A14
A15
NC
A1
A2
A3
MODE
A4
A5
100-pin QFP
or
100-pin TQFP
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6432A SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 2
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision: A
GENERAL DESCRIPTION
(continued)
chip enable (
CE
), depth- expansion chip enables
(
CE2
and
CE2),burst
control
inputs
(
ADSC
,
ADSP
, and
ADV
), write enables
(
BW1
,
BW2
,
BW3
,
BW4
, and
BWE
), and
global write (
GW
).
Asynchronous inputs include the output
enable (
OE
),Snooze enable (ZZ) and burst mode
control (MODE). The data outputs (Q), enabled
by
OE
, are also asynchronous.
Addresses and chip enables are registered
with either address status processor (
ADSP
) or
address status controller (
ADSC
) input pins.
Subsequent burst addresses can be internally
generated as controlled by the burst advance pin
(
ADV
).
Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to four bytes
wide as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-DQ16.
BW3
controls DQ17-DQ
24.
BW4
controls DQ25-DQ32.
BW1
,
BW2
,
BW3
, and
BW4
can be active only with
BWE
being LOW.
GW
being LOW causes all
bytes to be written. WRITE pass-through
capability allows written data available at the
output for the immediately next READ cycle.
This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing
system performance. The T35L6432A operates
from a 3.3V +10%/-5% power supply. The device
is ideally suited for Pentium
TM
, 680X0, and Power
PC
TM
systems and for systems that are benefited
from a wide synchronous data bus.
FUNCTIONAL BLOCK DIAGRAM
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
BYTE 1
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 2
WRITE REGISTER
ADDRESS
REGISTER
DO D1 Q1
BINARY
COUNTER
& LOGIC
CLR
Q0
BYTE 1
WRITE DRIVER
BYTE 2
WRITE DRIVER
BYTE 3
WRITE DRIVER
BYTE 4
WRITE DRIVER
16
16
14
16
A0
A1
A1'
A0'
64K x 8 x 4
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
INPUT
REGISTERS
8
8
8
8
8
8
8
8
32
32
32
DQ1
E
E
E
DQ32
4
A0-A15
MODE
ADV
CLK
ADSC
ADSP
BW4
BW3
BW2
BW1
CE
CE2
CE2
OE
GW
BWE
PIPELINED
ENABLE
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 3
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
PIN DESCRIPTIONS
QFP PINS
SYM.
TYPE
DESCRIPTION
32-37, 44-49,
A0-
Input-
Addresses: These inputs are registered and must meet the setup and
81, 82, 99, 100,
A15 Synchronous hold times around the rising edge of CLK. The burst counter -
generates internal addresses associated with A0 and A1,during
burst cycle and wait cycle.
93-96
BW1
Input-
Byte Write: A byte write is LOW for a WRITE cyle and HIGH for
BW2 Synchronous a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-
BW3
DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32.
BW4
Data I/O are high impedance if either of these inputs are LOW ,
conditioned by
BWE
being LOW.
87
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the setup and hold times around the rising edge of
CLK.
88
GW
Input-
Global Write: This active LOW input allows a full 32-bit WRITE
Synchronous to occur independent of the BWE and BWn lines and must meet
the setup and hold times around the rising edge of CLK.
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
98
CE
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device and conditions internal use of
ADSP
. This input is
sampled only when a new external address is loaded.
92
CE2
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
97
CE2
Input-
Synchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
86
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
84
ADSP
Input-
Address Status Processor: This active LOW input, along with
CE
Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
85
ADSC
Input-
Address Status Controller:This active LOW input causes device to
Synchronous be deselected or selected along with new external address to be
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 4
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
PIN DESCRIPTIONS
(continued)
QFP PINS
SYM.
TYPE
DESCRIPTION
31
MODE
Input-
Mode: This input selects the burst sequence. A LOW on this pin
Static
selects LINEAR BURST. A NC or HIGH on this pin selects
INTERLEAVED BURST. Do not alter input state while device is
operating.
64
ZZ
Input
Snooze Enable: This active HIGH asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory arry is retained.
2,3,6-9,12,13, 18,
DQ1-
Input/
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is
19,22-25,28,29,52,
DQ32
Output
DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25-
53,56-59,62,63,68,
DQ32. Input data must meet setup and hold times around the
69,72-75,78,79,
rising edge of CLK.
15,41,65,91
VCC
Supply
Power Supply: 3.3V +10%/-5%
17,40,67,90
VSS
Ground Ground: GND
4,11,20,27,54,
61,70,77
VCCQ I/O Supply Output Buffer Supply: 3.3V +10%/-5%
5,10,21,26,55,
60,71,76
VSSQ I/O Ground Output Buffer Ground: GND
1,14,16,30,38,39,
NC
-
No Connect: These signals are not internally conntected.
42,43,50,51,66,80
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 5
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE one byte
H
L
L
H
H
H
WRITE all byte
H
L
L
L
L
L
WRITE all byte
L
X
X
X
X
X
WRITE PASS-THROUGH TRUTH TABLE
PREVIOUS CYCLE
PRESENT CYCLE
NEXT CYCLE
OPERATION
BWn
OPERATION
CE
BWn
OE
OPERATION
Initiate WRITE cycle, all bytes All L2,3 Initiate READ cycle
L
H
L Read D(n)
Address= A(n-1), data= D(n-1)
Register A(n), Q= D(n-1)
Initiate WRITE cycle, all bytes All L2,3 No new cycle
H
H
L No carry-over from
Address= A(n-1), data= D(n-1)
Q = D(n-1)
previous cycle
Initiate WRITE cycle, all bytes All L2,3 No new cycle
H
H
H No carry-over from
Address= A(n-1), data= D(n-1)
Q = HIGH-Z
previous cycle
Initiate WRITE cycle, one bytes ONE L2 No new cycle
H
H
L No carry-over from
Address= A(n-1), data= D(n-1)
Q = D(n-1) for one byte
previous cycle
Note: 1. Previous cycle may be any cycle(non-burst, burst, or wait).
2.
BWE
is LOW for individual byte WRITE.
3.
GW
= LOW yields the same result for all-byte WRITE operation.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 6
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
TRUTH TABLE
OPERATION
ADDRESS
CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
USED
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
X
L
L
L
X
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
H
X
L
L
X
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
X
L
L
H
L
X
X
X
L-H High-Z
Deselected Cycle, Power Down
None
L
H
X
L
H
L
X
X
X
L-H High-Z
Snooze Cycle, Power Down
None
X
X
X
H
X
X
X
X
X
X High-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H High-Z
WRITE Cycle, Continue
Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue
Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Note: 1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or
more byte write enable signals
(
BW1
,
BW2
,
BW3
or
BW4
)
and
BWE
are LOW, or
GW
equals LOW. WRITE= H means all byte write signal are HIGH.
2.
BW1
= enables write to DQ1-DQ8.
BW2
= enables write to DQ9-DQ16.
BW3
= enables write to
DQ17-DQ24.
BW4
=enables write to DQ25-DQ32.
3. All inputs except
OE
must meet setup and hold times around the rising edge ( LOW to HIGH)
of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation.
OE
must be HIGH before the input data
required setup time plus High-Z time for
OE
and staying HIGH throughout the input data hold
time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7.
ADSP
= LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge
of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 7
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS.
............-0.5V to +4.6V
I/O Supply Voltage VccQ ........... Vss -0.5V to Vcc
VIN......................................... -0.5V to Vcc +0.5V
Storage Temperature (plastic)...... -55
C to +150
C
Junction Temperature ............................... +150
C
Power Dissipation ........................................ 1.6W
Short Circuit Output Current...................... 100mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0
C
Ta
70
C; VCC = 3.3V +10%/-5% unless otherwise noted)
DESCRIPTION
CONDITIONS
SYM.
MIN
MAX
UNITS
NOTES
Input High (Logic) voltage
VIH
2
VCCQ + 0.3
V
1, 2
Input Low (Logic) voltage
VIL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
VIN
VCC
ILI
-2
2
A
14
Output Leakage Current
Output(s) disabled, 0V
VOUT
VCC
ILO
-2
2
A
Output High Voltage
IOH = -4.0 mA
VOH
2.4
V
1, 11
Output Low Voltage
IOL = 8.0 mA
VOL
0.4
V
1, 11
Supply Voltage
Vcc
3.1
3.6
V
1
M A
X
DESCRIPTION
CONDITIONS
SYM.TYP -4.5 -5 -6
-7
-8 UNITS NOTES
Power Supply
Device selected; all inputs
VIL or
Icc 200 300 270 230 190 150
mA
3, 12, 13
Current:
VIH; cycle time
tKC MIN; VCC
Operating
= MAX; outputs open
Power Supply
Device selected;
ADSC
,
ADSP
,
ISB1 56 155 140 125 115 110
mA
12, 13
Current: Idle
ADV
,
GW
,
BWE
VIH; all
other
inputs
VIL or
VIH; VCC = MAX;
cycle time
tKC MIN: outputs open
CMOS Standby Device deselected; VCC = MAX; all ISB2 0.5 5
5
5
5
5
mA
12, 13
inputs
VSS + 0.2 or
VCC - 0.2;
all inputs static; CLK frequency =0
TTL Standby
Device deselected; all inputs
VIL ISB3 15 25 25 25 25 25
mA
12, 13
or
VIH; all inputs static; VCC =
MAX;CLK frequency = 0
Clock Running Device deselected; all inputs
VIL ISB4 30 81 81 76 66 51
mA
12, 13
or
VIH; VCC =MAX; CLK cycle
time
tKCMIN
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 8
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
CAPACITANCE
DESCRIPTION
CONDITIONS
SYM.
TYP
MAX
UNITS NOTES
Input Capacitance
TA = 25
C; f = 1 MHz
CI
3
4
pF
4
Input/ Output Capacitance(DQ)
VCC = 3.3V
CO
6
7
pF
4
THERMAL CONSIDERATION
DESCRIPTION
CONDITIONS
SYM. QFP TYP UNITS NOTES
Thermal Resistance - Junction to
Ambient
Still air, soldered on 4.25x
JA
20
C/W
Thermal Resistance - Junction to Case
1.125 inch 4-layer PCB
JB
1
C/W
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0
C
TA
70
C; VCC=3.3V +10%/-5%)
DESCRIPTION
-4.5
-5
-6
-7
-8
SYM. MIN MAX MINMAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Clock
Clock cycle time
tKC
8
10
12
15
20
ns
Clock HIGH time
tKH
3
4
4
5
6
ns
Clock LOW time
tKL
3
4
4
5
6
ns
Output Times
Clock to output valid
tKQ
4.5
5
6
7
8
ns
Clock to output invalid
tKQX
2
2
2
2
2
ns
Clock to output in Low-Z
tKQLZ 2
3
3
3
3
ns
6, 7
Clock to output in High-Z
tKQHZ
4.5
5
5
6
6
ns
6, 7
OE to output valid
tOEQ
4.5
5
5
5
6
ns
9
OE to output in Low-Z
tOELZ 0
0
0
0
0
ns
6, 7
OE to output in High-Z
tOEHZ
3
4
5
6
6
ns
6, 7
Setup Times
Address
tAS
2.5
3
3
3
3
ns
8, 10
Address Status( ADSC , ADSP ) tADSS 2.5
3
3
3
3
ns
8, 10
Address Advance ( ADV )
tAAS 2.5
3
3
3
3
ns
8, 10
Byte Write Enables
( BW1~ BW4 , BWE , GW )
tWS
2.5
3
3
3
3
ns
8, 10
Data-in
tDS
2.5
3
3
3
3
ns
8, 10
Chip Enables( CE , CE2 ,CE2) tCES
2.5
3
3
3
3
ns
8, 10
Hold Times
Address
tAH
0.5
0.5
0.5
0.5
0.5
ns
8, 10
Address Status( ADSC , ADSP ) tADSH 0.5
0.5
0.5
0.5
0.5
ns
8, 10
Address Advance ( ADV )
tAAH 0.5
0.5
0.5
0.5
0.5
ns
8, 10
Byte Write Enables
( BW1~ BW4 , BWE , GW )
tWH
0.5
0.5
0.5
0.5
0.5
ns
8, 10
Data-in
tDH
0.5
0.5
0.5
0.5
0.5
ns
8, 10
Chip Enables( CE , CE2 ,CE2) tCEH
0.5
0.5
0.5
0.5
0.5
ns
8, 10
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 9
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
AC TEST CONDITIONS
Input pulse levels
0V to 3.0V
Input rise and fall times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
Notes:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH
+3.6 V for t
tKC/2.
Undershoot: VIL
-1.0 V for t
tKC/2.
3. Icc is given with no output current. Icc increases
with greater output loading and faster cycle
times.
4. This parameter is sampled.
5. Test conditions as specified with the output
loading as shown in Fig. 1 unless otherwise
noted.
6. Output loading is specified with CL = 5 pF as in
Fig. 2.
7. At any given temperature and voltage condition,
tKQHZ is less than tKQLZ and tOEHZ is less
than tOELZ.
8. A READ cycle is defined by byte write enables
all HIGH or
ADSP
LOW along with chip
enables being active for the required setup and
hold times. A WRITE cycle is defined by at one
byte or all byte WRITE per READ/WRITE
TRUTH TABLE.
9.
OE
is a "don't care" when a byte write enable is
sampled LOW.
10.This is a synchronous device. All synchronous
inputs must meet specified setup and hold time,
except for "don't care" as defined in the truth
table.
11.AC I/O curves are available upon request.
12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth
table. "Device Selected" means the device is
active.
13.Typical values are measured at 3.3V, 25
C and
20ns cycle time.
14.MODE pin has an internal pull-up and exhibits
an input leakage current of
10
A.
OUTPUT LOADS
DQ
DQ
Fig.1 OUTPUT LOAD EQUIVALENT
Fig.2 OUTPUT LOAD EQUIVALENT
Z
0
= 50
50
30 pF
Vt = 1.5V
3.3V
317
351
5 pF
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 10
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
SNOOZE MODE
SNOOZE MODE is a low current, "power
down" mode in which the device is deselected and
current is reduced to I
SB2.
The duration of
SNOOZE MODE is dictated by the length of time
the ZZ pin is in a HIGH state. After entering
SNOOZE MODE, the clock and all other inputs are
ignored. The ZZ pin (pin 64) is an asynchronous,
active HIGH input that causes the device to enter
SNOOZE MODE. When the ZZ pin becomes a
logic HIGH, I
SB2
is guaranteed after the setup time
t
ZZ is met. Any access pending when entering
SNOOZE MODE is not guaranteed to successfully
complete. Therefore, SNOOZE MODE must not
be initiated until valid pending operations are
completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Current during
SNOOZE MODE
ZZ
V
IH
I
SB2
5
mA
ZZ HIGH to
SNOOZE MODE time
tZZ
2(tKC)
ns
4
SNOOZE MODE
Operation Recovery Time
tRZZ
2(tKC)
ns
4
SNOOZE MODE WAVEFORM
C L K
Z Z
tRZZ
tZZ
I
Z Z
I
SUPPLY
DO N'T CARE
C E
I
S UPP LY
Note:
1. The
CE
signal shown above refers to a TRUE state on all chip selects for the device.
2. All other inputs held to static CMOS levels (VIN
Vss + 0.2 V or
Vcc -0.2 V).
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 11
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
READ TIMING
Hig h-Z
BUR S T RE A D
C LK
A DS C
A D S P
A D DRE S S
G W , B W E ,
B W 1- B W 4
t KC
t
KH
t
KL
t A D SS t A DSH
DON'T CARE
UNDEFINED
t A DSS t A D SH
t A S t A H
t W S t WH
t CES t CEH
t A A S t A A H
t O EQ
t KQ X
tOEL Z
tOEHZ
t KQ
t KQHZ
t
KQ
t KQ LZ
S in g le RE A D
(NO TE 3)
Q (A 1)
Q (A 2)
Q(A 2+1)
Q (A 2+2)
Q(A2 +3 )
Q (A 2+1)
Bu rst wr a ps a ro und
to its in ita l sta te.
AD V s usp e nd s bu rs t.
Bur st con tin ue d with
n ew b ase ad d re ss.
Q(A2)
A 3
A 2
A 1
(NOT E1)
Des ele ct cy cle.
C E
( N O T E 2 )
A DV
O E
Q
Q(A 3)
t K QX
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and
CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE
does not cause Q to be driven until after the following clock rising edge.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 12
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
WRITE TIMING
BU RS T W RIT E
C LK
A DSC
Hig h-Z
A D S P
A D D RES S
B W E ,
B W 1- B W 4
t KC
t KH t KL
t A DSS t A DSH
DON'T CARE
UNDEFINED
t A S t A H
t WS t WH
t CES t CEH
t A A S t A A H
tO EHZ
t D S t DH
S in g le W RIT E
(NOT E 3)
D(A1)
D(A2)
D(A2+1)
D(A2 +2)
D(A2+3 )
D(A3+1)
D(A3 )
A 3
A 2
A 1
(NOT E 1)
C E
( NO T E 2 )
A DV
O E
D
A DS C exte n ds b ur s t.
t A D SS t A D SH
t A D SS t A D SH
G W
t W S t WH
D(A2+1)
D (A3+2 )
BUR ST RE A D
E xte nd e d BU RST W RIT E
Q
AD V su sp nd s b u rst .
(NO TE 4)
(N OT E 5)
BY T E W RIT E sig n als a r e
ig n or ed for fir st cy cle w hen
A DS P in it ialte s bu r st.
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW , CE2 is LOW
and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time. This
prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
ADV
must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4 LOW.
TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P. 13
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
READ/WRITE TIMING
A 4
Hi gh -Z
BURST REA D
C L K
A DS C
A D S P
A D DRE S S
B W E
B W 1- B W 4
t KC
t KH t KL
t A DSS t A DSH
DON'T CARE
UNDEFINED
t A S t A H
t W S t W H
t CE S t CEH
t DH
t KQ
tOELZ
tOE HZ
t DS
t KQ
t KQLZ
Si ng le W RIT E
Q(A1)
Q(A 2)
Q(A3 )
Q(A4)
Q(A4+1)
Q(A 4+3)
Q(A 4+2)
A5
A 3
A 1
(NOT E1)
C E
( N O T E 2 )
A DV
O E
D
A 2
A 6
Q
Hig h-Z
D(A3)
D(A 5)
D(A6)
Back-t o-Back REA Ds
Pass-thr ough
REA D
Back-to-Back
W RIT Es
Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP, ADSC or ADV
cycle is performed.
4. GW is HIGH.
5. Back-to-back READs may be controlled by either ADSP or ADSC.
TE
CH
tm
Preliminary
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P.14
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
PACKAGE DIMENSIONS
100-LEAD QFP SSRAM (14 x 20 mm)
SYMBOL
DIMENSIONS IN INCHES
DIMENTION IN MM
A
0.130(MAX)
3.302(MAX)
A1
0.112
0.005
2.845
0.127
A2
0.004(MIN)
0.102(MIN)
b
0.012+0.004-0.002
0.300+0.102-0.051
D
0.551
0.005
14.000
0.127
E
0.787
0.005
20.000
0.127
e
0.026
0.006
0.650
0.152
HD'
0.677
0.008
17.200
0.203
HE'
0.913
0.008
23.200
0.203
L'
0.032
0.008
0.800
0.203
L1'
0.063
0.008
1.600
0.203
t
0.006+0.004-0.002
0.150+0.102-0.051
y
0.004(MAX)
0.102(MAX)
c
0C~12C
0C~12C
TE
CH
tm
Preliminary
T35L6432A
Taiwan Memory Technology, Inc. reserves the right P.15
Publication Date: DEC. 1998
to change products or specifications without notice.
Revision:A
PACKAGE DIMENSIONS
100-LEAD TQFP SSRAM (14 x 20 mm)
SYMBOL
DIMENSIONS IN INCHES
DIMENTION IN MM
A
0.063(MAX)
1.600(MAX)
A1
0.055
0.005
1.400
0.050
A2
0.002(MIN)
0.050(MIN)
b
0.013+0.002-0.004
0.320+0.060-0.100
D
0.551
0.004
14.000
0.100
E
0.787
0.004
20.000
0.100
e
0.026
0.006
0.650
0.152
HD'
0.630
0.004
16.000
0.100
HE'
0.866
0.004
22.000
0.100
L'
0.024
0.006
0.600
0.150
L1'
0.039
0.006
1.000
0.150
t
0.006
0.002
0.150+0.050-0.060
y
0.003(MAX)
0.080(MAX)
c
0C~7C
0C~7C
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