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Электронный компонент: T35L6464A

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TE
CH
tm
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 1
Publication Date: AUG. 1998
to change products or specifications without notice.
Revision: E
SYNCHRONOUS
BURST SRAM
64K x 64 SRAM
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER
FEATURES
Fast Access times: 5, 6, 7, and 8ns
Fast clock speed: 100, 83, 66, and 50 MHz
Provide high performance 3-1-1-1 access rate
Fast OE access times: 5 and 6ns
Single 3.3V +10% / -5V power supply
Common data inputs and data outputs
BYTE WRITE ENABLE and GLOBAL
WRITE control
Five chip enables for depth expansion and
address pipelining
Address, control, input, and output pipelined
registers
Internally self-timed WRITE cycle
WRITE pass-through capability
Burst control pins ( interleaved or linear burst
sequence)
High density, high speed packages
Low capacitive bus loading
High 30pF output drive capability at rated access
time
SNOOZE MODE for reduced power standby
Single cycle disable ( Pentium
T M
BSRAM
compatible )
OPTIONS
TIMING
MARKING
5ns access/10ns cycle
-5
6ns access/12ns cycle
-6
7ns access/15ns cycle
-7
8ns access/20ns cycle
-8
Package
128-pin QFP
Q
128-pin LQFP
L
Part Number Examples
PART NO.
Pkg. BURST SEQUENCE
T35L6464A-5Q
Q
Interleaved
(MODE=NC or VCC)
T35L6464A-5L
L
Linear (MODE=GND)
PIN ASSIGNMENT (Top View)
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
VCCQ
VSSQ
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
VCCQ
VSSQ
DQ54
DQ55
DQ56
DQ57
DQ8
DQ9
DQ10
DQ11
VCCQ
VSSQ
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
VCCQ
VSSQ
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
VCCQ
1
11
10
9
8
7
6
5
4
3
2
18
17
16
15
14
13
12
28
27
26
25
24
23
22
21
20
19
30
29
39
49
48
47
46
45
44
43
42
41
40
57
56
55
54
53
52
51
50
58
82
81
80
79
78
77
76
75
74
73
92
91
90
89
88
87
86
85
84
83
102
101
100
99
98
97
96
95
94
93
123
124
116115114113112111110109
118
119
120
121
122
117
128127126125
CE3
VCCQ
CLK
OE
BW5
BW6
BW7
BW8
CE
VCC
VSS
CE2
CE3
CE2
BW3
BW4
GW
BWE
VCC
VSS
VSS
A11
A10
A9
A8
VCC
A13
A12
A0
A1
A2
A3
A4
VCC
A14
A15
ZZ
VSSQ
MODE
NC
128-pin QFP
or
128-pin LQFP
DQ58
31
DQ59
32
DQ60
33
DQ61
34
DQ62
35
DQ63
36
DQ64
37
VCCQ
38
63
62
61
60
59
64
VSS
A5
A6
A7
NC
VCCQ
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
72
71
70
69
68
67
66
65
108107106105104103
ADSC
ADSP
BW1
BW2
VSSQ
ADV
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable (CE ,CE2 and CE3 ), two additional
chip enables (CE2 and CE3) , burst control inputs
TE
CH
tm
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 2
Publication Date: AUG. 1998
to change products or specifications without notice.
Revision: E
GENERAL DESCRIPTION
(continued)
(ADSC , ADSP ,and
ADV
), write enables (
BW1
,
BW2
,
BW3
,
BW4
,
BW5
,
BW6
,
BW7
,
BW8
and
BWE
), and global write (
GW
).
Asynchronous inputs include the output enable
(
OE
) , Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
OE
,
are also asynchronous.
Addresses and chip enables are registered with
either address status processor (
ADSP
) or address
status controller (
ADSC
) input pins. Subsequent
burst addresses can be internally generated as
controlled by the burst advance pin (
ADV
).
Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to eight bytes
wide
as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-DQ16.
BW3
controls DQ17-DQ24.
BW4
controls DQ25-DQ32.
BW5
controls
DQ33-DQ40.
BW6
controls DQ41-DQ48.
BW7
controls DQ49-DQ56.
BW8
controls
DQ57-DQ64.
BW1
,
BW2
,
BW3
,
BW4
,
BW5
,
BW6
,
BW7
and
BW8
can be active only with
BWE
being LOW.
GW
being LOW causes all
bytes to be written. WRITE pass-through
capability allows written data available at the output
for the immediately next READ cycle. This
device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system
performance.
FUNCTIONAL BLOCK DIAGRAM
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
BYTE 1
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 2
WRITE REGISTER
ADDRESS
REGISTER
DO D1 Q1
BINARY
COUNTER
& LOGIC
CLR
LOAD
Q0
BYTE 1
WRITE DRIVER
BYTE 2
WRITE DRIVER
BYTE 3
WRITE DRIVER
BYTE 4
WRITE DRIVER
16
16
14
16
A0
A1
A1'
A0'
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
INPUT
REGISTERS
8
8
8
8
8
8
8
8
64
64
64
DQ1
.
.
.
DQ64
8
A0-A15
MODE
ADV
CLK
ADSC
ADSP
BW4
BW3
BW2
BW1
CE
CE2
CE2
OE
GW
BWE
PIPELINED
ENABLE
BYTE 5
WRITE REGISTER
BYTE 6
WRITE REGISTER
BYTE 7
WRITE REGISTER
BYTE 8
WRITE REGISTER
BYTE 7
WRITE DRIVER
BYTE 8
WRITE DRIVER
BW5
BW6
BW7
BW8
8
8
8
8
BYTE 6
WRITE DRIVER
BYTE 5
WRITE DRIVER
8
8
8
8
64K x 8 x 8
MEMORY
ARRAY
CE3
CE3
Chip
Enable
Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
TE
CH
tm
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 3
Publication Date: AUG. 1998
to change products or specifications without notice.
Revision: E
PIN DESCRIPTIONS
QFP PINS
SYM.
TYPE
DESCRIPTION
42-44, 47-51,
A0-
Input-
Addresses: These inputs are registered and must meet the setup and
53-57, 60-62
A15 Synchronous hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1,during burst
cycle and wait cycle.
107, 108, 111,
BW1
-
Input-
Byte Write: A byte write is LOW for a WRITE cyle and HIGH for
112,117-120
BW8
Synchronous a READ cycle.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-
DQ16.
BW3
controls DQ17-DQ24.
BW4
controls DQ25-DQ32.
BW5
controls DQ33-DQ40.
BW6
controls DQ41-DQ48.
BW7
controls DQ49-DQ56.
BW8
controls DQ57-DQ64. Data I/O are
high impedance if either of these inputs are LOW ,conditioned by
BWE
being LOW.
114
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the setup and hold times around the rising edge of
CLK.
113
GW
Input-
Global Write: This active LOW input allows a full 64-bit WRITE
Synchronous to occur independent of the
BWE
and
BWn
lines and must meet
the setup and hold times around the rising edge of CLK.
115
CLK
Input-
Clock: This signal registers the addresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
121
CE
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device and conditions internal use of
ADSP
. This input is
sampled only when a new external address is loaded.
124
CE2
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
126
CE2
Input-
Synchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
125
CE3
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
127
CE3
Input-
Synchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
116
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
TE
CH
tm
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date: AUG. 1998
to change products or specifications without notice.
Revision: E
PIN DESCRIPTIONS
(continued)
QFP PINS
SYM.
TYPE
DESCRIPTION
104
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
105
ADSP
Input-
Address Status Processor: This active LOW input, along with
CE
Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
106
ADSC
Input-
Address Status Controller:This active LOW input causes device to
Synchronous be de- selected or selected along with new external address to be
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
41
MODE
Input-
Mode: This input selects the burst sequence. A LOW on this pin
Static
selects LINEAR BURST. A NC or HIGH on this pin selects
INTERLEAVED BURST. Do not alter input state while device is
operating.
63
ZZ
Input
Snooze Enable: This active HIGH asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained.
2-12,15-24,
DQ1-
Input/
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-
27-37,66-76, DQ64
Output
DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25- DQ32.
79-88,91-101
Fifth Byte is DQ33- DQ40. Sixth Byte is DQ41- DQ48. Seventh
Byte is DQ49- DQ56. Eighth Byte is DQ57- DQ64. Input data
must meet setup and hold times around the rising edge of CLK.
45,58,109,122 VCC
Supply
Power Supply: 3.3V +10%/-5%.
46,59,110,123 VSS
Ground
Ground: GND
13,25,38,64, VCCQ I/O Supply Isolated Output Buffer Supply: 3.3V +10%/-5%.
77,89,102,128
1,14,26,39,65,
78,90,103
VSSQ I/O Ground Output Buffer Ground: GND
40,52
NC
-
No Connect: These signals are not internally conntected.
TE
CH
tm
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 5
Publication Date: AUG. 1998
to change products or specifications without notice.
Revision: E
INTERLEAVED BURST ADDRESS TABLE (MODE = NC/Vcc)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
LINEAR BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
PARTIAL TRUTH TABLE FOR READ/WRITE
Function
GW BWE BW1 BW2 BW3
BW4
BW5
BW6
BW7
BW8
READ
H
H
X
X
X
X
X
X
X
X
READ
H
L
H
H
H
H
H
H
H
H
WRITE byte 1
H
L
L
H
H
H
H
H
H
H
WRITE byte 2
H
L
H
L
H
H
H
H
H
H
WRITE byte 3
H
L
H
H
L
H
H
H
H
H
WRITE byte 4
H
L
H
H
H
L
H
H
H
H
WRITE byte 5
H
L
H
H
H
H
L
H
H
H
WRITE byte 6
H
L
H
H
H
H
H
L
H
H
WRITE byte 7
H
L
H
H
H
H
H
H
L
H
WRITE byte 8
H
L
H
H
H
H
H
H
H
L
WRITE all byte
H
L
L
L
L
L
L
L
L
L
WRITE all byte
L
X
X
X
X
X
X
X
X
X