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Электронный компонент: T431616C-6SG

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TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 1
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
SDRAM
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
FEATURES
3.3V power supply
Clock cycle time : 6 / 7 ns
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh and self refresh
32ms refresh period (2K cycle)
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
Available package type :
- 50 pin TSOP(II)/lead-free
Operating temperature :
- 0 ~ +70
C

ORDERING INFORMATION
GRNERAL DESCRIPTION
The T431616C is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NO.
CLOCK
CYCLE TIME
MAX
FREQUENCY
PACKAGE
OPERATING
TEMPERATURE
T431616C-6S
6ns
166 MHz
TSOP-II
0 ~ +70
C
T431616C-6SG
6ns
166 MHz
TSOP-II
Lead-free
0 ~ +70
C
T431616C-7S
7ns
143 MHz
TSOP-II
0 ~ +70
C
T431616C-7SG
7ns
143 MHz
TSOP-II
Lead-free
0 ~ +70
C
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 2
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
PIN ARRANGEMENT


(TSOP-II
Top View)
D Q 1
V
D D
4 6
4 5
4 4
4 3
4 1
4 2
4 0
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1
2
3
4
6
5
7
8
9
1 1
1 5
1 6
1 7
1 8
1 9
2 0
V
D D Q
D Q 1 1
D Q 1 0
A 8
A 7
A 9
1 0
2 1
2 2
4 7
4 8
4 9
5 0
V
S S Q
D Q 2
A 0
A 1
D Q 1 5
D Q 1 4
V
S S Q
V s s
2 3
2 4
2 5
2 8
2 7
2 6
D Q 3
D Q 0
V
D D Q
D Q 4
D Q 5
V
S S Q
D Q 6
R A S
C S
B A
A 1 0 /A P
A 2
A 3
V
D D
V
S S Q
D Q 1 3
D Q 1 2
D Q 9
U D Q M
N .C
C L K
C K E
V s s
A 6
A 5
A 4
1 2
1 3
1 4
3 9
3 8
3 7
D Q 7
V
D D Q
L D Q M
D Q 8
V
D D Q
N .C /R F U
W E
C A S
5 0 P IN T S O P (II)
(4 0 0 m il x 8 2 5 m il)
(0 .8 m m P IN P IT C H )


TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 3
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
BLOCK DIAGRAM
Data Input Register
I/
O
C
o
n
t
ro
l
O
u
t
p
u
t
B
u
ffer
512K x 16
512K x 16
Sens
e A
M
P
Colum n Decoder
Latency & Burst Length
Program ming Register
Bank Select
Ro
w
Bu
f
f
e
e
r
R
e
f
r
es
h C
ount
er
R
o
w
D
e
c
oder
A
d
dre
ss R
e
g
i
ster
Co
l
.
B
u
f
f
e
r
Timing Register
DQi
LDQM
LW E
LDQM
LW CBR
LCAS
LW E
LCBR
LRAS
L(U)DQM
RAS
CS
CKE
CLK
LCBR
LRAS
ADD
CLK
LCKE
CAS
W E



















TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 4
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK System
Clock
Active on the positive going edge to sample all input.
CS
Chip Select
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK
with
RAS
low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with
CAS
low.
Enables column access .
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power
Supply/Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output
Power/Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C/RFU
No
Connection/Reserved
for Future Use
This pin is recommended to be left No Connection on the device.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 5
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative To Vss
V
IN
,V
OUT
-1.0 to 4.6
V
Supply Voltage Relative To Vss
V
DD
,V
DDQ
-1.0 to 4.6
V
Short circuit Output Current
Iout 50 mA
Power Dissipation
P
D
1 W
Operating Temperature
TOPR
0 to +70
C
Storage Temperature
Tstg
-55 to +125
C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70



C, Voltage referenced to V
SS
=0V)
Parameter Symbol
Min.
Typ
Max.
Unit
Notes
Supply Voltage
V
DD
,V
DDQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0 3.0
V
DD
+0.3V V
1
Input Low Voltage
V
IL
-0.3 0 0.8 V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4 V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5 uA
3
Output leakage current
I
OL
-5 - 5 uA 4
Note : 1. V
IH
(max) = 4.6V AC for pulse width
10ns acceptable.
2. V
IL
(min) = -1.0V AC for pulse width
10ns acceptable.
3. Any input 0V
V
IN
V
DD
+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable, 0V
V
OUT
V
DD .

CAPACITANCE
(T
A
=25
C
,V
DD
=3.3V, f = 1MHz)
Pin Symbol
Min
Max
Unit
CLOCK C
CLK
2.5 4.0 pF
ADDRESS C
ADD
2.5 4.0 pF
DQ0 ~ DQ15
C
OUT
3.0 5.0 pF
RAS,CAS,WE,CS,CKE,LDQM,
UDQM
C
IN
2.5 4.0
pF
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 6
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
DC CHARACTERISTICS
T
A
= 0 to 70
C
, V
IH
(min)/V
IL
(max)=2.0V/0.8V
Speed version
Parameter Symbol
-6 -7
Unit Test
Condition
Note
Operating Current
( One Bank Active)
I
CC1
145
140
mA
Burst Length = 1
t
RC
t
RC
(min) ,
t
CC
t
CC
(min),I
OL
= 0 mA
1,3
I
CC2
P 2
CKE
V
IL
(max),
t
CC
=
t
CC(min)
Precharge Standby
Current in power-
down mode
I
CC2
PS 3
mA
CKE
V
IL
(max),CLK
V
IL
(max),
t
CC
=
3
I
CC2
N 30
CKE
V
IH
(min),
CS
V
IH
(min),
t
CC
=
t
CC(min)
Input signals are changed one time during 30ns
Precharge Standby
Current in non
power-down mode
I
CC2
NS 2
mA
CKE
V
IH
(min),CLK
V
IL
(min),
t
CC
=
Input signals are stable
3
I
CC3
P 10
CKE
VIL(max),
t
CC
=
t
CC(min)
Active Standby
Current in power-
down mode
I
CC3
PS 10
mA
CKE
V
IL
(max),CLK
V
IL
(max),
t
CC
=
3
I
CC3
N 40
CKE
V
IH
(min),
CS
V
IH
(min),
t
CC
=
t
CC(min)
Input signals are changed one time during 30ns
Active Standby
Current in non
power-down mode
(One Bank Active) I
CC3
NS 30
mA
CKE
V
IH
(min),CLK
V
IL
(min),
t
CC
=
Input signals are stable
3
150 140
CAS Latency 3
Operating Current
(Burst Mode)
I
CC4
150 140
mA
CAS Latency 2
I
OL
=0 mA,Page Burst
All Band Activated
t
CCD
=
t
CCD
(min)
1,3
Refresh Current
I
CC5
90
80
mA
t
RC
t
RC
(min)
2,3
Self refresh
Current
I
CC6
1
mA
CKE
0.2V
Note: 1. Measured with output open. Addresses are changed only one time during
t
CC
(min)
.
2. Refresh period is 32ms. Addresses are changed only one time during
t
CC
(min)
.
3.
t
CC
: Clock cycle time.
t
RC
: Row cycle time.
t
CCD
: Column address to column address delay time.






TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 7
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
AC OPERATING CONDITIONS
(V
DD
=3.3V
0.3V ,T
A
= 0 to 70
C
)
Parameter Value
Unit
Input levels (V
IH
/V
IL
)
2.0 / 0.8
V
Input timing measurement reference level
1.4
V
Input rise and fall time
t
r /
t
f = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig.2






3.3V
1200 ohm
Output
870 ohm
30pf
VOH(DC)=2.4,IOH=-2mA
VOL(DC)=0.4,IOL=2mA
ZO=50 ohm
Output
50 ohm
Vtt=1.4v
30pf
(Fig.1) DC Output Load Circuit (Fig.2)AC Output Load Circuit













TE
CH
tm
T431616C
TM Technology Inc. reserves the right P. 8
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
Speed Version
Parameter Symbol
-6 -7
Unit Note
Row active to row active delay
t
RRD
(min)
12 14
ns
1
RAS to CAS delay
t
RCD
(min)
18 21
ns
1
Row precharge time
t
RP
(min)
18 21
ns
1
t
RAS
(min)
36 42
ns
1
Row active time
t
RAS
(max)
100K ns
Row cycle time
t
RC
(min)
60 70
ns
1
Last data in to new col. Address delay
t
CDL
(min)
1 CLK
2
Last data in to row precharge
t
RDL
(min)
2 CLK
2
Last data in to burst stop
t
BDL
(min)
1 CLK
2
Col. Address to col. Address delay
t
CCD
(min)
1 CLK
3
CAS latency=3
1
Number of valid output data
CAS latency=2
1
ea 4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.9
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
AC CHARACTERISTICS
(AC opterating conditions unless otherwise noted)
-6 -7
Parameter
Symbol
Min Max Min Max
Unit Note
CAS Latency = 3
6
7
CLK cycle time
CAS Latency = 2
t
CC
8
1K
8.6
1K ns 1
CAS Latency = 3
-
5.5
-
6
ns
CLK to valid
Output delay
CAS Latency = 2
t
SAC
- 6 - 6 ns
1
Output data hold time
t
OH
1 1 ns 2
CLK high pulse width
t
CH
2 2.5 ns 3
CLK low pulse width
t
CL
2 2.5 ns 3
Input setup time
t
SS
2 2 ns 3
Input hold time
t
SH
1 1 ns 3
CLK to output in Low-Z
t
SLZ
1 1 ns 2
CAS Latency = 3
-
5.5
-
6
ns
CLK to output in Hi-Z
CAS Latency = 2
t
SHZ
- 6 - 6 ns
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns,transient time compensation should be considered,
i.e.,[(tr+tf)/2-1]ns should be added to the parameter.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.10
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: D
FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE
T431616C-6S (Unit : number of clock)
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
Frequency
CAS
Latency
60ns 36ns 18ns 12ns 18ns 6ns 6ns 12ns
166MHz(6.0ns)
3 10 6 3 2 3 1 1 2
143MHz(7.0ns) 3 9 6 3 2 3 1 1 2
125MHz(8.0ns) 2 8 5 3 2 3 1 1 2
111MHz(9.0ns) 2 7 4 2 2 2 1 1 2
100MHz(10.0ns)
2 6 4 2 2 2 1 1 2
T431616C-7S (Unit : number of clock)
t
RC
t
RAS
t
RP
t
RRD
t
RCD
t
CCD
t
CDL
t
RDL
Frequency
CAS
Latency
70ns 42ns 21ns 14ns 21ns 7ns 7ns 14ns
143MHz(7.0ns)
3 10 6 3 2 3 1 1 2
125MHz(8.0ns) 3 9 6 3 2 3 1 1 2
111MHz(9.0ns) 2 8 5 3 2 3 1 1 2
100MHz(10.0ns)
2 7 5 3 2 3 1 1 2
83MHz(12.0ns) 2 6 4 2 2 2 1 1 2
Note : 1. Clock count formula : clock
period
clock
value
base
(round off whole number).
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.11
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
MODE REGISTER
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 1
JEDEC Standard Test Set (refresh counter test)

11 10 9 8 7 6 5 4 3 2 1 0
x x 1 0 0 LTMODE WT
BL
Burst Read and Single Write (for Write Through Cache)

11 10 9 8 7 6 5 4 3 2 1 0
1 0
Use in future

11 10 9 8 7 6 5 4 3 2 1 0
x x x 1 1 v v v v v v v
Vender Specific

11 10 9 8 7 6 5 4 3 2 1 0
v = Valid
0 0 0 0 0 LTMODE WT
BL
Mode Register Set
x = Don't care
Bit2-0 WT=0 WT=1
000 1 1
001 2 2
010 4 4
011 8 8
100 R R
101 R R
110 R R
Burst length
111 Full
page R
0 Sequential
Wrap type
1 Interleave
Bit6-4 CAS
Latency
000 R
001 R
010 2
011 3
100 R
101 R
110 R
Latency mode
111 R
Remark R : Reserved
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.12
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
0 0,1 0,1
1 1,0 1,0

(Burst of Four)
Starting Address
(column address A1-A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
00 0,1,2,3
0,1,2,3
01 1,2,3,0
1,0,3,2
10 2,3,0,1
2,3,0,1
11 3,0,1,2
3,2,1,0

(Burst of Eight)
Starting Address
(column address A2-A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (Decimal)
000 0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
001 1,2,3,4,5,6,7,0
1,0,3,2,5,4,7,6
010 2,3,4,5,6,7,0,1
2,3,0,1,6,7,4,5
011 3,4,5,6,7,0,1,2
3,2,1,0,7,6,5,4
100 4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
101 5,6,7,0,1,2,3,4
5,4,7,6,1,0,3,2
110 6,7,0,1,2,3,4,5
6,7,4,5,2,3,0,1
111 7,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for
1Mx16 divice.
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain CKE = `H' , L(U)DQM = `H' and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initalize the mode register.
Cf.) Sequence of 4 & 5 is regardless of the order.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.13
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A

SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn CS RAS CAS WE DQM BA A
10
/AP A
9
~A
0
Note
Register
Mode Register Set
H
X
L
L
L
L
X
X
1,2
Auto Refresh
H
Entry
H
L
L L L H X
X
3
L H H H
Refresh
Self
Refresh
Exit
L H
H X X X
X X 3
Bank Active & Row Address
H
X
L
L
H
H
X
V
Row Address
Auto Precharge Disable
L
Read Column
Address
Auto Precharge Enable
H X
L
H
L
H
X
V
H
Column
Address
(A0~A7)
4,5
Auto Precharge Disable
L
Write & Column
Address
Auto Precharge Enable
H X L H L L X V
H
Column
Address
(A0~A7)
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Bank Selection
V
L
Precharge
Both Banks
H X L L H L X X H
4
H X X X
Entry
H L
L V V V
X
Clock Suspend or
Active Power Down
Exit
L H X X X X X
X
H X X X
Entry
H L
L H H H
X
H X X X
Precharge Power Down
Mode
Exit
L H
L V V V
X
X

DQM H
X
V
X
7
H H
X
X
X
No Operation Command
H
X
L H H H
X X
(V=Valid , X=Don't Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A
0
~A
10
/AP , BA : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by `Auto'. Auto / self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If 'Low' : at read , wriye , row active and precharge , bank A is selected.
If `High' : at read , wriye , row active and precharge , bank B is selected.
If A
10
/AP is `High' : at row precharge , BA ignored and both banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at
t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.14
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Single Bit READ-Write Cycle (Same Page) @CAS Latency=3,Burst Length=1
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
A10/AP
DQ
WE
DQM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
CH
t
CC
t
CL
HIGH
t
RAS
t
RC
*Note1
t
SH
t
SS
t
RP
t
RCD
t
S
H
t
SS
t
CCD
*Note2
*Note2.
3
*Note2.
3
*Note2.
3
*Note4
*Note2
t
SH
t
SS
t
SS
t
SH
t
SS
t
SH
*Note3
*Note3
*Note3
*Note4
t
RAC
t
SRC
t
SLZ
t
OH
t
SS
t
SH
t
SH
t
SS
t
SH
t
SS
Row Active
Read
W rite
Read
Precharge
Row Active
Ra
Ca
Cb
Cc
Rb
Bs
Bs
Bs
Bs
Bs
Bs
Rb
Ra
Qa
Db
Qc
:Don't care
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.15
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
*note : 1. All input expect CKE & DQM can be don't care when
CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
Active & Read/Write
0 Bank
A
1 Bnak
B

3. Enable and disable auto precharge function are controlled by A
10
/AP in read/wirte command.
A
10
/AP BA
Operation
0 Disable auto precharge,leave bank A active at end of burst.
0
1 Disable auto precharge,leave bank B active at end of burst.
0 Enable auto precharge, precharge bank A at end of burst.
1
1 Enable auto precharge, precharge bank B at end of burst.

4. A
10
/AP and BA control bank precharge when precharge command is asserted.
A
10
/AP BA precharge
0 0 Bank
A
0 1 Bank
B
1 X
Both
Banks
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.16
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Power Up Sequence
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
t
C C D
H ig h lev e l is n ec e ss a ry
t
R P
t
R C
t
R C
K ey
R A a
K ey
K ey
R A a
H ig h lev e l is n ec e ss a ry
H ig h -Z
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
P re c h a rg e
A ll B a n k s
A u to
R e fre sh
A u to R e fre s h
M o d e R e g iste r S e t
(A -B a n k )
R o w
A c tiv e
:D o n 't c a re
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.17
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Read & Write Cycle at Same Bank @Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
t
R C
D Q M
D Q
: D o n 't c a r e
* N o t e 1
t
R C D
* N o t e 2
* N o t e 4
* N o t e 3
* N o t e 3
* N o t e 4
R a
C a 0
R b
C b 0
R b
R a
Q a 0
Q a 1
Q a 2
Q a 3
Q a 0
Q a 1
Q a 2
Q a 3
D b 0
D b 0
D b 1
D b 1
D b 2
D b 2
D b 3
D b 3
t
R A C
t
S A C
t
O H
t
O H
t
S A C
t
S H Z
t
S H Z
t
R D L
t
R D L
R o w
A c t i v e ( A -
B a n k )
R e a d ( A -
B a n k )
P r e c h a r g
e ( A -
B a n k )
R o w A c t i v e
( A - B n a k )
W r i t e ( A -
B n a k )
P r e c h a r g e
( a - B n a k )

*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z(
t
SHZ
) after the clock.
3. Access time from Row active command.
t
CC
*(
t
RCD
+CAS latency-1)+
t
SAC
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can't end in Full Page Mode.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.18
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
t
C C D
D Q M
D Q
: D o n 't c a r e
R o w A c t i v e
( A - B n a k )
R e a d ( A -
B n a k )
R e a d ( A -
B n a k )
W r i t e ( A -
B n a k )
W r i t e ( A -
B n a k )
P r e c h a r g e
( A - B n a k )
* N o t e 1
* N o t e 3
* N o t e 2
t
R C D
t
R D L
t
C D L
R a
C a 0
C b 0
C c 0
C d 0
Q a 0
Q a 1
Q a 0
Q a 1
Q b 0
Q b 0
Q b 1
Q b 2
Q b 1
D c 0
D c 1
D c 0
D c 1
D d 0
D d 1
D d 0
D d 2



*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input,
t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.19
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Page Read Cycle at Different Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n 't c a r e
* N o t e 1
* N o t e 2
R A a
C A a
R B b
C B b
C A c
C B d
C A e
R A a
R B b
Q A a 0
Q A a 1
Q A a 2
Q A a 3
Q A a 0
Q A a 1
Q A a 2
Q A a 3
Q B b 0
Q B b 0
Q B b 1
Q B b 2
Q B b 3
Q B b 1
Q B b 2
Q B b 3
Q A c 0
Q A c 1
Q A c 0
Q A c 1
Q B d 0
Q B d 0
Q B d 1
Q B d 1
Q A e 0
Q A e 0
Q A e 1
Q A e 1
R o w A c t i v e
( A - B a n k )
R e a d ( A -
B a n k )
R o w A c t i v e
( B - B a n k )
R e a d ( B -
B a n k )
R e a d ( A -
B a n k )
R e a d ( B -
B a n k )
R e a d ( A -
B a n k )
P r e c h a r g e
( A - B a n k )




*Note : 1.
CS can be don't cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.20
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Page Write cycle at Different Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H IG H
:D o n 't c a re
R o w A c tiv e
(A -B a n k )
W rite ( A -
B a n k )
R o w A c tiv e
(B -B a n k )
W rite ( B -
B a n k )
W rite ( A -
B a n k )
W rite ( B -
B a n k )
P re c h a rg e
(A -B a n k )
* N o te 1
* N o te 2
t
C D L
t
R D L
R A a
C A a
R B b
C B b
C A c
C B d
R A a
R B b
D A a 0
D A a 1
D A a 2
D A a 3
D B b 0
D B b 1
D B b 2
D B b 3
D A c 0
D A c 1
D B d 0
D B d 1





*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.21
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Read & Write Cycle at Different Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n 't c a r e
Q A a 0
R A a
C A a
R B b
C B b
R A c
C A c
R A a
R B b
R A c
Q A a 1
Q A a 2
Q A a 3
Q A a 0
Q A a 1
Q A a 2
Q A a 3
D B b 0
D B b 1
D B b 2
D B b 3
D B b 0
D B b 1
D B b 2
D B b 3
Q A c 0
Q A c 0
Q A c 1
Q A c 2
Q A c 1
* N o t e 1
t
C D L
R o w A c t i v e
( A - B a n k )
R e a d ( A -
B a n k )
R o w A c t i v e
( B - B a n k )
P r e c h a r g e
( A - B a n k )
W r i t e ( B -
B a n k )
R o w A c t i v e
( A - B a n k )
R e a d ( A -
B a n k )



*Note : 1.
t
CDL
should be met to complete write.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.22
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Read & Write Cycle with Auto Precharge @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n 't c a r e
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( B - B a n k )
R e a d w i t h A u t o
p r e c h a r g e ( A -
B a n k )
C L = 2 A u t o
P r e c h a r g e S t a r t
P o i n t ( A - B a n k )
C L = 3 A u t o
P r e c h a r g e S t a r t
P o i n t ( A - B a n k )
W r i t e w i t h A u t o
P r e c h a r g e ( B -
B a n k )
A u t o P r e c h a r g e
S t a r t P o i n t ( A -
B a n k )
R a
R b
C a
C b
R a
R b
Q a 0
Q a 1
Q a 2
Q a 3
Q a 0
Q a 1
Q a 2
Q a 3
D b 0
D b 0
D b 1
D b 1
D b 2
D b 2
D b 3
D b 3




*Note : 1.
t
CDL
should be controlled to meet minimum
t
RAS
before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)

TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.23
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
:D o n 't c a r e
R o w A c tiv e
R e a d
C lo c k
S u s p e n s io n
R e a d
R e a d Q D M
W rite
W rite Q D M
C lo c k
S u s p e n s io n
W rite Q D M
* N o t e 3
R a
C a
C b
C c
R a
Q a 0
Q a 1
Q a 2
Q a 3
Q b 0 Q b 1
D c 0
D c 2
t
S H Z
t
S H Z






*Note 1. DQM is needed to prevent bus contention.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.24
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n 't c a r e
R A a
C A a
C A b
R A a
Q A a 0
Q A a 1
Q A a 2
Q A a 3
Q A a 4
Q A a 0
Q A a 1
Q A a 2
Q A a 3
Q A a 4
Q A b 0
Q A b 0
Q A b 1
Q A b 1
Q A b 2
Q A b 3
Q A b 2
Q A b 4
Q A b 3
Q A b 5
Q A b 4
Q A b 5
* N o t e 2
1
2
2
1
R o w A c t i v e
( A - B a n k )
R e a d ( A -
B a n k )
R e a d ( A -
B a n k )
B u r s t S t o p
P r e c h a r g e
( A - B a n k )
*Note : 1. Burst can't end in full page mode, so auto precharge can't issue.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of `Full Page write burst stop cycle'.
3. Burst stop is valid at every burst length.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.25
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
:D o n 't c a r e
R o w A c tiv e
(A -B a n k )
W rite ( A -
B a n k )
B u rs t S to p
W rite ( A -
B a n k )
P re c h a rg e
(A -B a n k )
R A a
C A a
C A b
R A a
D A a 0
D A a 1
D A a 2
D A a 3
D A a 4
D A b 0
D A b 1
D A b 2
D A b 3
D A b 4
D A b 5
* N o te 3
t
B D L
t
R D L

*Note : 1. Burst can't end in full page mode, so auto precharge can't issue.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell.
It is defined by AC parameter of
t
RDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.26
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Burst Read Single bit Write Cycle @ Burst Length = 2
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
C L = 2
C L = 3
W E
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
H I G H
D Q M
D Q
: D o n 't c a r e
* N o t e 2
R A a
C A a
R B b
C A b
R A c
C B c
C A d
R A a
R B b
R A c
D A a 0
D A a 0
D A b 0
D A b 0
D A b 1
D A b 1
D B c 0
D B c 0
D A d 0
D A d 1
D A d 0
D A d 1
R o w A c t i v e
( A - B a n k )
W r i t e ( A -
B a n k )
R o w A c t i v e
( A - B a n k )
R e a d w i t h A u t o
P r e c h a r g e ( A -
B a n k )
R o w A c t i v e
( A - B a n k )
W r i t e w i t h A u t o
P r e c h a r g e ( A -
B a n k )
R e a d ( A -
B a n k )
P r e c h a r g e
( A - B a n k )


*Note : 1. BRSW modes is enabled by setting A
9
`High' at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to `1' regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that
t
RAS
should not
be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command,
the precharge command will be issued after two clock cycle.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.27
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 /A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
:D o n 't ca re
P re c h a rg e
P o w e r-
D o w n E n try
P re c h a rg e
P o w e r-
D o w n E x it
R o w A c tiv e
A c tiv e
P o w e r-
D o w n E n try
A c tiv e
P o w e r-
D o w n E x it
R e a d
P re c h a rg e
Q a 0 Q a 1 Q a 2
R a
C a
R a
t
S H Z
S S
tss
ts s
ts s
* N o te 1
* N o te 3
* N o te 2
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK+
t
SS
prior to Row active command.
3. Can not violate minimum refresh specification.(32ms)
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.28
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Self Refresh Entry & Exit Cycle
C L O C K
C K E
C S
R A S
C A S
A D D R
B A
A 1 0 / A P
D Q
W E
D Q M
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
: D o n 't c a r e
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
* N o t e 2
* N o t e 1
* N o t e 3
* N o t e 4
* N o t e 6
* N o t e 7
* N o t e 5
t
S S
t
R C m i n
H i - z
S e l f R e f r e s h E n t r y
S e l f R e f r e s h E x i t
A u t o R e f r e s h
H i - z
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs inculding the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays `Low'.
Cf.) Once the device enters self refresh mode, minimum
t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the
system uses burst refresh.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.29
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
Mode Register Set Cycle Auto Refresh Cycle
C L O C K
C K E
C S
R A S
C A S
A D D R
D Q
W E
D Q M
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
1 0
:D o n 't c a re
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
S S
* N o te2
* N o te1
* N o te3
t
R P C
A u to R e fre sh
N e w C o m m a n d
M R S
N e w C o m m a n d
H i-z
K ey
K ey
H i-z
H IG H
H IG H




*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
TE
CH
tm
T431616C
TM Technology Inc. reserves the right P.30
Publication Date: AUG. 2004
to change products or specifications without notice.
Revision: A
PACKAGE DIMENSIONS
50 LEAD TSOPII (400 mil)
D
26
50
1
25
E
1
E
29
1
-C-
-H-
A
A2
DEFAULT
A
0.
2
1
RE
F
0
.
465
RE
F
A1
DEFAULT
A
3 (4X)
2(4X)
R2
R1
B
PLANE
-C-
.2
.
5
GAGE
B
1
L
L1
1.5
8.78
C1
C
b
b1
BASE METAL
WITH
PLATING
SETING
PLANE
e
-C-
(ZD)
b
0.10 C
SECTION B-B
Dimension in mm
Dimension in inch
Symbol
Min Nom Max Min Nom Max
A - - 1.20 - - 0.047
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 - 0.45 0.012 - 0.018
b1 0.30 0.35 0.40 0.012 0.014 0.016
c 0.12 - 0.21 0.005 - 0.008
c1 0.10 0.127 0.16 0.004 0.005 0.006
D 20.82 20.95 21.08 0.820 0.825 0.830
ZD
0.875 REF
0.034 REF
E 11.56 11.76 11.96 0.455 0.463 0.471
E1 10.03 10.16 10.29 0.394 0.400 0.405
L 0.40 0.50 0.60 0.016
0.020
0.024
L1
0.80 REF
0.031 REF
e
0.80 BSC
0.031 BSC
R1 0.12 - - 0.005 - -
R2 0.12 - 0.25 0.005 - 0.010
0 - 8 0 - 8
1
0 - - 0 - -
2
10 15 20 10 15 20
3
10 15 20 10 15 20
"A"