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Электронный компонент: T436416A-7.5S

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TE
CH
tm
T436416A
TM Technology Inc. reserves the right P. 1
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: B
SDRAM
4M x 16 SDRAM
1M x 16bit x 4Banks Synchronous DRAM
FEATURES
3.3V power supply
Four banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh and self refresh
64ms refresh period (4K cycle)
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
Available package type in 54 pin TSOP(II)
Operating temperature : 0 ~ +70
C
ORDERING INFORMATION
GRNERAL DESCRIPTION
The T436416A is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 1,048,576 words by 16 bits , fabricated with
high performance CMOS technology .
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clockcycle . Range of operating
frequencies , programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth , high
performance memory system applications.
PIN ARRANGEMENT (Top View)
D Q 1
V
D D
4 6
4 5
4 4
4 3
4 1
4 2
4 0
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1
2
3
4
6
5
7
8
9
1 1
1 5
1 6
1 7
1 8
1 9
2 0
V
D D Q
D Q 1 1
D Q 1 0
A 8
A 7
A 9
1 0
2 1
2 2
4 7
4 8
4 9
5 0
V
S S Q
D Q 2
A 0
A 1
D Q 1 5
D Q 1 4
V s s
2 3
2 4
2 5
2 8
2 7
2 6
D Q 3
D Q 0
V
D D Q
D Q 4
D Q 5
V
S S Q
D Q 6
R A S
C S
B A 1
A 1 0 / A P
A 2
A 3
V
D D
V
S S Q
D Q 1 3
D Q 1 2
D Q 9
U D Q M
N . C
C L K
C K E
V s s
A 6
A 5
A 4
1 2
1 3
1 4
3 9
3 8
3 7
D Q 7
V
D D
L D Q M
D Q 8
V s s
N . C / R F U
W E
C A S
5 4 P I N T S O P ( I I )
( 4 0 0 m i l x 8 7 5 m i l )
( 0 . 8 m m P I N P I T C H )
5 1
5 2
5 3
5 4
V
D D Q
B A 0
V
D D Q
V
S S Q
A 1 1
PART NO.
MAX
FREQUENCY
PACKAGE
T436416A-6S
166 MHz
54 pin TSOP(II)
T436416A-7S
143 MHz
54 pin TSOP(II)
T436416A-7.5S
133 MHz
54 pin TSOP(II)
T436416A-8S 125 MHz
54 pin TSOP(II)
T436416A-10S
100 MHz
54 pin TSOP(II)
T436416A-6SG
166 MHz
54 pin TSOP(II)
lead-free
T436416A-7SG
143 MHz
54 pin TSOP(II)
lead-free
T436416A-7.5SG 133 MHz
54 pin TSOP(II)
lead-free
T436416A-8SG 125 MHz
54 pin TSOP(II)
lead-free
T436416A-10SG 100 MHz
54 pin TSOP(II)
lead-free
TE
CH
tm
T436416A
TM Technology Inc. reserves the right P. 2
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: B
BLOCK DIAGRAM


Data Input Register
I
/
O
C
ont
r
o
l
O
u
t
put
B
u
f
f
e
r
1M x 16
1M x 16
Se
n
s
e
AM
P
Colum n Decoder
Latency & Burst Length
Program ming Register
Bank Select
Ro
w
B
u
f
f
e
e
r
R
e
f
r
e
s
h C
ount
e
r
R
o
w
D
e
code
r
A
d
d
r
e
ss R
e
gist
e
r
Co
l
.
B
u
f
f
e
r
Tim ing Register
DQi
LDQM
LW E
LDQM
LW CBR
LCAS
LW E
LCBR
LRAS
L(U)DQM
RAS
CS
CKE
CLK
LC
B
R
LR
A
S
ADD
CLK
LCKE
CAS
W E
1M x 16
1M x 16
TE
CH
tm
T436416A
TM Technology Inc. reserves the right P. 3
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: B
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK System
Clock
Active on the positive going edge to sample all input.
CS
Chip Select
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,column address : CA0 ~ CA7
BA0 ~ BA1
Bank Select Address
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK
with
RAS
low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with
CAS
low.
Enables column access .
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
L(U)DQM
Data Input/Output
Mask
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power
Supply/Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output
Power/Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C/RFU
No
Connection/Reserved
for Future Use
This pin is recommended to be left No Connection on the device.
TE
CH
tm
T436416A
TM Technology Inc. reserves the right P. 4
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: B
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative To Vss
V
IN
,V
OUT
-1.0 to 4.6
V
Supply Voltage Relative To Vss
V
DD
,V
DDQ
-1.0 to 4.6
V
Short circuit Output Current
Iout 50 mA
Power Dissipation
P
D
1 W
Operating Temperature
TOPR
0 to +70
C
Storage Temperature
Tstg
-55 to +125
C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70



C
, Voltage referenced to V
SS
=0V)
Parameter Symbol
Min.
Typ
Max.
Unit
Notes
Supply Voltage
V
DD
,V
DDQ
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0 3.0
V
DD
+0.3V V
1
Input Low Voltage
V
IL
-0.3 0 0.8 V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4 V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5 uA
3
Output leakage current
I
OL
-5 - 5 uA 4
Note : 1. V
IH
(max) = 4.6V AC for pulse width
10ns acceptable.
2. V
IL
(min) = -1.0V AC for pulse width
10ns acceptable.
3. Any input 0V
V
IN
V
DD
+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable, 0V
V
OUT
V
DD .

CAPACITANCE
(T
A
=25
C
,V
DD
=3.3V, f = 1MHz)
Pin Symbol
Min
Max
Unit
CLOCK C
CLK
2.5 4.0 pF
ADDRESS C
ADD
2.5 5.0 pF
DQ0 ~ DQ15
C
OUT
4.0 6.5 pF
RAS,CAS,WE,CS,CKE,LDQM,
UDQM
C
IN
2.5 5.0
pF
TE
CH
tm
T436416A
TM Technology Inc. reserves the right P. 5
Publication Date: MAY. 2003
to change products or specifications without notice.
Revision: B
DC CHARACTERISTICS
T
A
= 0 to 70
C
, V
IH
(min)/V
IL
(max)=2.0V/0.8V
Speed version
Parameter Symbol
-6 -7 -7.5 -8 -10
Unit Test
Condition
Note
Operating Current
( One Bank Active)
I
CC1
140 120 115 110 100 mA
Burst Length = 1
t
RC
t
RC
(min) ,
t
CC
t
CC
(min),I
OL
= 0 mA
1,3
I
CC2
P 2
CKE
V
IL
(max),
t
CC
=15ns
Precharge Standby
Current in power-
down mode
I
CC2
PS 2
mA
CKE
V
IL
(max),CLK
V
IL
(max),
t
CC
=
3
I
CC2
N 30
CKE
V
IH
(min),
CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
Precharge Standby
Current in non
power-down mode
I
CC2
NS 2
mA
CKE
V
IH
(min),CLK
V
IL
(min),
t
CC
=
Input signals are stable
3
I
CC3
P 10
CKE
VIL(max),
t
CC
=15ns
Active Standby
Current in power-
down mode
I
CC3
PS 10
mA
CKE
V
IL
(max),CLK
V
IL
(max),
t
CC
=
3
I
CC3
N 40
CKE
V
IH
(min),
CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
Active Standby
Current in non
power-down mode
(One Bank Active) I
CC3
NS 10
mA
CKE
V
IH
(min),CLK
V
IL
(min),
t
CC
=
Input signals are stable
3
150 130 125 120 110
CAS Latency 3
Operating Current
(Burst Mode)
I
CC4
150 130 125 120 110
mA
CAS Latency 2
I
OL
=0 mA,Page Burst
All Band Activated
t
CCD
=
t
CCD
(min)
1,3
Refresh Current
I
CC5
150 130 125 120 110 mA t
RC
t
RC
(min)
2,3
Self refresh
Current
I
CC6
1
mA
CKE
0.2V
Note: 1. Measured with output open. Addresses are changed only one time during
t
CC
(min)
.
2. Refresh period is 64ms. Addresses are changed only one time during
t
CC
(min)
.
3.
t
CC
: Clock cycle time.
t
RC
: Row cycle time.
t
CCD
: Column address to column address delay time.