T6L24

2002-01-07

TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

T6L24

Source Driver for TFT LCD Panels

The T6L24 is a 240-channel-output source driver for TFT LCD
panels.
The T6L24 offers both low power consumption and high
integration circuit due to CMOS technology.

Features

l LCD drive outputs

: 240 outputs (80 outputs each for

R, G and B)

l Power supply voltage

: Digital power supply voltage

...2.7 to 5.5 V

Analog power supply voltage

...Max 5.5 V

l Sampling method

: 2 latches

l Data transfer method

: Bi directional shift register

l Operating temperature

: -20 to 75°C

l Package

: Tape carrier package (TCP)

l Switching simultaneous/sequential sampling

T6L24

2002-01-07

Pin Function

Pin Name

I/O

Function

DI/O
DO/I

I/O

Vertical shift data I/O pins

These pins are used to input and output shift data. These pins are switched between input and
output by setting the U/D pin as shown below:

U/D DI/O DO/I

H Input

Output

L Output

Input

When set for input

When

MODE

= low

The data is latched into the internal logic synchronously with the rising edge of CPH. The data
is sampling in sequentially, starting at the rise of CPH after three clock period.

When

MODE

= high

The data is latched into the internal logic synchronously with the rising edge of CPH. The data
is sampling in sequentially, starting at the next rise of CPH.

When set for output

When two or more T6L24s are cascaded, this pin outputs the data to be fed into the next stage.

U/D I

Transfer direction select pin

This pin specifies the direction of sampling performed by the sample-and-hold circuit.
When

MODE

= low

When U/D is high, data is sampled in the sequence
SA1

® SB1 ® SC1 ® SA2 ® SB2 ® × × × ® SC80

When U / D is low, the sequence is reversed to give
SC80

® SB80 ® SA80 ® SC79 ® × × × ® SA1

When

MODE

= high

When U/D is high, data is sampled in the sequence
SA1, SB1, SC1

® SA2, SB2, SC2 ® × × × ® SA80, SB80, SC80

When U/D is low, the sequence is reversed to give
SC80, SB80, SA80

® SC79, SB79, SA79 ® × × × ® SC1, SB1, SA1

CPH I

Shift clock input

This clock sequentially shift the signals necessary to sample the data that are output to the LCD
drive output pins (QA1 to QC80).

CX I

Sample-and-hold switching pin.

This pin switches between two sample-and-hold circuits.

MODE I

Sampling mode setting pin.

When

MODE

= high

Simultaneously samples three video output signals corresponding to the LCD drive outputs.

When

MODE

= low

Sequentially samples the video output signals corresponding to the LCD drive outputs.

VA
VB
VC

Analog signal input

These pins accept as their input the analog signals that are output to the LCD drive output pins.

C-COM I

Sample and hold reference voltage input

This is the reference voltage for the sample-and-hold circuit.
Apply stable DC voltage to the pin.

QA1 to QA80
QB1 to QB80

QC1 to QC80

LCD drive output pins

These pins output one of the analog signal inputs (VA, VB and VC) after it has been sampled and
held by the sample-and-hold circuit.

Power supply for the device's logic block

Power supply for the device's high-voltage block

Digital GND for the device

Analog GND for the device

TST

Test pin

Use the pin as required.

T6L24

2002-01-07

Device Operation

(1) Analog signal sampling

Data transfer begins with the assertion of DI/O (U/D = high) or DO/I (U/D = low).

<Simultaneous sampling>

When

MODE

=
=
=
= high, U/D ==== high

A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the
analog signal to be output to (SA1, SB1, SC1) is sampled at next rising edge of CPH. In this way, all
analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and
the analog signals are output to (SA2, SB2, SC2), (SA3, SB3, SC3) and so on.
After the device finishes sampling the data for (SA80, SB80, SC80), it automatically enters standby
state. Unless DI/O is asserted again, no data is sampled, irrespective of whether CPH are input to the
device.

When

MODE

=
=
=
= high, U/D ==== low

A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the
analog signal to be output to (SA80, SB80, SC80) is sampled at next rising edge of CPH. In this way, all
analog signals are sampled of each three channel sequentially at the rising edge of CPH and so on, and
the analog signals are output to (SA79, SB79, SC79), (SA78, SB78, SC78) and so on.
After the device finishes sampling the data for (SA1, SB1, SC1), it automatically enters standby state.
Unless DO/I is asserted again, no data is sampled, irrespective of whether CPH are input to the device.

<Sequential sampling>

When

MODE

=
=
=
= low, U/D ==== high

A high on DI/O is latched into the internal logic synchronously with the rising edge of CPH, and the
analog signal to be output to SA1 is sampled at the rising edge of CPH after three clock period. In this
way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog
signals are output to SB1, SC1, SA2, SB2, SC2, SA3, SB3, SC3 and so on.
After the device finishes sampling the data for SC80, it automatically enters standby state. Unless DI/O
is asserted again, no data is sampled, irrespective of whether CPH are input to the device.

When

MODE

=
=
=
= low, U/D ==== low

A high on DO/I is latched into the internal logic synchronously with the rising edge of CPH, and the
analog signal to be output to SC80 is sampled at the rising edge of CPH after three clock period. In this
way, all analog signals are sampled sequentially at the rising edge of CPH and so on, and the analog
signals are output to SB80, SA80, SC79, SB79, SA79, SC78, SB78, SA78 and so on.
After the device finishes sampling the data for SA1, it automatically enters standby state. Unless DO/I
is asserted again, no data is sampled, irrespective of whether CPH are input to the device.

T6L24

2002-01-07

(2) LCD drive output

The T6L24 has two sample-and-hold circuits called Sample-And-Hold (1) and (2).
These two circuits alternate between serving as the output and the sample-and-hold. Which circuit
fulfils which function is determined by the setting of the CX pin.

CX Output

Sample-and-Hold

Sample-and-hold circuit (1)

Sample-and-hold circuit (2)

Sample-and-hold circuit (1)

The analog signal inputs VA, VB and VC are output as follows: VA is sent to the LCD driver output pins
SC1 to SC80, VB is sent to output pins SB1 to SB80, and VC is sent to output pins SA1 to SA80. The
analog signal inputs will be sent to LCD driver output pins by the setting of the CX pin as shown below:

Note: The CX pin setting must not be altered while the device is sampling data.

(3) Vertical shift data output

When MODE

=
=
=
= high

The output DO/I (U/D = high) or DI/O (U/D = low) is driven high for one clock period synchronously with

the rising CPH, one clock period before the data (which is to be output to (SA80, SB80, SC80) or (SA1,
SB1, SC1)) is latched into the shift register.

When MODE

=
=
=
= low

The output DO/I (U/D = high) or DI/O (U/D = low) is driven high for one clock period synchronously with

the rising CPH, one clock period before the data (which is to be output to SA80 or SC1) is latched into
the shift register.

When using two or more of these devices to drive a large screen, connect the vertical shift data output
from the first stage of the LCD driver directly to the vertical shift data input at the next stage. In this
way, the device's LCD drive output pin can easily be expanded as necessary.

(4) Sample-and-hold reference voltage

(C-COM)

The device's sample-and-hold circuits are configured using the internal capacitors. The C-COM pin is
used to supply the reference voltage for these circuits. Apply stable DC voltage to the pin.

T6L24

2002-01-07

Absolute Maximum Ratings

(AV

=
=
=
= DV

=
=
=
= 0 V)

Parameter Symbol

Rating

Unit

Relevant

Supply Voltage (1)

-0.3 to 6.5

Supply Voltage (2)

-0.3 to 6.5

Digital Input Voltage

-0.3 to DV

+ 0.3

(Note 1)

Reference Analog Voltage

-0.3 to AV

+ 0.3

(Note 2)

Storage Temperature

stg

-55 to 125

°C

Recommended Operating Conditions

(AV

=
=
=
= DV

=
=
=
= 0 V)

Parameter Symbol

Rating

Unit

Relevant

Supply Voltage (1)

2.7 to 5.5

Supply Voltage (2)

to 5.5

Reference Analog Voltage

0.2 to AV

- 0.2

(Note 2)

Operating Temperature

-20 to 75

°C

MODE

= high

CLK

0.5

Operating
Frequency

MODE

= low

CLK

0.5

Output Load Capacitance

50 (max)

pF/PIN

Input Capacitance

10 (max)

Electrical Characteristics

DC Characteristics

(DV

=
=
=
= 3.0 ±±±± 0.3 V, AV

=
=
=
= 5.0 ±±±± 0.5 V, AV

=
=
=
= DV

=
=
=
= 0 V, Ta ====

-
-
-
-

20 to 75°C)

Parameter Symbol

Test

Circuit

Test Conditions

Min

Typ.

Max

Unit

Relevant Pin

Low Level

0.2

Input Voltage

High Level

0.8

V (Note

Low Level

= 40 mA 0

0.3

Output Voltage

High Level

= -40 mA

0.3 V

DI/O,

DO/I

Output Offset Voltage

OFF

-20

SA1 to SC80

Input Current

-1

µA (Note

Current Consumption (1)

mA DV

Current Consumption (2)

mA AV

Note 1: All input pins except the analog signal input pins (VA, VB, VC)
Note 2: Analog signal input pins (VA, VB, VC)

T6L24

2002-01-07

AC Characteristics

(DV

=
=
=
= 3.0 ±±±± 0.3 V, AV

=
=
=
= 5.0 ±±±± 0.5 V, AV

=
=
=
= DV

=
=
=
= 0 V, Ta ==== ----20 to 75°C)

Parameter Symbol

Test

Circuit

Test Conditions

Min

Typ.

Max

Unit

MODE

= low

0.5

Operating Frequency

fCPH

(1 / tCPH)

MODE

= high

0.5

MHz

CPH Pulse Width H

CWH

CPH Pulse Width L

CWL

Data Set-up Time

DSU

Data Hold Time

DHD

CX Set-up Time

tpdC

CPH

period

Output Delay Time 1

tpdDO

= 30 pF

16 ns

Output Delay Time 2

tpdDS

= 50 pF Target output voltage

(90%, 10%)

8 µs

Output Delay Time 3

tpdDX

= 50 pF, Target output voltage

15 µs

T6L24

2002-01-07

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000707EBE

RESTRICTIONS ON PRODUCT USE

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