TA1296FN

2002-02-12

TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic

TA1296FN

Down-Converter IC with PLL for Satellite Tuner

The TA1296FN is a wideband down-converter which can

operate at input frequency ranging from 850 MHz to 2200 MHz.
Intended primarily for use in satellite tuners, this IC includes an
oscillator, a mixer, an IF amplifier and a PLL.

The I

C bus data format is used as the data control format.

The supply voltage of 5.0 V helps minimize the tuner's power

dissipation, while the compact 30-pin SSOP package allows the
tuner to be kept small.

Features

· Supply voltage: 5.0 V (typ.)
· Wide input frequency range
· Low phase noise oscillator
· Standard I

C bus format control

· 4-MHz (X'tal) buffer output pin
· Reference oscillator input change-over switch [X'tal or external input]
· 33-V high-voltage tuning amplifier built-in
· 3-bit input port (for read mode)
· 2-bit band switch drive transistor (for write mode)
· 5-level AD converter
· Frequency step: 62.5 kHz or 125 kHz (for 4-MHz X'tal)
· 4-address setting via address selector
· Power-on reset circuit
· ×1/2 prescaler
· Flat compact package: SSOP30-P-300-0.65 (0.65-mm pitch)

Power-On Reset Operation Conditions

· Frequency step: 125 kHz
· Charge pump output current: ±50 mA
· Counter data: all [0]
· Band driver: OFF
· Tuning amplifier: OFF

Note 1: This device can easily be damaged by high voltages or electrical fields. For this reason, please handle it

with care.

Weight: 0.17 g (typ.)

Preliminary

TA1296FN

2002-02-12

Pin Functions

Pin No.

Pin Name

Function

Interface

GND1

Ground pin for oscillator circuit block

Power supply pin for local oscillator
circuit block

Oscillator

Local oscillator circuit

GND2

Ground pin for oscillator circuit block

Vt Output

Tuning voltage output pin with built-in
tuning amplifier

Reference Input

(4-MHz input)

Crystal oscillator input

Can be switched between X'tal
oscillator and external input using pin
24 (XO switch).

Power supply pin for PLL circuit block

Reference signal
buffer output

Buffer output pin for reference signal

GND3

Ground pin for PLL circuit block

GND1

GND3

1 k

5 k

1 k

GND3

5 k

GND3

TA1296FN

2002-02-12

Pin No.

Pin Name

Function

Interface

Band 1 Output

Band 2 Output

Output can be controlled by setting
band switch data.

GND4

Ground pin for IF amplifier circuit
block

IF Output

IF output pin

Power supply pin for IF amplifier
circuit block

GND5

Ground pin for IF amplifier circuit
block

XO Switch

Determines reference signal input.

If connected to ground:
X'tal oscillator.

If open or connected to V

external input

ADR Set

The address for hardware bit setting
can be selected by applying voltage to
this pin.

4 programmable address can be
programmed.

GND6

Ground pin for mixer circuit block

GND3

18, 19

GND4

GND3

25 k

1 k

GND3

50 k

150

100

1 k

100

TA1296FN

2002-02-12

Absolute Maximum Ratings

(Ta

=
=
=
=

25°C)

Parameter Pin

No.

Symbol

Rating

Unit

Supply voltage

Tuning amplifier voltage

VBT

Power dissipation

1130

(Note 2)

Operating temperature

opr

20 to 85

°C

Storage temperature

stg

55 to 150

°C

Note 2: 50 mm

50 mm

1.6 mm, 40% Cu board

If Ta

25°C, derate this value by 9.1 mW/°C.

Recommended Operating Conditions

Pin No.

Symbol

Min

Typ.

Max

Unit

Local oscillator block

4.5

5.0

5.5

PLL block

4.5

5.0

5.5

IF amplifier block

4.5

5.0

5.5

Mixer block

4.5

5.0

5.5

Electrical Characteristics

DC Characteristics

(unless otherwise specified, V

=
=
=
=

5 V, Ta

=
=
=
=

25°C)

When power on, counter data

=
=
=
=

all [0], VBT

=
=
=
=

OFF, CP1

=
=
=
=

CP0

=
=
=
=

0 and band

=
=
=
=

all [0]

Parameter Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

5.0

7.5

10.0

16.0

20.0

25.5

16.5

20.0

24.5

Power supply current

9.5

12.5

16.0

Total

-total

47.0

60.0

76.0

TA1296FN

2002-02-12

Down-Converter Block

AC Characteristics

(unless otherwise specified, V

=
=
=
=

5 V, Ta

=
=
=
=

25°C)

Parameter Symbol

Test

Circuit

Test Condition

(Note 4)

Min Typ. Max

Unit

RF input frequency

Mfin

850

2200

MHz

RF input level

MPin

dBmW

IF output frequency

Afin

350

550

MHz

IF output impedance

(Note 3)

AZout

Single-end

Local oscillator frequency

1300

2700

MHz

fRF

898 MHz

27.5

fRF

1598 MHz

27.5

34.5

Conversion gain

(Note 3)

CG 2

fRF

2198 MHz

32.5

fRF

898 MHz

9 10.5

fRF

1598 MHz

9 11

Noise figure

(Note 3)

NF 3

fRF

2198 MHz

11 13

fRF

898 MHz

6.5

8.5

fRF

1598 MHz

6.5

8.5

IF output power level

(Note 3)

Apsat 2

fRF

2198 MHz

6.5

8.5

dBmW

898 MHz, fud

903 MHz

18.5

1598 MHz,

fud

1603 MHz

15 17

inter modulation

(IF output intercept point)

(Note 3)

IP3 4

2198 MHz,

fud

2203 MHz

15 17

dBmW

fRF

898 MHz

fRF

1598 MHz

Conversion gain shift

(Note 3)

CGs 2

fRF

2198 MHz

fosc

1300 MHz

4.5

fosc

2000 MHz

3.5

Frequency shift

(PLL OFF)

fB 2

fosc

2600 MHz

3.5

MHz

fosc

1300 MHz

fosc

2000 MHz

Phase noise

(with 10-kHz offset)

PN 2

fosc

2600 MHz

dBc/

fosc

1300 MHz

fosc

2000 MHz

RF pin

LO leak level

LORF 2

fosc

2600 MHz

dBmW

fosc

1300 MHz

fosc

2000 MHz

IF pin

LO leak level

LOIF 2

fosc

2600 MHz

32.5

dBmW

Note 3: IF output frequency

402 MHz

Note 4: IF output load

TA1296FN

2002-02-12

PLL Block

(unless otherwise specified, V

=
=
=
=

5 V, Ta

=
=
=
=

25°C)

Parameter Symbol

Test

Circuit

Test Condition

(Note 4)

Min Typ. Max

Unit

Tuning amplifier output voltage (close)

Vt out

VBT

33 V, RL

33 k

0.3

Tuning amplifier maximum current

Ivt

VBT

33 V

X'tal negative resistance

XtR

2.5

X'tal operating range

OSCin

XO-SW:GND (X'tal oscillator
mode)

[NDK (AT-51), 4 MHz used]

3.2

4.5

MHz

X'tal external input level

Xo extl

100

1000

p-p

X'tal external input frequency

X-ext

XO-SW: V

2 or open

MHz

Ratio setting range

16-bit counter

1024

65,535

Logic input low voltage

0.3

1.5

Logic input high voltage

SDA and SCL pins

2.4

0.3

Logic input current (low)

I BsL

Logic input current (high)

I BsH

SDA and SCL pins

ACK output voltage

VACK

ISINK

3 mA

0.4

CP1

[0], CP0

[0]

CP1

[0], CP0

[1]

100

145

CP1

[1], CP0

[0]

180

240

345

Charge pump output current

Ichg

CP1

[1], CP0

[1]

375

490

700

Band driver drive current

IBD

B1, B2

Band driver voltage drop

VBDsat

B1, B2: IBD

10-mA drive

0.2

Comparator pin input voltage

VCMP

IP-1, IP-2, IP-3

Comparator pin low voltage

VLCMP

IP-1, IP-2, IP-3

1.5

Comparator pin high voltage

VHCMP

IP-1, IP-2, IP-3

2.7

Xo buffer output level

Xo out

1-k

, 10-pF load

X'tal: NDK (AT-51), 4 MHz
used.

4-MHz level monitored on
oscilloscope using FET probe
(1 M

, 1.9 pF).

350

500

p-p

TA1296FN

2002-02-12

Bus Line Characteristics

Parameter Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

SCL clock frequency

fSCL

100

kHz

Bus free time between a STOP and
START conditions

BUF

4.7

Hold time for repeated START
condition

; STA

SCL clock low period

LOW

4.7

SCL clock high period

HIGH

Set-up time for repeated START
condition

; STA

4.7

Data hold time

; DAT

Data set-up time

; DAT

250

Rise time for SDA and SCL signals

1000

Fall time for SDA and SCL signals

300

Set-up time for STOP condition

tsU; STO

Please refer to data timing
chart.

; STA

tSU; STO

SDA

SCL

BUF

LOW

; STA

; DAT

HIGH

; DAT t

; STA

P S

Figure 1 I

C Bus Data Timing Chart (rising-edge timing)

TA1296FN

2002-02-12

Test Conditions

(1) Conversion

gain

RF input level = -40dBmW

(2) Noise

figure

NF meter direct-reading value (DSB measurement)

(3) IF output power level

Measure maximum IF output level.

(4) 3

inter modulation

· fd (fd input level = -40dBmW)

· fud = fd + 5 MHz (fud input level = -40dBmW)

Calculate IF output intercept point as follows:

IP3 = S/(N - 1) + P [dBmW]

S: suppression level

N: 3 P: IF output level

(5) Conversion gain shift

Conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges

= 5 V to 4.5 V or V

= 5 V to 5.5 V.

(6) Frequency shift (PLL OFF)

Frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges

1 = 5 V to 4.5 V or V

1 = 5 V to 5.5 V.

(7) Phase

noise

(offset

= 10 kHz)

Measure phase noise at 10-kHz offset.

(8) RF pin local-leak level

Measure worst-case local-leak level for RF pin (with IF output pin open).

(9) IF pin local-leak level

Measure worst-case local-leak level for IF pin (with RF input pins shorted using 50-W resistor).

TA1296FN

2002-02-12

PLL Block

--I

C Bus Communications Control--

The TA1296FN conforms to Standard Mode I

C bus format.

C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for

processing status data).

Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte.
If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected.
Address can be set using the hardware bits. 4 programmable address can be programmed.
Using this setting, multiple frequency synthesizers can be used on the same I

C bus line.

The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin

25). The address is selected according to the setting of these bits.

During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low.
If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low

during the next acknowledgment.

A) Write mode (setting command)

When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte

4 holds frequency data, the divider ratio setting and function setting data; and byte 5 holds output
port data.

Data is latched and transferred at the end of byte 3, byte 4 and byte 5.
Byte 2 and byte 3 are latched and transferred as a byte pair.
Once a valid address has been received and acknowledged, the data type can be determined by

reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1,
the data is function-setting or band output data.

Additional data can be input without the need to transmit the address data again until the I

C bus

STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible).

If a data transmission is aborted, data programmed before the abort remains valid.

[[BYTE 1]]

The address data for byte 1 can be set using the hardware bit.
The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 25).

[[BYTE 2, BYTE 3, (N15) in BYTE 4]]

Byte 2 , byte 3 and N15 of byte 4 control the 16-bit programmable counter ratio and are stored

in the 16-bit shift register together with frequency setting counter data.

The program frequency can be calculated using the following formula:

fosc = 2 ´ fr ´ N

fosc: Program frequency
fr: Phase comparator reference frequency
N: Counter total divider ratio

fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio

set in byte 4 (the control byte).

(fr = X'tal oscillator frequency/reference divider ratio)

The reference frequency divider ratio can be set to 1/64 or 1/128.
When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step

frequencies are 125 kHz and 62.5 kHz.

[[BYTE 4]]

Byte 4 is a control byte used for selecting functions. Bit 4 (CP1) and bit 5 (CP0) determine the

output current of the charge pump circuit.

If bit 4 and bit 5 are set to [CP1]:[CP0] = 00, the output current is set to ±50 mA.

If bit 4 and bit 5 are set to [CP1]:[CP0] = 01, the output current is set to ±100 mA.

If bit 4 and bit 5 are set to [CP1]:[CP0] = 10, the output current is set to ±240 mA.

If bit 4 and bit 5 are set to [CP1]:[CP0] = 11, the output current is set to ±490 mA.

Bit 7 (Rs) can be used to set the X'tal reference frequency divider ratio. If bit 7 is set to 0, the

X'tal divider ratio is 1/128 (with a frequency step of 62.5 kHz). If it is set to 1, the X'tal divider
ratio is 1/64 (with a frequency step of 125 kHz).

Bit 8 (OS) can be used to set the charge pump driver amplifier output setting. If bit 8 is set to 0,

the output is ON (the normal setting). If it is set to 1, the output is OFF.

TA1296FN

2002-02-12

[[BYTE 5]]

Byte 5 can be used to select Test Mode and to control the output ports (band 1 and band 2).
Bit 1, bit 2 and bit 3 (T2, T1 and T0) can be used to set up Test Mode. These bits determine the

phase comparator reference signal output and the counter divider output.

Bit 5 (for B2) and bit 8 (for B1) can be used to control the output ports. When either of these

bits is set to 0, the corresponding port is turned OFF. When either of these bits is set to 1, the
corresponding port is turned ON. Each output port can be driven at less than 10 mA.

B) Read mode (status request)

When Read Mode is selected, the power-on reset operation status, phase comparator lock detector

output status, comparator input port status and 5-level AD converter pin input voltage status are
output to the master device.

Bit 1 (POR) indicates the power-on reset operation status. When the power supply voltage V

2 is

cut off, this bit is set to 1. Bit 1 is reset to 0 when a voltage of 3 V or higher is applied to V

2 and

transmission is requested in Read Mode. At this point the new status is output. (bit 1 is also set to 1
when V

2 is turned ON.)

Bit 2 (FL) indicates the phase comparator lock status. When the phase comparator is locked, 1 is

output. When the phase comparator is unlocked, 0 is output.

Bit 3, bit 4 and bit 5 (I-P3, I-P2, I-P1) indicate the input comparator status. I-P3, I-P2 and I-P1

indicate the status of input ports I-P3, I-P2 and I-P1 (pins 13, 14 and 15) respectively. The input
voltage status for each comparator input port pin is output to the master device. High is indicated by
1. Low is indicated by 0. High represents a voltage of above 2.7 V applied to the corresponding pin.
Low represents an applied voltage of below 1.5 V.

Bit 6, bit 7 and bit 8 (A2, A1 and A0) indicate the status of the five-level AD converter. The voltage

applied to the AD converter input pin (pin 3) is output after being resolved to one of five levels.

To see the bit values output for the five resolution levels and to see how these levels correspond to

the voltage applied to the AD converter input pin (ADCin-pin 12), please refer to the table entitled A2,
A1 and A0: Five-level AD converter status (e.g. the AFT output voltage data can be given to the
master device).

Data Format

A) Write

mode

MSB

LSB

Address

Byte 1 1 0 0 0

MA1

MA0

R/W

ACK

Divider Byte 1

N14

N13

N12

N11

N10

ACK

Divider

Byte

2 N7 N6 N5 N4 N3 N2 N1 N0

ACK

(L)

4 Control

Byte

N15

CP1

CP0

Rs OS

ACK

(L)

5 Band

Byte

ACK

(L)

: Don't care

ACK: Acknowledged

(L): Latch and transfer timing

B) Read

mode

MSB

LSB

Address

Byte 1 1 0 0 0

MA1

MA0

R/W

ACK

2 Status

Byte

POR

I-P3

I-P2

I-P1

ACK: Acknowledged

TA1296FN

2002-02-12

Data Specifications

· MA1 and MA0: programmable hardware address bits

MA1

MA0

Voltage Applied to Address Pin

0 to 0.1V

OPEN or 0.2V

2 to 0.3V

0.4V

2 to 0.6V

0.9V

2 to V

· N15-N0: programmable counter data

· CP1 and CP0: charge pump output current setting

CP1

CP0

Output Current (

50 (typ.)

100 (typ.)

240 (typ.)

490 (typ.)

· Rs: reference frequency divider ratio selection bit.

Rsa

Divider Ratio

Step Frequency

Phase Comparator Reference

Frequency

1/128

62.5 kHz

31.25 kHz

1/64

125 kHz

62.5 kHz

· OS: tuning amplifier control bit

0: Tuning amplifier ON (normal operation)
1: Tuning amplifier OFF

· T2, T1 and T0: test mode setting bits

Parameter

Notes

Normal operation

OFF

Charge pump is OFF.

SINK

Only charge pump sink current is ON.

Charge pump

SOURCE

Only charge pump source current is ON.

Reference signal output

Reference signal output (check output: ADC)

1/2 counter divider output

1/2 counter output (check output: ADC)

Phase comparator test

Comparative signal input: SDA

Reference signal input: SCL

: DON'T CARE

Note 5: When Test Mode is used, the tuning amplifier control bit OS is 0, signifying normal operation.

To test the counter divider output, programmable counter data input is required.

TA1296FN

2002-02-12

(4) Slave

address

R/W

Purchase of TOSHIBA I

C components conveys a license under the Philips I

C Patent Tights to use

these components in an I

C system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

Handling Precautions

1. The device should not be inserted into or removed from the test jig while a voltage is being applied to it:

otherwise the device may be degraded or break down.
Also, do not abruptly increase or decrease the power supply to the device (see figure 1).
Overshoot or chattering in the power supply may cause the IC to be degraded.
To avoid this, filters should be placed on the power supply line.

2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the

device's performance. TOSHIBA intend neither to recommend the configuration or related values of the
peripheral circuits nor to manufacture such application systems in large quantities.
Please note that the high-frequency characteristics of the device may vary depending on the external
components, the mounting method and other factors relating to the application design. Therefore, the
evaluation of the characteristics of application circuits is the responsibility of the designer.
TOSHIBA only guarantee the quality and characteristics of the device as described in this datasheet and
do not assume any responsibility for the customer's application design.

3. In order to better understand the quality and reliability of TOSHIBA semiconductor products and to

incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor
Reliability Handbook (integrated circuits) published by TOSHIBA Semiconductor Company.
This handbook can also be viewed on-line at the following URL:
<http://www.semicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm>.

1 ms

Time

10%

90%

6 V (

38 V (VBT)

uppl

y v

o
l
t
age

Figure 1

TA1296FN

2002-02-12

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability
Handbook" etc..

The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer's own risk.

The products described in this document are subject to the foreign exchange and foreign trade laws.

The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.

The information contained herein is subject to change without notice.

000707EBA

RESTRICTIONS ON PRODUCT USE

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