TENTATIVE TB31356AFL

Nov. 27, 2002 PAGE 1

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000630EBA1

TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

T B 3 1 3 5 6 A F L

1.8GHz,600MHz DUAL-PLL FREQUENCY SYNTHESIZER

The TB31356AFL is a PLL synthesizer used for application

of the digital mobile communication and similar other
applications.

The

device

features

two

independently-controllable, built-in PLLs.

FEATURES

Operating frequency PLL1 : 700 to 1800MHz

PLL2 : 40 to 600MHz

Current consumption Total : 3.7mA(PLL1+PLL2+XIN)

(Typ.)
PLL1 : 2.7mA (PLL1+XIN) (Typ.)
PLL2 : 1.1mA (PLL2+XIN) (Typ.)
(XIN=0.1mA Typ.)

Operating voltage

: 2.4 to 3.3V

Independent battery save supported

Compact leadless package : QON16pin(0.65mm pitch)

LPF

BS-PLL1

BS-PLL2

VCC-PLL1

LPF

CLK

DATA

STB

TCXO

VCC-PLL2

PLL1

16/17

PLL2

64/65

QON16-P-0404-0.65

Weight : 0.04g (Typ.)

BLOCK DIAGRAM

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 2

PIN FUNCTION (The value of resistor and capacitor are typical.)

No.

PIN NAME

FUNCTION

INTERNAL EQUIVALENT

CIRCUIT

FIN1

PLL1 prescaler input pin. Inputs

frequency from VCO.

VCC

GND

Ground pin.

CP1

Charge pump output pin for PLL1.
Constant current output.

VCC

GND

VCC-PLL1 Power supply pin (PLL1).

BS-PLL2

PLL2 battery saving pin.

GND

Lock detection output pin. Open drain
output. PLL to be detected can be
switched by serial data.

GND

PLL2 setting frequency switch pin.

GND

XIN

Reference oscillator input pin.

VCC

GND

VCC-PLL2 Power supply pin (PLL2).

16K

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 4

DESCRIPTION OF FUNCTION AND OPERATION

(1) Serial data control

TB31356AFL operates according to serial data program. Serial data is input from the clock (CLK),
data (DATA), and strobe (STB) pin.

(2) Entry of serial data

At the rising edge of each clock pulse, data is sent to the internal shift register from the LSB

sequentially. When all the data is sent, set the strobe pin to high. At this rising edge,
data is stored in latches depending on the control contents. At the same time as data is
stored, control starts.

The CLK, DATA, and STB pin contain the schmitt trigger circuit to prevent the data

errors by noise, etc.

At power on, send the option control data before any other divider data.

(3) Serial data input timing

(4) Serial data groups and group code

The IC has control divided into five groups so that they may be controlled independent of

one another. Each group is identified by three-bit group code attached at the data end.

Bit before

preceding one

Preceding bit

Last bit

Control contents

PLL1 programmable divider (FIN1) data

PLL2 programmable divider (FIN2) data

PLL1 reference divider (XIN) data

PLL2 reference divider (XIN) data

Option Control

CLK

DATA

STB

=>0.1

=>0.04

=>0.02

=>0.04

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 5

(5) PLL1 divider data

Consist of a 6-bit swallow counter (programmable counter), a 12-bit programmable counter, and

a 1/64, 1/65 two modulus prescaler.

By sending any data to the swallow counter and programmable counter, number of division can

be set from 4032 to 262143.

LSB

A0 A1 A2 A3 A4 A5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SB1 SB2 SBX 0 0 0

Swallow counter : A Programmable counter : N Battery saving
Group code

Number of divisions = 64N+A (4032 =< Number of divisions =< 262143)
A=A0+A1*2

.......+A5*2

A : Value of A counter

N=D0+D1*2

+.......+D11*2

N : Value of N counter

(6) PLL2 divider data

Consist of a 4-bit swallow counter (programmable counter), a 11-bit programmable counter, and

a 1/16, 1/17 two modulus prescaler.

By sending any data to the swallow counter and programmable counter, number of division can

be set from 240 to 32767.

LSB

A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LA SB1 SB2 SBX 0 1 0

Swallow counter : A Programmable counter : N Battery saving
Group code

Number of divisions = 16N+A (240 =< Number of divisions =< 32767)
A=A0+A1*2

.......+A3*2

A : Value of A counter

N=D0+D1*2

+.......+D10*2

N : Value of N counter

(7) PLL1 reference divider data

Consist of a 12-bit reference counter (programmable counter).

By sending any data to the reference counter, number of division can be set from 4 to 4095

LSB

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SB1 SB2 SBX 0

Reference counter Battery saving Group code

D=D0+D1*2

+.........D11*2

4 =< Number of divisions =< 4095

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 6

(8) PLL2 reference divider data

Consist of a 12-bit reference counter (programmable counter).

By sending any data to the reference counter, number of division can be set from 4 to 4095.

LSB

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LA SB1 SB2 SBX 0

Reference counter Battery saving Group code

D=D0+D1*2

+.........D11*2

4 =< Number of divisions =< 4095

PLL2 divider data

LA External Pin

Resistor

LA = "0"

LA = "1"

(9) Option Control

LSB

0 CP1 CP2 CP3 CP4 LD1 LD2 SB1 SB2 SBX 1

Charge pump current Lock detection Battery saving Group code

Charge pump output current

This IC uses a constant current output type charge pump circuit. Output current is varied by serial data "CP1"
and "CP2".

CP1

CP3

PLL1 Charge Pump

Output Current

CP2

CP4

PLL2 Charge Pump

Output Current

4mA

2mA

1mA

0.5mA

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 7

Lock detection

A signal indicating whether the PLL has phase-locked to the desired frequency is presented to the LD pin.
The PLL to be detected in this way can be selected by setting two bits, LD1 and LD2, as shown in the table
below.

LD1

LD2

Detected PLL

Not detected (fixed low)

PLL2

PLL1

Only when both PLL1 and PLL2 are

detected

Locked in phase = open, Unlocked = low, Power-down mode = open

Power-down mode

The PLL1, PLL2, and crystal oscillator circuit can be switched between operating and power-down
modes by using three bits--SB1, SB2, and SBX. The table below shows how operation is controlled by using
these bits and external battery save pins.

External Pin

Serial Data

Operation State

BS1

BS2

SB1

SB2

SBX

PLL1

PLL2

Buffer

OFF

Notes1 : ON : operating, OFF : power-down (not operating), * : don't care
Notes2 : Switching between operating and battery saving (power down) mode by using serial data is
renewed at the rising edge of strobe signal.
Notes3 : Switching between operating and battery saving (power down) mode by using external pin
(BS-PLL1,BS-PLL2) is controlled real-time.
Notes4 : Immediately after power on, need a initial setting by serial data before operation state "ON".

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 8

MAXIMUM RATINGS (Ta=25°C)

CHARACTERISTIC

SYMBOL

RATING

UNIT

Power Supply Voltage

VCC-PLL1 , VCC-PLL2

3.6

Power Dissipation

240

Input Voltage

CLK , DATA , STB , LA , BS-PLL1 , BS-PLL2

3.6

Storage Temperature

Tstg

55 to +150

°C

Note: The maximum ratings cannot be exceeded even for an instant. Ple ase make sure the device is operated under

conditions not exceeding the parameters shown here.

OPERATING RANGES

CHARACTERISTIC

SYMBOL

TEST

CIR-CI

TEST CONDITION

RANGE

UNIT

Operating Voltage

Vopr

Ta=25°C

2.4 to 3.3

Operating Temperature

Topr

30 to +85

°C

FIN1

700 to 1800

MHz

FIN2

40 to 600

MHz

FXIN

5 to 30

MHz

Operating Frequency

fopr

FCLK

1k to 10M

VIN1

92 to 107

VIN2

92 to 107

Input Operating Voltage

VINopr

VXIN

97 to 113

Power Supply Voltage at
Stand-by 1

ICCQ1

VCC-PLL1 , VCC-PLL2 ,
BS1="L" , BS2="L"

0 to 10

Low Level Input Voltage

VL(SW)

BS State
BS-PLL1 , BS-PLL2 , LA,
CLK , DATA , STB

0.2 to VCC*0.2

High Level Input Voltage

VH(SW)

Active State
BS-PLL1 , BS-PLL2 , LA,
CLK , DATA , STB

VCC*0.8 to 3.3

Note 1: The allowable operating ranges stipulate conditions under which the device's basic functions can operate
normally, although accompanied by fluctuations in its electrical characteristics.
Note 2: The unit "dBµV" denotes the level at load-end. (0 dBm = 107 dBµV @50

)

TENTATIVE TB31356AFL

This specification is design target. It is subject to change without notice

Nov. 27 2002 PAGE 9

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified, Ta=25

, FIN1=1619MHz, FIN2=130MHz, XIN=14.4MHz,

VCC-PLL1=3.0V, VCC-PLL2=3.0V)

CHARACTERISTIC

SYMBOL

TEST

CIR-CI

TEST CONDITION

MIN.

TYP. MAX. UNIT

Current Consumption 1
at No Signal

Icco1

All Operating
(PLL1+PLL2+XIN)
VCC-PLL1 , VCC-PLL2
BS1="H" , BS2="H" ,
SB1="1" , SB2="1"

3.7

4.8

Current Consumption 2
at No Signal

Icco2

PLL1 Operating
(PLL1+XIN)
VCC-PLL1 , VCC-PLL2
BS1="H" , BS2="L"

2.7

3.5

Current Consumption 3
at No Signal

Icco3

PLL2 Operating
(PLL2+XIN)
VCC-PLL1 , VCC-PLL2
BS1="L" , BS2="H"

1.1

1.4

Current Consumption 4
at No Signal

Icco4

XIN Operating
VCC-PLL1 , VCC-PLL2
BS1="H" , BS2="H" ,
SB1="0",SB2="0",SB="1"

0.10

0.13

PLL1 Charge Pump Output
Current 1

ICP1

Vcp1=1/2VCC
CP1="0" , CP3="0"

2.8

4.0

5.2

PLL1 Charge Pump Output
Current 2

ICP2

Vcp1=1/2VCC
CP1="0" , CP3="1"

1.4

2.0

2.6

PLL1 Charge Pump Output
Current 3

ICP3

Vcp1=1/2VCC
CP1="1" , CP3="0"

0.7

1.0

1.3

PLL1 Charge Pump Output
Current 4

ICP4

Vcp1=1/2VCC
CP1="1" , CP3="1"

0.35

0.5

0.65

PLL2 Charge Pump Output
Current 5

ICP5

Vcp2=1/2VCC
CP2="0" , CP4="0"

2.8

4.0

5.2

PLL2 Charge Pump Output
Current 6

ICP6

Vcp2=1/2VCC
CP2="0" , CP4="1"

1.4

2.0

2.6

PLL2 Charge Pump Output
Current 7

ICP7

Vcp2=1/2VCC
CP2="1" , CP4="0"

0.7

1.0

1.3

PLL2 Charge Pump Output
Current 8

ICP8

Vcp2=1/2VCC
CP2="1" , CP4="1"

0.35

0.5

0.65

Charge Pump Off Leak Current ICP(OFF)

PLL1 , PLL2 ,
Vcp=1/2VCC

0.1

LD Output Off Leak
Current

ILD

VLD=3.3V

LD Output On Resistance

RLD(ON)

VLD=0.4V

1100

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