TC55V040AFT-55,-70
2003-08-06 1/11
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V040AFT is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5
A standby
current (at V
DD
=
3 V, Ta
=
25C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low.
There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and
output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system
applications where high speed, low power and battery backup are required. And, with a guaranteed operating
extreme temperature range of
-
40 to 85C, the TC55V040AFT can be used in environments exhibiting extreme
temperature conditions. The TC55V040AFT is available in normal and reverse pinout plastic 40-pin
thin-small-outline package (TSOP).
FEATURES
Low-power dissipation
Operating: 10.8 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
-
40 to 85C
Standby Current (maximum):
3.6 V
7
A
3.0 V
5
A
PIN ASSIGNMENT
(TOP VIEW)
40 PIN TSOP
PIN NAMES
A0~A18 Address
Inputs
1
CE , CE2
Chip Enable
R/W Read/Write
Control
OE Output
Enable
I/O1~I/O8 Data
Inputs/Outputs
V
DD
Power
GND Ground
NC No
Connection
Pin
No. 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15 16 17 18 19
20
Pin
Name A16 A15 A14 A13 A12 A11 A9
A8
R/W CE2
NC
NC
A18
A7
A6 A5 A4 A3 A2
A1
Pin
No. 21 22 23 24 25 26 27
28
29
30
31
32
33
34
35 36 37 38 39
40
Pin Name
A0
CE1
GND OE I/O1 I/O2 I/O3
I/O4
NC
V
DD
V
DD
I/O5
I/O6
I/O7
I/O8 A10 NC NC GND A17
Access Times (maximum):
TC55V040AFT
-55 -70
Access Time
55 ns
70 ns
1
CE Access Time
55 ns
70 ns
CE2 Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
Package:
TSOP40-P-1014-0.50 (AFT) (Weight: 0.32 g typ)
(Normal)
21
40
20
1
TC55V040AFT-55,-70
2003-08-06 2/11
BLOCK DIAGRAM
OPERATING MODE
MODE
1
CE CE2 OE R/W
I/O1~I/O8
POWER
Read
L H L H
Output
I
DDO
Write L
H
*
L Input
I
DDO
Output
Deselect
L H H H
High-Z
I
DDO
H
*
*
*
High-Z
I
DDS
Standby
*
L
*
*
High-Z
I
DDS
*
= don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL RATING
VALUE
UNIT
V
DD
Power Supply Voltage
-
0.3~4.6 V
V
IN
Input Voltage
-
0.3
*
~4.6 V
V
I/O
Input/Output Voltage
-
0.5~V
DD
+
0.5
V
P
D
Power Dissipation
0.6
W
T
solder
Soldering Temperature (10s)
260
C
T
stg
Storage Temperature
-
55~150 C
T
opr
Operating Temperature
-
40~85 C
*
:
-
3.0 V when measured at a pulse width of 50ns
COLUMN ADDRESS
BUFFER
A5
I/O1
MEMORY CELL ARRAY
2,048
256
8
(4,194,304)
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
SENSE AMP
A6
A7
A8
A9
A12
A11
A13
A14
CE
V
DD
GND
CE
A4
A18
A2
A0 A1
A17
A3 A10A15A16
ROW ADDRESS
DECODER
ROW ADDRESS
BUFFER
ROW ADDRESS
REG
I
STER
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
DA
T
A
C
O
NT
RO
L
CLOCK
GENERA
T
O
R
8
CE
1
CE
R/W
OE
CE2
TC55V040AFT-55,-70
2003-08-06 3/11
DC RECOMMENDED OPERATING CONDITIONS
(Ta
=
-
40 to 85C)
2.3 V~3.6 V
SYMBOL PARAMETER
MIN TYP MAX
UNIT
V
DD
Power
Supply
Voltage
2.3 3.0 3.6 V
V
IH
Input High Voltage
2.2
V
DD
+
0.3
V
V
IL
Input
Low
Voltage
-
0.3
*
V
DD
0.22
V
V
DH
Data Retention Supply Voltage
1.5
3.6 V
*
:
-
3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS
(Ta
=
-
40 to 85C, V
DD
=
2.3 to 3.6 V)
SYMBOL PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
I
IL
Input Leakage
Current
V
IN
=
0 V~V
DD
1.0
A
I
OH
Output
High
Current
V
OH
=
V
DD
-
0.5 V
-
0.5
mA
I
OL
Output
Low
Current
V
OL
=
0.4 V
2.1
mA
I
LO
Output Leakage
Current
1
CE
=
V
IH
or CE2
=
V
IL
or R/W
=
V
IL
or OE
=
V
IH
,
V
OUT
=
0 V~V
DD
1.0
A
55 ns
60
70 ns
50
l
DDO1
1
CE
=
V
IL
and CE2
=
V
IH
and
R/W
=
V
IH
and I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
V
DD
=
3 V
10%
t
cycle
1
s
10
mA
55 ns
55
70 ns
45
l
DDO2
Operating Current
1
CE
=
0.2 V and
CE2
=
V
DD
-
0.2 V and
R/W
=
V
DD
-
0.2 V, I
OUT
=
0 mA,
Other Input
=
V
DD
-
0.2 V/0.2 V
V
DD
=
3 V
10%
t
cycle
1
s
5
mA
I
DDS1
CE
=
V
IH
or CE2
=
V
IL
2 mA
Ta
=
25C
0.6
V
DD
=
3 V
10%
Ta
=
-
40~85C
6
Ta
=
25C
0.7
V
DD
=
3.3 V
0.3 V
Ta
=
-
40~85C
7
Ta
=
25C
0.05 0.5
Ta
=
-
40~40C
1
I
DDS2
(Note)
Standby Current
1
CE
=
V
DD
-
0.2 V
or CE2
=
0.2 V
V
DD
=
1.5 V~3.6 V
V
DD
=
3.0 V
Ta
=
-
40~85C
5
A
Note: In standby mode with
1
CE
V
DD
-
0.2 V, these limits are assured for the condition CE2
V
DD
-
0.2 V or CE2
0.2 V.
CAPACITANCE
(Ta
=
25C, f
=
1 MHz)
SYMBOL PARAMETER
TEST CONDITION
MAX
UNIT
C
IN
Input
Capacitance
V
IN
=
GND
10
pF
C
OUT
Output
Capacitance
V
OUT
=
GND
10
pF
Note: This parameter is periodically sampled and is not 100% tested.
TC55V040AFT-55,-70
2003-08-06 4/11
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
-
40 to 85C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55V040AFT
-55 -70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read Cycle Time
55
70
t
ACC
Address Access Time
55
70
t
CO1
Chip Enable(
1
CE ) Access Time
55
70
t
CO2
Chip Enable(CE2) Access Time
55
70
t
OE
Output Enable Access Time
30
35
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
OD
Chip Enable High to Output High-Z
25
30
t
ODO
Output Enable High to Output High-Z
25
30
t
OH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55V040AFT
-55 -70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
55
70
t
WP
Write Pulse Width
45
50
t
CW
Chip Enable to End of Write
50
60
t
AS
Address
Setup
Time
0
0
t
WR
Write
Recovery
Time
0
0
t
ODW
R/W Low to Output High-Z
25
30
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
25
30
t
DH
Data
Hold
Time
0
0
ns
AC TEST CONDITIONS
PARAMETER TEST
CONDITION
Output load
30 pF
+
1 TTL Gate
Input pulse level
0.4 V, 2.4 V
Timing measurements
V
DD
0.5
Reference level
V
DD
0.5
t
R
, t
F
5 ns
TC55V040AFT-55,-70
2003-08-06 5/11
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
-
40 to 85C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55V040AFT
-55 -70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
RC
Read Cycle Time
70
85
t
ACC
Address Access Time
70
85
t
CO1
Chip Enable(
1
CE ) Access Time
70
85
t
CO2
Chip Enable(CE2) Access Time
70
85
t
OE
Output Enable Access Time
35
45
t
COE
Chip Enable Low to Output Active
5
5
t
OEE
Output Enable Low to Output Active
0
0
t
OD
Chip Enable High to Output High-Z
30
35
t
ODO
Output Enable High to Output High-Z
30
35
t
OH
Output Data Hold Time
10
10
ns
WRITE CYCLE
TC55V040AFT
-55 -70
SYMBOL PARAMETER
MIN MAX MIN MAX
UNIT
t
WC
Write
Cycle
Time
70
85
t
WP
Write Pulse Width
50
55
t
CW
Chip Enable to End of Write
60
70
t
AS
Address
Setup
Time
0
0
t
WR
Write
Recovery
Time
0
0
t
ODW
R/W Low to Output High-Z
30
35
t
OEW
R/W High to Output Active
0
0
t
DS
Data
Setup
Time
30
35
t
DH
Data
Hold
Time
0
0
ns
AC TEST CONDITIONS
PARAMETER TEST
CONDITION
Output load
30 pF
+
1 TTL Gate
Input pulse level
V
DD
-
0.2 V, 0.2 V
Timing measurements
V
DD
0.5
Reference level
V
DD
0.5
t
R
, t
F
5 ns
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