TC58512FT
2001-03-05 1/43
Power supply
V
CC
= 2.7 V to 3.6 V
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Cell array to register 25 ms max
Serial Read Cycle
50 ns min
Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby 100
mA
Package
TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M
8 BITS) CMOS NAND E
2
PROM
DESCRIPTION
The TC58512 is a single 3.3 V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as 528 bytes 32 pages 4096 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes
32 pages).
The TC58512 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 128K 8
Register 528
8
Page size
528 bytes
Block size
(16K + 512) bytes
Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Multi Block Program, Multi Block Erase
Mode control
Serial input/output
Command control
PIN ASSIGNMENT
(TOP VIEW)
PIN
NAMES
I/O1 to I/O8
I/O port
CE
Chip
enable
WE
Write
enable
RE
Read
enable
CLE
Command latch enable
ALE
Address latch enable
WP
Write
protect
BY
/
RY
Ready/Busy
GND
Ground input
V
CC
Power
supply
V
SS
Ground
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
BY
/
RY
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide
for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer's own risk.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
000707EBA1
TC58512FT
2001-03-05 4/43
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
=
=
=
0 to 70C, V
CC
=
=
=
=
2.7 V to 3.6 V)
SYMBOL PARAMETER
MIN
MAX
UNIT
NOTES
t
CLS
CLE
Setup
Time
0
ns
t
CLH
CLE
Hold
Time
10
ns
t
CS
CE Setup Time
0
ns
t
CH
CE Hold Time
10
ns
t
WP
Write
Pulse
Width
25
ns
t
ALS
ALE
Setup
Time
0
ns
t
ALH
ALE
Hold
Time
10
ns
t
DS
Data
Setup
Time
20
ns
t
DH
Data
Hold
Time
10
ns
t
WC
Write
Cycle
Time
50
ns
t
WH
WE High Hold Time
15
ns
t
WW
WP High to WE Low
100
ns
t
RR
Ready
to
RE Falling Edge
20
ns
t
RP
Read
Pulse
Width
35
ns
t
RC
Read
Cycle
Time
50
ns
t
REA
RE Access Time (Serial Data Access)
35 ns
t
CEH
CE High Time for Last Address in Serial Read Cycle
100
ns
(2)
t
REAID
RE Access Time (ID Read)
35 ns
t
OH
Data Output Hold Time
10
ns
t
RHZ
RE High to Output High Impedance
30 ns
t
CHZ
CE High to Output High Impedance
20 ns
t
REH
RE High Hold Time
15
ns
t
IR
Output-High-impedance-to- RE Rising Edge
0
ns
t
RSTO
RE Access Time (Status Read)
35 ns
t
CSTO
CE Access Time (Status Read)
45 ns
t
RHW
RE High to WE Low
0
ns
t
WHC
WE High to CE Low
30
ns
t
WHR
WE High to RE Low
30
ns
t
AR1
ALE Low to RE Low (ID Read)
100
ns
t
CR
CE Low to RE Low (ID Read)
100
ns
t
R
Memory Cell Array to Starting Address
25
m
s
t
WB
WE High to Busy
200 ns
t
AR2
ALE Low to RE Low (Read Cycle)
50
ns
t
RB
RE Last Clock Rising Edge to Busy (in Sequential Read)
200 ns
t
CRY
CE High to Ready (When interrupted by CE in Read Mode)
1
+
t
r
(
BY
/
RY
)
m
s (1)
(2)
t
RST
Device Reset Time (Read/Program/Erase)
6/10/500
m
s
AC TEST CONDITIONS
PARAMETER CONDITION
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3 ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
C
L
(100 pF)
+
1 TTL
TC58512FT
2001-03-05 5/43
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the
BY
/
RY
pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when t
CEH
is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns,
BY
/
RY
signal stays Ready.
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
=
=
=
=
0 to 70C, V
CC
=
=
=
=
2.7 V to 3.6 V)
SYMBOL PARAMETER MIN
TYP.
MAX
UNIT
NOTES
t
PROG
Programming
Time
200
1000
m
s
t
DBSY
Dummy Busy Time for Multi Block
Programming
2 10
m
s
t
MBPBSY
Multi Block Program Busy Time
200
1000
m
s
N
Number of Programming Cycles on Same
Page
3 (1)
t
BERASE
Block
Erasing
Time
2 10 ms
(1): Refer to Application Note (12) toward the end of this document.
: 0 to 30 ns
Busy signal is not output.
A
CE
RE
t
CEH
100 ns
*
525
Busy
BY
/
RY
*
: V
IH
or V
IL
A
526 527
t
CRY
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