TCD1709D
2002-11-14
1
TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device)
TCD1709D
The TCD1709D is a high sensitive and low dark current 7500
pixels CCD image sensor.
The sensor is designed for facsimile, imagescanner and OCR.
The device contains a row of 7500 pixels photodiodes which
provide a 24 lines/mm (600DPI) across a A3 size paper. The
device is operated by 5-V (pulse), and 12-V power supply.
Features
Number of image sensing pixels: 7500 pixels
Image sensing pixel size: 7 m by 7 m on 7-m center
Photo Sensing Region
: High sensitive and low voltage dark signal pn photodiode
Clock: CMOS 5-V drive
Power supply voltage: 12-V power supply
Package: 68-pin CERDIP
Maximum Ratings
(Note 1)
Characteristics Symbol
Rating
Unit
Clock pulse voltage
V
f
Shift pulse voltage
V
SH
Reset pulse voltage
V
RS
Clamp pulse voltage
V
CP
-0.3 to 8
Power supply voltage
V
OD
-0.3 to 15
V
Operating temperature
T
opr
0
to
60
C
Storage temperature
T
stg
-25 to 85
C
Note 1: All voltages are with respect to SS pins (ground).
Weight: 16.0 g (typ.)
TCD1709D
2002-11-14
2
Pin Connections
(top view)
7500
OS2
1
2
3
4
5
6
7
OS1
f
1A1
NC
8
9
10
11
1
68
67
66
65
64
63
62
61
60
59
58
CP
RS
f
2A2
12
13
14
15
16
17
18
19
20
21
22
f
2A3
f
1A3
f
2B
SH
23
24
25
26
27
28
RS
29
30
31
32
33
34
OD
f
2A1
OD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
f
2B
f
1A2
f
1A4
f
2A4
OS4
OS3
OD
SS
TCD1709D
2002-11-14
3
Circuit Diagram
Pin Names
f1A1, 2, 3, 4 Clock (phase 1)
f2A1, 2, 3, 4 Clock (phase 2)
f2B
Last stage clock (phase 2)
SH Shift
gate
RS Reset
gate
CP Clamp
gate
OS1 Output
signal
1
OS2 Output
signal
2
OS3 Output
signal
3
OS4 Output
signal
4
OD Power
supply
SS Ground
NC No
connect
Shift gate 2
Shift gate 1
CCD analog shift register 2
D26
D27
D28
D126
D127
S1
S2
S3
S
7498
S
7499
S
7500
D127
D126
D28
D27
D26
66
68 67 65
64
63
CCD analog shift register 4
Signal
output
buffer
50
49
48
47
Signal
output
buffer
....
Photo
diode
....
Signal
output
buffer
Signal
output
buffer
CCD analog shift register 1
CCD analog shift register 3
21 23 24
45
22
3
4
5
6
19
20
1
2
OS4
SH
OS3
SS
OD
f1A4
f2A4
f2A2
f1A2
RS
CP
SS
f2B
f2A3
f2A1
f1A1
OS2
OS1
OD OD
f1A3
f2B RS CP
46
TCD1709D
2002-11-14
4
Optical/Electrical Characteristics
(Ta
=
=
=
=
25C, V
OD
=
=
=
=
12 V, V
B
B
B
B
=
=
=
=
V
SH
=
=
=
=
V
RS
=
=
=
=
V
CP
=
=
=
=
5 V (Pulse), f
B
B
B
B
=
=
=
=
1 MHz,
t
INT
(integration time)
=
=
=
=
10 ms, light source
=
=
=
=
daylight fluorescent lamp,
load resistance
=
=
=
=
100 k
W
W
W
W
)
Characteristics Symbol
Min
Typ.
Max
Unit
Note
Sensitivity R
12
15
18
V/(lxs)
PRNU
3 10 %
(Note
2)
Photo response non uniformity
PRNU (3)
5 12 mV
(Note
8)
Saturation output voltage
V
SAT
1.5
2.0
V
(Note
3)
Saturation exposure
SE
0.08
0.16
lxs (Note
4)
Dark signal voltage
V
DRK
1 3 mV
(Note
5)
Dark signal non uniformity
DSNU
2 6 mV
(Note
5)
DC power dissipation
P
D
800
1040
mW
Total transfer efficiency
TTE
92
98
%
Output impedance
Z
o
0.2 1 kW
Dynamic range
DR
2500
(Note
6)
DC signal output voltage
V
OS
4.5
6
7.5
V
(Note
7)
DC differential error voltage
|V
OSX
-V
OSY
|
300
mV
(Note
9)
Random noise
ND
s
0.7 mV (Note
10)
Note 2: Measured at 50% of SE (typ.)
Definition of PRNU : PRNU =
%
100
c
c
D
Where
?
is average of total signal outputs and
?
,
is maximum deviation from
?
under uniform
illumination (Channel 1).
In the case of 1875 pixels (channel 2, channel 3 and channel 4), the condition is the same as above too.
Note 3: V
SAT
is defined as minimum saturation output voltage of all effective pixels.
Note 4: Definition of SE: SE =
R
SAT
V
(lxs)
TCD1709D
2002-11-14
5
Note 5: V
DRK
is defined as average dark signal voltage of all effective pixels.
DSNU is defined by the difference between average value (V
DRK
) and the maximum value of the dark
voltage.
Note 6: Definition of DR : DR =
DRK
V
SAT
V
V
DRK
is proportional to tINT (integration time).
So the shorter t
INT
condition makes wider DR values.
Note 7: DC signal output voltage is defined as follows:
Note 8: PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of SE (typ.)
Note 9: DC differential error voltage is defined as follows:
Definition of DC differential error voltage = |V
OSX
- V
OSY
|
V
OSX
: Maximum DC signal output voltage
V
OSY
: Minimum DC signal output voltage
VOS
OS
SS
OS
DSNU
V
DRK
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