February 6, 2003
TM5500/TM5800
Version 1.0
Data Book
Crusoe Processors Described in this Document
Processor
Memory Interface
SKU
Package
Marking
L2 Cache
Max Core
Frequency
Core
Voltage
T
j
Max
TDP
DDR
SDR
TM5800-933
CoolRun80
DDR/SDR
5800C093310 512 KBytes 933 MHz
0.90-1.35 V
80/100 C
7.5 W
Yes
Yes
TM5800-867
CoolRun80
DDR/SDR
5800C086710 512 KBytes 867 MHz
0.90-1.35 V
80/100 C
7.5 W
Yes
Yes
TM5800-800
100C
DDR/SDR
5800A080010 512 KBytes 800 MHz
0.90-1.30 V
100 C
6.0 W
Yes
Yes
TM5500-800
100C
DDR/SDR
5500A080010 256 KBytes 800 MHz
0.90-1.30 V
100 C
6.0 W
Yes
Yes
TM5800-733
100C
DDR/SDR
5800A073310 512 KBytes 733 MHz
0.90-1.30 V
100 C
5.5 W
Yes
Yes
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Copyright 2001-2003 Transmeta Corporation. All rights reserved.
February 6, 2003
2
TM5500/TM5800 Version 1.0 Data Book
CrusoeTM Processor Model TM5500/TM5800 Version 1.0
Data Book
Revision 1.00
Revision History:
0.1
Preliminary first draft
0.2
June 13, 2001 - first release
0.3
June 26, 2002 - added 867, 900 MHz SKUs, updated memory interface descriptions, updated LongRun tables
1.00
February 6, 2003 - updated SKUs to current production SKUs
February 6, 2003
3
Table of Contents
List of Tables .......................................................................................................................................... 5
List of Figures ......................................................................................................................................... 7
Introduction
............................................................................................................................................. 9
Chapter 1
Functional Interface Description ......................................................................................................... 13
1.1
Power and Thermal Management............................................................................................. 13
1.1.1
Power Management States ........................................................................................ 13
1.1.2
LongRun Power Management .................................................................................... 16
1.1.3
LongRun Thermal Management ................................................................................. 17
1.1.4
Processor Thermal Monitoring.................................................................................... 18
1.1.5
SDRAM Power Saving Modes.................................................................................... 18
1.2
Memory Interfaces .................................................................................................................... 19
1.2.1
DDR SDRAM Interface ............................................................................................... 19
1.2.2
DDR Memory Interface Constraints............................................................................ 20
1.2.3
DDR Interface Reference Voltage Circuit ................................................................... 20
1.2.4
SDR SDRAM Interface ............................................................................................... 21
1.2.5
SDR Memory Interface Constraints ............................................................................ 22
1.3
System Memory Configurations ................................................................................................ 23
1.3.1
Recommended Memory Configurations ..................................................................... 23
1.3.2
Example Memory Configurations................................................................................ 25
1.3.3
Code Morphing Software Memory .............................................................................. 26
1.4
PCI Interface ............................................................................................................................. 27
1.4.1
PCI Bus Commands ................................................................................................... 27
1.4.2
Bus Arbitration ............................................................................................................ 28
1.5
Southbridge Sideband Signals.................................................................................................. 29
1.6
Serial Interfaces ........................................................................................................................ 29
1.7
Clocks ....................................................................................................................................... 30
1.8
JTAG Test Interface .................................................................................................................. 31
1.9
Supply Voltages ........................................................................................................................ 31
1.10
Core Voltage Regulator VRDA Interface................................................................................... 31
1.11
Power-On Sequence................................................................................................................. 32
Chapter 2
Signal Descriptions and Ballouts ....................................................................................................... 33
2.1
Signal Descriptions ................................................................................................................... 33
2.2
I/O Signal Listings ..................................................................................................................... 41
2.3
Footprint and Ballout Assignments ........................................................................................... 46
Chapter 3
Electrical Specifications ...................................................................................................................... 57
3.1
Absolute Maximum Ratings ...................................................................................................... 57
3.2
Recommended Operating Conditions ....................................................................................... 58
February 6, 2003
4
Table of Contents
3.2.1
Core Voltage ...............................................................................................................58
3.2.2
Other Voltages and Temperature Range ....................................................................59
3.2.3
PLL Supply Core Voltage Tracking/Clamp..................................................................60
3.2.4
PLLVDD/CVDD Tracking/Clamp Circuit Bypass.........................................................61
3.3
Power Supply Current ...............................................................................................................62
3.4
Thermal Design and ACPI Power..............................................................................................63
3.5
DC Specifications for I/O Signals ..............................................................................................64
3.6
Timing Specifications for I/O Signals.........................................................................................66
3.6.1
General AC Testing Conditions...................................................................................66
3.6.2
Power On Specifications .............................................................................................67
3.6.3
Input Clocks ................................................................................................................69
3.6.4
DDR SDRAM Interface ...............................................................................................71
3.6.5
SDR SDRAM Interface................................................................................................77
3.6.6
PCI Interface ...............................................................................................................82
3.6.7
Southbridge Sidebands and Power Management Interface........................................82
3.6.8
Debug Interface...........................................................................................................83
3.6.9
Code Morphing Software Boot ROM Interface............................................................84
3.6.10
Configuration (Mode-bit) ROM Interface .....................................................................85
3.6.11
JTAG Interface ............................................................................................................86
Chapter 4
Mechanical Specifications ...................................................................................................................87
4.1
Thermal Specifications ..............................................................................................................87
4.2
Package Dimensions.................................................................................................................87
4.3
Package Marking.......................................................................................................................90
February 6, 2003
5
List of Tables
Table 1:
System Power Management States ........................................................................... 13
Table 2:
Processor Power Management States ....................................................................... 14
Table 3:
LongRun Power Management Specifications............................................................. 17
Table 4:
DDR SDRAM Memory Configurations........................................................................ 19
Table 5:
SDR SDRAM Memory Configurations ........................................................................ 21
Table 6:
DDR SDRAM Base Memory Configurations............................................................... 23
Table 7:
SDR SDRAM Base or Expansion Memory Configurations......................................... 24
Table 8:
PCI Bus Commands Supported.................................................................................. 27
Table 9:
Core Clock Multipliers and PCI Interface Divisors ...................................................... 30
Table 10:
Power-On Default VRDA Output Values .................................................................... 31
Table 11:
Signal Summary ......................................................................................................... 33
Table 12:
DDR SDRAM Interface Signals .................................................................................. 34
Table 13:
Logical Alignment of DDR Byte Enables, Data Strobes and Data Bits....................... 34
Table 14:
SDR SDRAM Interface Signals .................................................................................. 35
Table 15:
Logical Alignment of SDR Clocks, Clock Enables, and Chip Selects......................... 35
Table 16:
Logical Alignment of SDR Byte Enables and Data Bits .............................................. 35
Table 17:
Memory Address Translations .................................................................................... 36
Table 18:
PCI Interface Signals .................................................................................................. 37
Table 19:
Southbridge Sideband Interface Signals .................................................................... 38
Table 20:
Serial Interface Signals............................................................................................... 38
Table 21:
Thermal/Power/System Management Signals............................................................ 39
Table 22:
JTAG Interface and Debug Signals ............................................................................ 39
Table 23:
Reserved and No Connection Signals........................................................................ 40
Table 24:
Core Voltage Sniff Signals.......................................................................................... 40
Table 25:
Power and Ground Signals......................................................................................... 40
Table 26:
Input Only Signals....................................................................................................... 41
Table 27:
Output Only Signals.................................................................................................... 43
Table 28:
Bidirectional Signals ................................................................................................... 45
Table 29:
Signal Ballout Assignments - Sorted by Ball Number................................................. 48
Table 30:
Signal Ballout Assignments - Sorted by Signal Name ................................................ 52
Table 31:
Absolute Maximum Ratings ........................................................................................ 57
Table 32:
Core Voltage Specifications........................................................................................ 58
Table 33:
Other Voltage and Temperature Specifications.......................................................... 59
Table 34:
Power Supply Current Specifications ......................................................................... 62
Table 35:
Power Specifications .................................................................................................. 63
Table 36:
DC Specifications for All Signals Except PCI and DDR SDRAM Interfaces............... 64
Table 37:
DC Specifications for DDR SDRAM Interface ............................................................ 64
Table 38:
DC Specifications for PCI Interface ............................................................................ 65
Table 39:
Thermal Diode Specifications ..................................................................................... 65
Table 40:
General AC Testing Conditions .................................................................................. 66
Table 41:
Power On Specifications............................................................................................. 67
Table 42:
Timing Specifications for Input Clocks........................................................................ 69
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