T E C H N I C A L I N F O R M A T I O N
TA2024 Preliminary, Rev. 1.0
Page 1
Stereo 10W (4
) Class-TTM Digital Audio Amplifier using
Digital Power ProcessingTM Technology
TA2024
February 27, 2001 Preliminary Rev. 1.0
General Description
The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power Amplifier
IC using Tripath's proprietary Digital Power ProcessingTM technology. Class-T amplifiers offer
both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
Computer/PC Multimedia
DVD Players
Cable Set-Top Products
Televisions
Video CD Players
Battery Powered Systems
Benefits
Fully integrated solution with FETs
Easier to design-in than Class-D
Reduced system cost with no heat sink
Dramatically improves efficiency versus
Class-AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Features
Class-T architecture
Single Supply Operation
"Audiophile" Quality Sound
0.04% THD+N @ 9W, 4
0.18% IHF-IM @ 1W, 4
6W @ 8
, 0.1% THD+N
11W @ 4
, 0.1% THD+N
High Power
10W @ 8
, 10% THD+N
15W @ 4
, 10% THD+N
High Efficiency
88% @ 10W, 8
81% @ 15W, 4
Dynamic Range = 102 dB
Mute and Sleep inputs
Turn-on & turn-off pop suppression
Over-current protection
Over-temperature protection
Bridged outputs
36-pin Power SOP package
Typical Performance
THD+N (%)
Output Power (W)
THD+N versus Output Power
1
2
5
0.02
0.01
0.05
0.1
0.2
0.5
10
1
2
5
10
20
500m
R
L
= 4
R
L
= 8
VDD = 12V
f = 1kHz
Av = 12
BW = 22Hz - 22kHz
T E C H N I C A L I N F O R M A T I O N
Page 2
TA2024 Preliminary, Rev. 1.0
Absolute Maximum Ratings
(Note 1)
SYMBOL PARAMETER
Value
UNITS
V
DD
Supply Voltage
16
V
V5
Input Section Supply Voltage
6.0
V
SLEEP
SLEEP Input Voltage
-0.3 to 6.0
V
MUTE
MUTE Input Voltage
-0.3 to V5+0.3
V
ESD
HBM
ESD Susceptibility, All pins except pins 1,4
Human Body Model (Note2) Pins 1, 4
2000
1000
V
V
ESD
MM
ESD Susceptibility, Machine Model (Note 3)
200
V
T
STORE
Storage Temperature Range
-40
to 150
C
T
A
Operating Free-air Temperature Range
0 to 70
C
T
J
Junction Temperature
150
C
Note 1 : Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2 : Human Body Model, 100pF discharged through a 1.5k resistor.
Note 3 : Machine Model, 200pF discharged directly to each pin
Note 4 : See Power Dissipation Derating in the Applications Information section.
Operating Conditions
(Note 5)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
V
DD
Supply Voltage
8.5
12
13.2
V
V
IH
High-level Input Voltage (MUTE, SLEEP)
3.5
V
V
IL
Low-level Input Voltage (MUTE, SLEEP)
1
V
Note 5: Recommended Operating Conditions indicate conditions for which the device is functional.
See Electrical Characteristics for guaranteed specific performance limits.
T E C H N I C A L I N F O R M A T I O N
TA2024 Preliminary, Rev. 1.0
Page 3
Electrical Characteristics
See Test/Application Circuit. Unless otherwise specified, V
DD
= 12V, f = 1kHz, Measurement
Bandwidth = 22kHz, R
L
= 4
, T
A
= 25
C, Package heat slug soldered to 2.8 square-inch PC pad.
SYMBOL PARAMETER
CONDITIONS MIN.
TYP.
MAX.
UNITS
P
O
Output Power
(Continuous Average/Channel)
THD+N = 0.1%
R
L
= 4
R
L
= 8
THD+N = 10%
R
L
= 4
R
L
= 8
9
5.5
12
8
11
6
16
10
W
W
W
W
I
DD,MUTE
Mute Supply Current
MUTE = V
IH
5.5
7
mA
I
DD, SLEEP
Sleep Supply Current
SLEEP = V
IH
0.25
2
mA
I
q
Quiescent Current
V
IN
= 0 V
61
75
mA
THD + N Total Harmonic Distortion Plus
Noise
P
O
= 9W/Channel
0.04
%
IHF-IM
IHF Intermodulation Distortion
19kHz, 20kHz, 1:1 (IHF)
0.18
0.5
%
SNR Signal-to-Noise
Ratio
A-Weighted, P
OUT
= 1W, R
L
= 8
89
dB
CS
Channel Separation
30kHz Bandwidth
50
55
dB
PSRR
Power Supply Rejection Ratio
Vripple = 100mV.
60
80
dB
Power Efficiency
P
OUT
= 10W/Channel, R
L
= 8
88 %
V
OFFSET
Output Offset Voltage
No Load, MUTE = Logic Low
50
150
mV
V
OH
High-level output voltage
(FAULT & OVERLOAD)
3.5
V
V
OL
Low-level
output
voltage
(FAULT & OVERLOAD)
1
V
e
OUT
Output Noise Voltage
A-Weighted, input AC grounded
100
V
Note: Minimum and maximum limits are guaranteed but may not be 100% tested.
T E C H N I C A L I N F O R M A T I O N
Page 4
TA2024 Preliminary, Rev. 1.0
Pin Description
Pin
Function
Description
2, 3
DCAP2, DCAP1
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
4, 9
V5D, V5A
Digital 5VDC, Analog 5VDC
5, 8,
17
AGND1, AGND2,
AGND3
Analog Ground
6
REF
Internal reference voltage; approximately 1.0 VDC.
7
OVERLOADB
A logic low output indicates the input signal has overloaded the amplifier.
10, 14
VP1, VP2
Input stage output pins.
11, 15
IN1, IN2
Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with
approximately 2.4VDC bias.
12
MUTE
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
16
BIASCAP
Input stage bias voltage (approximately 2.4VDC).
18
SLEEP
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
19
FAULT
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
20, 35
PGND2, PGND1
Power Grounds (high current)
22 DGND
Digital
Ground
24, 27;
31, 28
OUTP2 & OUTM2;
OUTP1 & OUTM1
Bridged outputs
25, 26,
29, 30
VDD2, VDD2
VDD1, VDD1
Supply pins for high current H-bridges, nominally 12VDC.
13, 21,
23, 32,
34
NC
Not connected. Not bonded internally.
33 VDDA
Analog
12VDC
36
CPUMP
Charge pump output (nominally 10V above VDDA)
1
5VGEN
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
FAULT
PGND2
NC
NC
VDD2
OUTM2
OUTM1
VDD1
NC
VDDA
NC
PGND1
CPUMP
DCAP2
AGND3
BIASCAP
IN2
VP2
MUTE
IN1
VP1
V5A
AGND2
OVERLOADB
REF
AGND1
V5D
DCAP1
30
19
20
21
22
23
24
25
26
27
28
29
1
15
14
13
11
10
12
9
8
7
6
5
4
3
2
36-pin Power SOP Package
(Top View)
16
17
18
+5VGEN
36
31
32
33
34
35
OUTP1
VDD1
VDD2
OUTP2
DGND
NC
SLEEP
T E C H N I C A L I N F O R M A T I O N
TA2024 Preliminary, Rev. 1.0
Page 5
Application / Test Circuit
TA2024
R
L
4
or *8
MUTE
FAULT
OVERLOADB
(+12V)
C
I
2.2uF
VP1
VP2
IN1
IN2
OUTP1
OUTM1
OUTP2
OUTM2
VDDA
+5VGEN
BIASCAP
DCAP2
DCAP1
C
I
2.2uF
C
A
0.1uF
C
D
0.1uF
CPUMP
10
11
20
1
33
29
26
7
19
31
28
24
27
36
2
3
15
14
12
16
R
F
20K
18
R
Z
10
, 1/2W
R
Z
10
, 1/2W
C
Z
0.47uF
C
P
1uF
+
+
5V
SLEEP
5V
5V
+12V
0.1uF
REF
R
REF
8.25K
, 1%
6
1meg
All Diodes Motorola MBRS130T3
* Use C
o
= 0.22
F for 8 Ohm loads
VDD1
PGND1
VDD1
PGND1
VDD2
VDD2
PGND2
PGND2
Note: Analog and Digital/Power Grounds must
be connected locally at the TA2024
C
S
0.1uF
C
S
0.1uF
To Pin 1
4
5
V5D
8
AGND1
AGND2
V5A
22
C
S
0.1uF
DGND
VDD1
PGND2
35
PGND1
180uF, 16V
VDD2
VDD
+
+
+
Processing
&
Modulation
Processing
&
Modulation
*C
o
0.47uF
L
o
10uH, 2A
9
(Pin 8)
Analog Ground
Digital/Power Ground
(Pin 35)
(Pin 35)
(Pin 20)
(Pin 20)
To Pins 4,9
R
I
20K
(Pin 8)
R
F
20K
R
I
20K
AGND3
17
180uF, 16V
C
SW
C
SW
*C
o
0.47uF
L
o
10uH, 2A
R
L
4 or *8
L
o
10uH, 2A
L
o
10uH, 2A
*C
o
0.47uF
*C
o
0.47uF
C
Z
0.47uF
C
SW
0.1uF
C
SW
0.1uF
C
S
0.1uF
D
O
D
O
D
O
D
O
C
CM
0.1uF
C
CM
0.1uF
(Pin 35)
(Pin 20)
13
NC
21
23
25
30
32
34
VDD1
VDD2
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