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www.ubicom.com

UbicomTM and the Ubicom logo are trademarks of Ubicom, Inc.
I

CTM is a trademark of Philips Corporation

All other trademarks mentioned in this document are property of their respec-
tive companies.

March, 2002

SX20AC/SX28AC

Configurable Communications Controllers with EE/Flash Program
Memory, In-System Programming Capability and On-Chip Debug

1.0

PRODUCT OVERVIEW

1.1

Introduction

The Ubicom SX family of configurable communications
controllers are fabricated in an advanced CMOS process
technology. The advanced process, combined with a
RISC-based architecture, allows high-speed computa-
tion, flexible I/O control, and efficient data manipulation.
Throughput is enhanced by operating the device at fre-
quencies up to 75 MHz and by optimizing the instruction
set to include mostly single-cycle instructions. In addition,
the SX architecture is deterministic and totally reprogra-
mable. The unique combination of these characteristics

enables the device to implement hard real-time functions
as software modules (Virtual PeripheralTM) to replace tra-
ditional hardware functions.

On-chip functions include a general-purpose 8-bit timer
with prescaler, an analog comparator, a brown-out detec-
tor, a watchdog timer, a power-save mode with multi-
source wakeup capability, an internal R/C oscillator, user-
selectable clock modes, and high-current outputs.

Figure 1-1. Block Diagram

Interrupt

MIWU

Port B

Comp

Power-On

Reset

RESET

8-bit Watchdog

Timer (WDT)

8-bit Timer

RTCC

Port C

Port A

Internal Data Bus

In-System

Debugging

In-System

Programming

2k Words

EEPROM

System

Clock

Brown-Out

MIWU

MCLR

OSC

Driver

4MHz

Internal

RC OSC

Clock

Select

4 or

136 Bytes

SRAM

Address

Write Data

Read Data

Instruction

FSR

STATUS

MODE

OPTION

System Clock

OSC1 OSC2

Fetch

Address

ALU

RTCC

Analog

Interrupt Stack

3 Level

Decode

Executive

Write Back

IREAD

Stack

Instruction

Pipeline

Prescaler for RTCC

Prescaler for WDT

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SX20AC/SX28AC

Table of Contents

1.0

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1

The Virtual Peripheral Concept . . . . . . . . 4

1.3.2

The Communications Controller . . . . . . . . 4

1.4

Programming and Debugging Support . . . . . . . . . . 4

1.5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.0

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3

Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.0

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1

Reading and Writing the Ports . . . . . . . . . . . . . . . . . 7
3.1.1

Read-Modify-Write Considerations . . . . . 9

3.2

Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1

MODE Register . . . . . . . . . . . . . . . . . . . . 9

3.2.2

Port Configuration Registers . . . . . . . . . . 9

3.2.3

Port Configuration Upon Reset . . . . . . . 10

4.0

Special-Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1

PC Register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2

STATUS Register (03h) . . . . . . . . . . . . . . . . . . . . . 11

4.3

OPTION Register . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.0

Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . 13
5.1

FUSE Word (Read/Program at FFFh in main memory
map) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2

FUSEX Word (Read/Program via Programming
Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3

DEVICE Word (Hard-Wired Read-Only) . . . . . . . . 14

6.0

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1

Program Counter . . . . . . . . . . . . . . . . . . 15

6.1.2

Subroutine Stack . . . . . . . . . . . . . . . . . . 15

6.2

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.1

File Select Register (04h) . . . . . . . . . . . 15

7.0

Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1

Multi-Input Wakeup . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2

Port B MIWU/Interrupt Configuration . . . . . . . . . . . 18

8.0

Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.0

Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1

XT, LP or HS modes . . . . . . . . . . . . . . . . . . . . . . . 21

9.2

External RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.3

Internal RC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.0

Real Time Clock (RTCC)/Watchdog Timer . . . . . . . . . . . . .23
10.1

RTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

10.2

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .23

10.3

The Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

11.0

Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

12.0

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

13.0

Brown-Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

14.0

Register States Upon DiffeRent reset operations . . . . . . .29

15.0

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
15.1

Instruction Set Features . . . . . . . . . . . . . . . . . . . . .30

15.2

Instruction Execution . . . . . . . . . . . . . . . . . . . . . . .30

15.3

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . .30

15.4

RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . .31

15.5

The Bank Instruction . . . . . . . . . . . . . . . . . . . . . . .31

15.6

Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .31

15.7

Input/Output Operation . . . . . . . . . . . . . . . . . . . . . .31

15.8

Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . .31

15.9

Loop Counting and Data Pointing Testing . . . . . . .31

15.10

Branch and Loop Call Instructions . . . . . . . . . . . . .31
15.10.1

Jump Operation . . . . . . . . . . . . . . . . . . .31

15.10.2

Page Jump Operation . . . . . . . . . . . . . .32

15.10.3

Call Operation . . . . . . . . . . . . . . . . . . . .32

15.10.4

Page Call Operation . . . . . . . . . . . . . . . .32

15.11

Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . .32

15.12

Subroutine Operation . . . . . . . . . . . . . . . . . . . . . . .33
15.12.1

Push Operation . . . . . . . . . . . . . . . . . . .33

15.12.2

Pop Operation . . . . . . . . . . . . . . . . . . . .33

15.13

Comparison and Conditional Branch Instructions .34

15.14

Logical Instruction . . . . . . . . . . . . . . . . . . . . . . . . .34

15.15

Shift and Rotate Instructions . . . . . . . . . . . . . . . . .34

15.16

Complement and SWAP . . . . . . . . . . . . . . . . . . . .34

15.17

Key to Abbreviations and Symbols . . . . . . . . . . . . .34

16.0

Instruction Set Summary Table . . . . . . . . . . . . . . . . . . . . . .35
16.1

Equivalent Assembler Mnemonics . . . . . . . . . . . . .38

17.0

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .39
17.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .39

17.2

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .40

17.3

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .41

17.4

Comparator DC and AC Specifications . . . . . . . . .41

17.5

Typical Performance Characteristics. . . . . . . . . . . .42

18.0

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

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SX20AC/SX28AC

1.2

Key Features

50 MIPS Performance

· SX20AC/SX28AC: DC - 75 MHz

· SX20AC/SX28AC: 13.3 ns instruction cycle, 39.9 ns in-

ternal interrupt response

· 1 instruction per clock (branches 3)

EE/FLASH Program Memory and SRAM Data Memory

· Access time of < 13.3 ns provides single cycle access

· EE/Flash rated for > 10,000 rewrite cycles

· 2048 Words EE/Flash program memory

· 136x8 bits SRAM data memory

CPU Features

· Compact instruction set

· All instructions are single cycle except branch

· Eight-level push/pop hardware stack for subroutine

linkage

· Fast table lookup capability through run-time readable

code (IREAD instruction)

· Totally predictable program execution flow for hard

real-time applications

Fast and Deterministic Interrupt

· Jitter-free 3-cycle internal interrupt response

· Hardware context save/restore of key resources such

as PC, W, STATUS, and FSR within the 3-cycle inter-
rupt response time

· External wakeup/interrupt capability on Port B (8 pins)

Flexible I/O

· All pins individually programmable as I/O

· Inputs are TTL or CMOS level selectable

· All pins have selectable internal pull-ups

· Selectable Schmitt Trigger inputs on Ports B, and C

· All outputs capable of sourcing/sinking 30 mA

· Port A outputs have symmetrical drive

· Analog comparator support on Port B (RB0 OUT, RB1

IN-, RB2 IN+)

· Selectable I/O operation synchronous to the oscillator

clock

Hardware Peripheral Features

· One 8-bit Real Time Clock/Counter (RTCC) with pro-

gramable 8-bit prescaler

· Watchdog Timer (shares the RTCC prescaler)

· Analog comparator

· Brown-out detector

· Multi-Input Wakeup logic on 8 pins

· Internal RC oscillator with configurable rate from 31.25

kHz to 4 MHz

· Power-On-Reset

Packages

· 20-pin SSOP, 28-pin DIP/SSOP

Programming and Debugging Support

· On- chip in-system programming support with serial

and parallel interfaces

· In-system serial programming via oscillator pins

· On-chip in-System debugging support logic

· Real-time emulation, full program debug, and integrat-

ed development environment offered by third party tool
vendors

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SX20AC/SX28AC

1.3

Architecture

The SX devices use a modified Harvard architecture.
This architecture uses two separate memories with sepa-
rate address buses, one for the program and one for
data, while allowing transfer of data from program mem-
ory to SRAM. This ability allows accessing data tables
from program memory. The advantage of this architec-
ture is that instruction fetch and memory transfers can be
overlapped with a multi-stage pipeline, which means the
next instruction can be fetched from program memory
while the current instruction is being executed using data
from the data memory.

Ubicom has developed a revolutionary RISC-based
architecture and memory design techniques that is 20
times faster than conventional MCUs, deterministic, jitter
free, and totally reprogramable.

The SX family implements a four-stage pipeline (fetch,
decode, execute, and write back), which results in execu-
tion of one instruction per clock cycle. For example, at
the maximum operating frequency of 75 MHz, instruc-
tions are executed at the rate of one per 13.3ns clock
cycle.

1.3.1 The Virtual Peripheral Concept

Virtual Peripheral concept enables the "software system
on a chip" approach. Virtual Peripheral, a software mod-
ule that replaces a traditional hardware peripheral, takes
advantage of the Ubicom architecture's high performance
and deterministic nature to produce same results as the
hardware peripheral with much greater flexibility.

The speed and flexibility of the Ubicom architecture com-
plemented with the availability of the Virtual Peripheral
library, simultaneously address a wide range of engineer-
ing and product development concerns. They decrease
the product development cycle dramatically, shortening
time to production to as little as a few days.

Ubicom's time-saving Virtual Peripheral library gives the
system designers a choice of ready-made solutions, or a
head start on developing their own peripherals. So, with
Virtual Peripheral modules handling established func-
tions, design engineers can concentrate on adding value
to other areas of the application.

The concept of Virtual Peripheral combined with in-sys-
tem re-programmability provides a power development
platform ideal for the communications industry because
of the numerous and rapidly evolving standards and pro-
tocols.

Overall, the concept of Virtual Peripheral provides bene-
fits such as using a more simple device, reduced compo-
nent count, fast time to market, increased flexibility in
design, customization to your application, and ultimately
overall system cost reduction.

Some examples of Virtual Peripheral modules are:

· Communication interfaces such as I

CTM, MicrowireTM

(µ-Wire), SPI, IrDA Stack, UART, and Modem func-
tions

· Frequency generation and measurement

· PPM/PWM output

· Delta/Sigma ADC

· DTMF generation/detection

· PSK/FSK generation/detection

· FFT/DFT based algorithms

1.3.2 The Communications Controller

The combination of the Ubicom hardware architecture
and the Virtual Peripheral concept create a powerful, cre-
ative platform for the communications design communi-
ties: SX communications controller. Its high processing
power, recofigurability, cost-effectiveness, and overall
design freedom give the designer the power to build
products for the future with the confidence of knowing
that they can keep up with innovation in standards and
other areas.

1.4

Programming and Debugging Support

The SX devices are currently supported by third party
tool vendors. On-chip in-system debug capabilities have
been added, allowing tools to provide an integrated
development environment including editor, macro assem-
bler, debugger, and programmer. Un-obtrusive in-system
programming is provided through the OSC pins. There is
no need for a bon-out chip, so the user does not have to
worry about the potential variations in electrical charac-
teristics of a bond-out chip and the actual chip used in the
target applications. the user can test and revise the fully
debugged code in the actual SX, in the actual application,
and get to production much faster.

1.5

Applications

Emerging applications and advances in existing ones
require higher performance while maintaining low cost
and fast time-to-production.

The device provides solutions for many familiar applica-
tions such as process controllers, electronic appli-
ances/tools, security/monitoring systems, consumer
automotive, sound generation, motor control, and per-
sonal communication devices. In addition, the device is
suitable for applications that require DSP-like capabili-
ties, such as closed-loop servo control (digital filters), dig-
ital answering machines, voice notation, interactive toys,
and magnetic-stripe readers.

Furthermore, the growing Virtual Peripheral library fea-
tures new components, such as the Internet Protocol
stack, and communication interfaces, that allow design
engineers to embed Internet connectivity into all of their
products at extremely low cost and very little effort.

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SX20AC/SX28AC

2.0

CONNECTION DIAGRAMS

2.1

Pin Assignments

2.2

Pin Descriptions

SSOP

1
2
3
4
5
6
7
8

16
15

RC4
RC3

RB6
RB5

SX 28-PIN

OSC2
RC7
RC6
RC5

RA2
RA3
RB0
RB1
RB2
RB3
RB4

Vss

MCLR
OSC1

RC2
RC1
RC0
RB7

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

Vss

RTCC

RA0
RA1

1
2
3
4
5
6
7
8

16
15

RC4
RC3

RB6
RB5

SX 28-PIN

OSC2
RC7
RC6
RC5

n.c.

Vss

RA2
RA3
RB0
RB1
RB2
RB3
RB4

MCLR
OSC1

RC2
RC1
RC0
RB7

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

RTCC

RA0
RA1

n.c.

DIP

1
2
3
4
5
6
7
8

16
15

RB5
RB4

SX 20-PIN

OSC2

RTCC

RA0

RB0
RB1
RB2
RB3

MCLR

OSC1

RB7
RB6

9
10

14
13
12
11

20
19
18
17

RA2
RA3

Vss

RA1

Vss

SSOP

Name

Pin Type Input Levels

Description

RA0

I/O

TTL/CMOS

Bidirectional I/O Pin; symmetrical source / sink capability

RA1

I/O

TTL/CMOS

Bidirectional I/O Pin; symmetrical source / sink capability

RA2

I/O

TTL/CMOS

Bidirectional I/O Pin; symmetrical source / sink capability

RA3

I/O

TTL/CMOS

Bidirectional I/O Pin; symmetrical source / sink capability

RB0

I/O

TTL/CMOS/ST

Bidirectional I/O Pin; comparator output; MIWU/Interrupt input

RB1

I/O

TTL/CMOS/ST

Bidirectional I/O Pin; comparator negative input; MIWU/Interrupt input

RB2

I/O

TTL/CMOS/ST

Bidirectional I/O Pin; comparator positive input; MIWU/Interrupt input

RB3

I/O

TTL/CMOS/ST