UM61512A Series
64K X 8 BIT HIGH SPEED CMOS SRAM
1
Features
Single +5V power supply
Access times: 15/20/25ns (max.)
Current: Operating: 160mA (max.)
Standby: 10mA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 3V (min.)
Available in 32-pin SKINNY DIP, TSOP, SOP, SOJ
and both 300/400 mil packages
General Description
The UM61512A is a low operating current 524,288-bit
static random access memory organized as 65,536
words by 8 bits and operates on a single 5V power
supply. It is built using UMC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 3V.
Pin Configurations
SKINNY/SOJ/SOP
TSOP (forward type)
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
CE1
A10
OE
A9
A8
A13
WE
CE2
A15
VCC
A11
UM61512A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
UM61512AV
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
A11
17
A3
2
A9
18
A2
3
A8
19
A1
4
A13
20
A0
5
WE
21
I/O
1
6
CE2
22
I/O
2
7
A15
23
I/O
3
8
VCC
24
GND
9
NC
25
I/O
4
10
NC
26
I/O
5
11
A14
27
I/O
6
12
A12
28
I/O
7
13
A7
29
I/O
8
14
A6
30
CE1
15
A5
31
A10
16
A4
32
OE
UM61512A
2
Block Diagram
DECODER
512 X 2048
MEMORY ARRAY
INPUT
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
VCC
GND
A0
A13
A14
A15
I/O
1
I/O
8
CE2
CE1
OE
WE
Pin Descriptions SKINNY/SOJ/SOP
Pin No.
Symbol
Description
1, 2
NC
No Connection
3 - 12, 23,
25 - 28, 31
A0 - A15
Address Inputs
13 - 15, 17 - 21
I/O
1
- I/O
8
Data Input/Outputs
16
GND
Ground
22
CE1
Chip Enable
24
OE
Output Enable
29
WE
Write Enable
30
CE2
Chip Enable
32
VCC
Power Supply
Pin Description TSOP
Pin No.
Symbol
Description
1 - 4, 7,
11 - 20, 31
A0 - A15
Address Inputs
5
WE
Write Enable
6
CE2
Chip Enable
8
VCC
Power Supply
9, 10
NC
No Connection
21 - 23, 25 - 29
I/O
1
- I/O
8
Data Input/Outputs
24
GND
Ground
30
CE1
Chip Enable
32
OE
Output Enable
UM61512A
3
Recommended DC Operating Conditions
(T
A
= 0
C to + 70
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
4.75
5.0
5.25
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
3.5
VCC + 0.3
V
V
IL
Input Low Voltage
-0.3
0
+0.8
V
C
L
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature, Topr . . . . . . . . . . 0
C to +70
C
Storage Temperature, Tstg . . . . . . . . . . -55
C to +125
C
Temperature Under Bias, Tbias . . . . . . . -10
C to +85
C
Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . 1.0W
Soldering Temp. & Time . . . . . . . . . . . . . 260
C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics
(T
A
= 0
C to + 70
C, VCC = 5V
5%, GND = 0V)
Symbol
Parameter
UM61512A-15/20/25
Unit
Conditions
Min.
Max.
I
LI
Input Leakage Current
-
2
A
V
IN
= GND to VCC
I
LO
Output Leakage Current
-
2
A
CE1 = V
IH
or CE2 = V
IL
or
OE = V
IH
or WE = V
IL
V
I/O
= GND to VCC
I
CC1
(1)
Dynamic Operating Current
-
160
mA
CE1 = V
IL
, CE2 = V
IH
I
I/O
= 0 mA
I
SB
-
30
mA
CE1 = V
IH
or CE2 = V
IL
I
SB1
Standby Power
Supply Current
-
20
mA
CE1
VCC - 0.2V,
CE2
VCC - 0.2V,
V
IN
0.2V or V
IN
VCC - 0.2V
I
SB2
-
20
mA
CE1
0.2V, CE2
0.2V
V
IN
0.2V or V
IN
VCC - 0.2V
V
OL
Output Low Voltage
-
0.4
V
I
OL
= 8 mA
V
OH
Output High Voltage
2.4
-
V
I
OH
= -4 mA
Note: 1. I
CC1
is dependent on output loading, cycle rates, and Read/Write patterns.
UM61512A
4
Truth Table
Mode
CE1
CE2
OE
WE
I/O Operation
Supply Current
Standby
H
X
X
X
High Z
I
SB
, I
SB1
X
L
X
X
High Z
I
SB
, I
SB2
Output Disable
L
H
H
H
High Z
I
CC1
Read
L
H
L
H
D
OUT
I
CC1
Write
L
H
X
L
D
IN
I
CC1
Note: X = H or L
Capacitance
(T
A
= 25
C, f = 1.0 MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
8
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
10
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0
C to +70
C, VCC = 5V
10%)
Symbol
Parameter
UM61512A-15
UM61512A-20
UM61512A-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
15
-
20
-
25
-
ns
t
AA
Address Access Time
-
15
-
20
-
25
ns
t
ACE1
Chip Enable Access Time
CE1
-
15
-
20
-
25
ns
t
ACE2
CE2
-
15
-
20
-
25
ns
t
OE
Output Enable to Output Valid
-
7
-
9
-
12
ns
t
CLZ1
Chip Enable to Output in Low Z
CE1
5
-
5
-
5
-
ns
t
CLZ2
CE2
5
-
5
*
5
-
ns
t
OLZ
Output Enable to Output in Low Z
2
-
2
-
2
-
ns
t
CHZ1
Chip Disable to Output in High Z
CE1
-
10
-
10
-
15
ns
t
CHZ2
CE2
-
10
-
10
-
15
ns
t
OHZ
Output Disable to Output in High Z
2
9
2
9
2
10
ns
t
OH
Output Hold from Address Change
3
-
5
-
5
-
ns
UM61512A
5
AC Characteristics (continued)
Symbol
Parameter
UM61512A-15
UM61512A-20
UM61512A-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle
t
WC
Write Cycle Time
15
20
20
25
25
-
ns
t
CW
Chip Enable to End of Write
12
15
15
20
20
-
ns
t
AS
Address Setup Time of Write
0
0
0
0
0
-
ns
t
AW
Address Valid to End of Write
12
15
15
20
20
-
ns
t
WP
Write Pulse Width
9
-
11
-
-
-
ns
t
WR
Write Recovery Time
0
-
0
-
-
-
ns
t
WHZ
Write to Output in High Z
0
8
0
13
13
13
ns
t
DW
Data to Write Time Overlap
7
-
7
-
-
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
-
-
ns
t
OW
Output Active from End of Write
5
-
5
-
-
-
ns
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1
(1,2,4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
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