Vishay Siliconix
SPICE Device Model Si4910DY
N-Channel 40-V (D-S) MOSFET
CHARACTERISTICS
N-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
gd
model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
1
www.vishay.com
Document Number: 74168
S-60411
Rev. A, 20-Mar-06
Vishay Siliconix
SPICE Device Model Si4910DY
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Condition
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
A
1.2
V
On-State Drain Current
a
I
D(on)
V
DS
5 V, V
GS
= 10 V
224 A
V
GS
= 10 V, I
D
= 6 A
0.021
0.022
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 4.5 V, I
D
= 4.8 A
0.026
0.026
Forward Transconductance
a
g
fs
V
DS
= 15 V, I
D
= 6 A
17
20
S
Forward Voltage
a
V
SD
I
S
= 1.5 A
0.83
0.73
V
Dynamic
b
Input Capacitance
C
iss
1085
855
Output Capacitance
C
oss
111
105
Reverse Transfer Capacitance
C
rss
V
DS
= 20 V, V
GS
= 0 V, f = 1 MHz
58 65
pF
V
DS
= 20 V, V
GS
= 10 V, I
D
= 5 A
17
21
Total Gate Charge
Q
g
9
9.6
Gate-Source Charge
Q
gs
2.3
2.3
Gate-Drain Charge
Q
gd
V
DS
= 20 V, V
GS
= 4.5 V, I
D
= 5 A
3.2
3.2
nC
Notes
a. Pulse test; pulse width
300 s, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
2
www.vishay.com
Document Number: 74168
S-60411
Rev. A, 20-Mar-06
Vishay Siliconix
SPICE Device Model Si4910DY
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
3
www.vishay.com
Document Number: 74168
S-60411
Rev. A, 20-Mar-06
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