ChipFind - документация

Электронный компонент: VT73LVP10M

Скачать:  PDF   ZIP
2002-01-15 Page
1
MDST-0014-07
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Applications
= PECL clock source
General Description
The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW
enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts
an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail.
When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state.

Features
= 700ps typical propagation delay
= Differential LVPECL outputs
= Flow-through pinout
= -40
o
C to +85
o
C operating temperature range
= 5V - tolerant inputs
= ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
= Available as die, 8-pin SOIC or 8 pin
MSOP package





Preliminary
VT73LVP10
TTL to Differential LVPECL Translator
with Enable
Figure 1. Functional Block Diagram & Pin Assignment
/EN
QN
Q
NC
4
3
2
1
6
7
8
TTL/
CMOS
LVPECL
5 GND
NC
D
V
DD
8 pin SOIC/ MSOP
100k
VT73LVP10
Preliminary
2002-01-15 Page
2
MDST-0014-06
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Table 1. Pin Description
Name Description
Type
Pin
#
/EN
CMOS/TTL Active LOW enable input, with pull-down resistor
I
4*
Q
PECL data output
O
2
QN
PECL complementary data output
O
3
V
DD
Connect to 3.3V
P
8
D
CMOS/TTL data input
I
7
GND
Connect to ground
P
5

Legend: I = Input
O = Output
P = Power supply connection
* = Internal 100k
pull-down resistor
Table 2. Absolute Maximum Ratings
Symbol Parameter
Conditions
Min
Typ
Max
Units
V
DD
Supply voltage
Referenced to GND
6
V
V
IN
Input voltage
Referenced to GND
-0.5
6
V
I
OUT
Output current in LOW state
50
mA
T
STG
Storage
temperature
-65 150
o
C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Table 3. Operating Conditions
Symbol Parameter
Conditions
Min Typ Max
Units
V
DD
Power Supply Voltage
3.0
3.6
V
T
A
Ambient
Temperature
-40 85
o
C
V
IH
Input HIGH Voltage
D, /EN inputs
2.0
V
V
IL
Input LOW Voltage
D, /EN inputs
0.8
V
t
Rin
Input slew rate
10% to 90% (L
H)
1
V/ns
t
Fin
Input slew rate
90% to 10% (H
L)
1
V/ns

VT73LVP10
Preliminary
2002-01-15 Page
3
MDST-0014-06
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Table 4. DC Characteristics
T
A
= -40
o
C to +85
o
C, V
DD
= 3.0V to 3.6V unless otherwise stated below.
Symbol Parameter
Conditions Min
Typ
Max
Units
D input
1
I
IH
Input HIGH Current
V
IN
= 2.7V
/EN input
50
A
D input
1
I
IL
Input LOW Current
V
IN
= 0.5V
/EN input
20
A
V
IK
Input Clamp Diode Voltage
I
IN
= -18mA
-1.2
V
-40
o
C 2275
2375
2475
mV
25
o
C 2200
2300
2400
mV
V
OH
Output HIGH Voltage
(1, 2)
85
o
C
V
DD
= 3.3V
2125 2225 2325 mV
-40
o
C 1350
1450
1550
mV
25
o
C 1400
1500
1600
mV
V
OL
Output LOW Voltage
(1, 2)
85
o
C
V
DD
= 3.3V
1450 1550 1650 mV
I
DD
Power Supply Current
(2)
33 mA
Notes:
1.The VT73LVP10 is designed to meet these specifications after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board.
2. Q and QN outputs are loaded with 50 ohms to V
DD
-2 volts.


Table 5. AC Characteristics
T
A
= -40
o
C to +85
o
C, V
DD
= 3.0V to 3.6V
Symbol Parameter
Conditions Min
Typ
Max
Units
t
PLH
Propagation
Delay
(1)
0.7
1.2
ns
t
PHL
Propagation
Delay
(1)
0.7
1.2
ns
t
PLH
Propagation Delay
/EN to Q, QN
1.5
2.5
ns
t
PHL
Propagation Delay
/EN to Q, QN
1.5
2.5
ns
t
r
/t
f
Output Rise/Fall time
20%-80%
0.25
0.35
0.7
ns
f
MAX
Maximum Input Frequency
LVTTL or LVCMOS input
170
MHz
f
MAX
Maximum Input Frequency
(2)
750mV peak-to-peak sine
wave (AC coupled)
400 MHz
Notes:
1. Q and QN outputs are loaded with 50 ohms to V
DD
-2 volts.
2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source.



Ordering Information
Part Number
Marking
Shipping/Packaging
No. of Pins
Package
Temperature
VT73LVP10S1 VT73LVP10S1
Tubes
8
SOIC -40
C to +85
C
VT73LVP10S1X VT73LVP10S1 Tape & Reel
8
SOIC
-40
C to +85
C
VT73LVP10M VT73LVP10M
Tubes
8
MSOP -40
C to +85
C
VT73LVP10MX
VT73LVP10M
Tape & Reel
8
MSOP
-40
C to +85
C
VT73LVP10/D
Dice in waffle-pak
-40
C to +85
C
VT73LVP10/DW
Dice in wafer form
-40
C to +85
C