1998 Copyright Cyrix Corporation. All rights reserved.
Printed in the United States of America
Trademark Acknowledgments:
Cyrix is a registered trademark of Cyrix Corporation.
6x86, 6x86MX, M II are trademarks of Cyrix Corporation. MMX is a trademark of Intel Corporation.
All other brand or product names are trademarks of their respective companies.
Order Number: 94329-00
Cyrix Corporation
2703 North Central Expressway
Richardson, Texas 75080-2010
United States of America
Cyrix Corporation (Cyrix) reserves the right to make changes in the devices or specifications described herein without notice.
Before design-in or order placement, customers are advised to verify that the information is current on which orders or design
activities are based. Cyrix warrants its products to conform to current specifications in accordance with Cyrix' standard warranty.
Testing is performed to the extent necessary as determined by Cyrix to support this warranty. Unless explicitly specified by
customer order requirements, and agreed to in writing by Cyrix, not all device characteristics are necessarily tested. Cyrix assumes
no liability, unless specifically agreed to in writing, for customers' product design or infringement of patents or copyrights of third
parties arising from the use of Cyrix devices. No license, either express or implied, to Cyrix patents, copyrights, or other intellec-
tual property rights pertaining to any machine or combination of Cyrix devices is hereby granted. Cyrix products are not intended
for use in any medical, life saving, or life sustaining system. Information in this document is subject to change without notice.
Introduction
Advanci ng the S tandar ds
PRELIMINARY
The Cyrix M II
TM
processor is an enhanced processor
with high speed performance. This processor has a
64K unified write-back cache, a two- level TLB and a
512-entry BTB. The M II CPU contains a scratchpad
RAM feature, supports performance monitoring, and
allows caching of both SMI code and SMI data. It
delivers high 16- and 32-bit performance while
running Windows 95, Windows NT, OS/2, DOS,
UNIX, and other operating systems.
The M II processor achieves top performance through
the use of two optimized superpipelined integer
units, an on-chip floating point unit, and a 64 KByte
unified write-back cache. The superpipelined archi-
tecture reduces timing constraints and increase
frequency scalability. Advanced architectural
techniques include register renaming, out-of-order
completion, data dependency removal, branch
prediction and speculative execution.
Enhanced Sixth-Generation
Architecture
- M II-300 and higher
- 64K 4-Way Unified Write-Back Cache
- 2 Level TLB (16 Entry L1, 384 Entry L2)
- Branch Prediction with a 512-entry BTB
- Enhanced Memory Management Unit
- Scratchpad RAM in Unified Cache
- Optimized for both 16- and 32-Bit Code
- High Performance 80-Bit FPU
X86 Instruction Set Includes
MMX
TM
Instructions
- Compatible with MMX
TM
Technology
- Runs Windows
95, Windows 3.x, Windows NT,
DOS, UNIX
, OS/2
, Solaris
, and others
Other Features
- Socket 7 Pinout Compatible
- 2.9 V Core, 3.3 V I/O
- Flexible Core/Bus Clock Ratios (2x, 2.5x, 3x, 3.5x)
- Leverages Existing Socket Infrastructure
April 1998
Order Number: 94xxx-xx
April 13, 1998 10:38 am
c:\ !!!dev~1\ m2\!m2_0-1.f m
Rev 0.8
Rev 0.7 For addendum: t emp 70, 2.2->2.8 page 4-1
Rev 0.6 Added and subtracted bullet s
Rev 0.5 Removed expanded MMX Inst ructions
Rev 0.4 Reworded
Rev 0.3: Cleaned up block diagram
Rev 0.2: Added new block diagram and rewrote center paragraphs
Bus
Interface
Cont rol
D63-D0
A31-A3
64
1747800
BE7#-BE0#
C LK
Bus Interface
Unit
C ache Unit
CPU C ore
64- KByte Unified Cac he
Data
Address
Instruction Address
32
128
Instruction Data
X D ata
Y Data
32
32
32
32
32
64
X Linear
Address
Y Linear
Addr ess
256-Byte Instruction
Line Cache
X Physical
Address
Y Physical
Address
32
FPU
Data
64
Direct- Mapped
16-Entry
Level 1
TLB
6-Way
384-Entry
Level 2
TLB
Super pipelined
Integer Unit
512-Entry
BT B
FPU with
MMX
Extension
Memor y
Management Unit
32
MII
TM
PROCESSOR
Enhanced High Performance CPU
TABLE OF CONTENTS
v
Advanci ng the S tandar ds
1.
ARCHITECTURE OVERVIEW
1.1
Major Differences Between the M II and 6x86 Processors . . . . . . . . . . . . . 1-2
1.2
Major Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
Integer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4
Cache Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.5
Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.6
Floating Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.7
Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
2.
PROGRAMMING INTERFACE
2.1
Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4
System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.5
Model Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.6
Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.7
Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.8
Performance Monitoring Counters 1 and 2 . . . . . . . . . . . . . . . . . . . . 2-39
2.9
Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2.10
Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.11
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.12
Memory Addressing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
2.13
Memory Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
2.14
Interrupt and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
2.15
System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
2.16
Shutdown and Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
2.17
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
2.18
Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2.19
Floating Point Unit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2.20
MMX Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
3.
BUS INTERFACE
3.1
Signal Description Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3
Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
4.
ELECTRICAL SPECIFICATIONS
4.1
Electrical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.4
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.5
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
5.
MECHANICAL SPECIFICATIONS
5.1
296-Pin SPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
6.
INSTRUCTION SET
6.1
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2
General Instruction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3
CPUID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.4
Instruction Set Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.5
FPU Instruction Clock Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.6
M II Processor MMX Instruction Clock Counts . . . . . . . . . . . . . . . . . . 6-37
Appendix, Index and Distributors
MII
TM
PROCESSOR
Enhanced High Performance CPU
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