VIA Technologies, Inc.
Preliminary VT6304
2
P
RELIMINARY
R
ELEASE
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1998, Via Technologies Incorporated. Printed in Taiwan. A
LL
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IGHTS
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ESERVED
.
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VIA Technologies, Inc.
Preliminary VT6304
3
VT6304 IEEE 1394
A
F
OUR
P
ORT
C
ABLE
T
RANSCEIVER
/A
RBITER
F
EATURES
n
Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a
Supplement 2.0.
n
Full P1394a Supplement Support includes:
n
Arbitrated short reset,
n
Connection Debounce,
n
Multispeed Concatenation,
n
Ack Accelerated Arbitration,
n
Fly-By Concatenation,
n
Programmable Port Disable, Suspend, Resume,
n
PHY IDs Do Not Increment Past 63
n
Provides Four 1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbit/s)
n
Single 3.3 V power supply
n
Logic Performs Bus Initialization and Arbitration Functions
n
Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding
n
Incoming Data Resynchronized to Local Clock.
n
Data Interface to Link-Layer Controller Provided Through 2/4/8 Parallel Lines at 49.152 MHz
n
24.576 MHZ Crystal Oscillator and PLL Provide TX/RX Data at 100/200/400 Mbps and Link-Layer
Controller Clock at 49.152 MHZ.
n
Cable Power Presence Monitoring.
n
Programable Node Power Class Information for System Power Management
n
Embedded Bus Holder Isolation to Link Layer Controller Interface
n
Optional On-chip Resistors to Reduce Component Counts for Electrical Isolation to Link Layer
Controller Interface
n
Fully Compliant P1394a 2.0 PHY Map
n
Separate TPBIAS for Each Port
n
Fully Interoperable with IEEE Std1394-1995 Devices
n
Cable Ports Monitor Line Conditions for Active Connection to Remote Node
n
Low Power Design for Battery-Powered Applications includes: User Controlled Power-Down via PD,
Automatic Device Power-Down during All Ports Suspended and Link Interface Disabled, Link
Interface Power-Down via Inactive LPS, Automatic Inactive Ports Powered-Down, and Automatic
Inactive Logic Power-Down
n
Self Power Up Reset and Pinless PLL to Reduce Component Counts on System
n
Low Cost 100-Pin PQFP package
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