VT82C42
K
EYBOARD
C
ONTROLLER
Preliminary Release
DATE : November 22, 1995
VIA TECHNOLOGIES, INC.
P
RELIMINARY
D
OCUMENT
R
ELEASE
The material in this document supersedes all previous documentation issued for any of the products
included herein. Please contact VIA Technologies for the latest documentation.
Copyright Notice:
Copyright
1995, Via Technologies Incorporated. Printed in Taiwan. A
LL
R
IGHTS
R
ESERVED
.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or
translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical,
chemical, manual or otherwise without the prior written permission of Via Technologies Incorporated.
The VT82C42 may only be used to identify products of VIA Technologies.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA
Technologies makes no warranties, implied or otherwise, in regard to this document and to the products
described in this document. The information provided by this document is believed to be accurate and
reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for
any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or
misuse of the information in this document and for any patent infringements that may arise from the use of
this document. The information and product specifications within this document are subject to change at
any time, without notice and without obligation to notify any person of such change.
Offices:
5020 Brandin Court
8th Floor, No. 533
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94538
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Taipei, Taiwan ROC
Tel:
(510) 683-3300
Tel:
(886-2) 218-5452
Fax:
(510) 683-3301
Fax:
(886-2) 218-5453
VIA Technologies, Inc.
VT82C42
-1-
VT82C42 Keyboard Controller
Date : November 22, 1995
1. General Overview:
The VT82C42 is a compatible direct replacement for the Intel 80C42 BIOS version of the Keyboard
Controller. The VT82C42 is fully implemented by hardware logic so that it has a very fast response capability
for any command issued by the host. In addition to keyboard support, the VT82C42 also offers PS/2 mouse
support. The VT82C42 also offers the Mouse Lock
TM
function (patent pending), a feature exclusively
designed by VIA technologies, which locks the mouse when the keylock function is initiated.
2. Features:
Fully hardware implemented, 0.8
m CMOS Technology.
Very high speed response of A20 GATE & reset.
Support PS2 style mouse.
Compatible with all major BIOS, including AWARD, PHOENIX and AMI.
40 pin PDIP and 44 pin PLCC packages.
3. Function Description:
The internal timer counting is based on an 8Mhz clock input from X1, X2 ( or X2, with X1 connected to
ground). After the deassertion of RESET#, the VT82C42 will drive high at pin P23 and pin P27. After 6
s (6
x 8 clocks) of driving, the VT82C42 will check on pins T1 & P10; if both pins are low, then the VT82C42
will switch to PS/2 mode. Otherwise, the VT82C42 will remain in AT mode.
If the VT82C42 is in AT mode after the self test, then it will drive P24 and P25 low with all other ports high.
If the VT82C42 is in PS/2 mode, then it will drive P24, P25, P22, and P27 low with all other ports high. The
VT82C42 will not change its driving value until it receives the command "AA" from the host. When receiving
the command "AA" from the host, the VT82C42 will prepare a "55" in its output buffer and drive P24
(reflecting the internal OBF flag) high within 6 clocks. This response time is the typical active time for
internal IBF flag. After this initialization procedure, the VT82C42 will drive P26 low (AT mode) or drive P26
and P23 low (PS/2 mode) in order for the keyboard and mouse interface to receive data from keyboard or
mouse.
When the keyboard or mouse toggles the interface (KBCLK, KBDATA, MSCLK,MSDATA), the controller
receives data from the serial interface and stores the received data into its internal output buffer. If the
received data is from the keyboard, a scan code translation is executed before the data is sent to the output
buffer. The VT82C42 also raises P24 or P25 to indicate a output buffer full. The host is signaled to issue a
read command to the data port to read the received data out. When the VT82C42 receives data in the normal
mode (pin 25 on DIP40 or pin 28 on PLCC44 parts connected to VCC) and the status of P17 is low, then the
controller will not raise the P24, nor activate its internal OBF flag. It looks like the controller will consume the
income data itself. And if the data is from the mouse, the controller will still raise P25 to indicate that data is
coming from mouse. However, if the VT82C42 is in Mouse Lock
TM
mode (pin 25 on DIP40 or pin 28 on
PLCC44 parts connected to GND), the data from either keyboard or mouse will be prohibited from sending to
the host.
VIA Technologies, Inc.
VT82C42
-2-
The host can program the output port (P20-P23 in AT mode, or P20-P21 in PS/2 mode) or in-out port (P10-
P15 in AT mode, or P12-P15 in PS/2 mode) by issuing a command to the command register on the VT82C42.
The controller will then quickly execute the specified command. Note that P16-P17 is implemented as an
input port only. The host can also transmit data to the keyboard and mouse by issuing a command to the data
register. The data coming to the data register (with A0 = 0, CS# = 0, RD# = 1, and WR# = 0) will be sent to
the keyboard via the keyboard serial interfaces. The data sent to the mouse will be completed by 1) issuing a
D4 command to the command register, 2) then writing the following data byte to the data register (to be sent to
the mouse via mouse serial interface). In either case, the VT82C42 will wait for an acknowledgement from the
keyboard or mouse to complete a transmission. At the same time as the completion of the transmission, the
VT82C42 will raise P24 or P25 (when sending data to mouse) to signal the host of a completion of
transmission. When the controller receives or transmits, the controller does a parity and time-out check. If any
error occurs in the interface or inside the external devices (keyboard or mouse), the controller will reflect that
error in the following status register.
command
decoder
+
scan
mapping
data input buffer
command register/
data register
data output buffer
status register
arbitration &
central control
unit
timer
X1, X2
A0
CS
D[7:0]
receiving unit
transmitting unit
de
bo
u
n
c
i
n
g
clocking
(8 Mhz)
In/Out
port buffer
KBCK
KBDT
MSCK
MSDT
P[17:10]
P[27:20]
RESET
IOR
IOW
mode
selector
T1
T0
Fig 1. Block Diagram for VT82C42
VIA Technologies, Inc.
VT82C42
-3-
4. Register
Table 1. Status register: read only (with A0 = 1, CS# = 0, RD# = 0, WR# = 1)
Bit0 : OBF
1 means output buffer is full, 0 means output buffer is empty.
Bit1 : IBF
1 means input buffer is full, 0 means input buffer is empty.
Bit2 : system flag
0 after power on
Bit3 : command/Data
1 means last write is command write. 0 means last write is data write.
Bit4 : keylock status
To represent the inhibition of keyboard. 0 means keyboard is inhibited. 1
means keyboard is not inhibited.
Bit5 : transmit time-
out/mouse OBF
Act as transmit time-out on AT mode. 1 means error happens. Act as Mouse
OBF on PS2 mode. 1 means mouse output buffer full.
Bit6 : receive time-
out/general time-out
Act as receive time-out on AT mode. 1 means error happens. Act as general
(receive/transmit) time-out on PS2 mode.
Bit7 : parity error
1 means even parity has occurred in the last transmit/receive.
Table 2. Command register: read/write (use command 20h/60h)
Bit0 : OBF enable
1 means controller will generate high (interrupt) on P24 when output buffer
has been written.
Bit1 : mouse OBF enable
1 means controller will generate high (interrupt) on P25 when mouse data
comes in output buffer.
Bit2 : system flag
Connect to the status register Bit2.
Bit3 : inhibit override
Write a '1' to this Bit will disable the keyboard inhibit function.
Bit4 : prohibit enabling of
keyboard interface
Write a '1' to this Bit will disable keyboard interface
Bit5 : IBM PC keyboard
type protocol/disable
mouse interface
On AT mode, 0 means that the controller will do a IBM keyboard like
checking on receiving. On PS2 mode, a '1' disable the mouse interface
Bit6 : PC compatible mode
Default is 1, means the scan code translation is on.
Bit7 : reserved.
Table 3. Command List: (with A0 = 1, CS# = 0, RD# = 1, WR# = 0)
20h : read command byte
register.
After command execution, OBF = 1 means data is ready on the output
buffer.
60h : write command byte
register.
Next byte write to Data port will be written to command byte register.
9xh : write low nibble to
(Port13-Port10).
A1h : controller's version
number.
After command execution, OBF = 1 means data is ready on the output
buffer.
A4h : check password
command
Always return 'F1' on output buffer.
A7h : disable mouse
interface
After the command execution, Command byte register bit5 = 1 and P23 = 1
on PS2 mode. No effect on AT mode.
A8h : enable mouse
interface
After the command execution, Command byte register bit5 = 0 and P23 = 0
on PS2 mode. No effect on AT mode.
A9h : mouse interface test.
Return 00h if the interface is O.K..
AAh : controller's self test
Return 55h if the controller is O.K..
ABh : keyboard interface
test.
Return 00h if the interface is O.K..
ADh : disable keyboard
interface.
AEh : enable keyboard
interface.
AFh : return version
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