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Электронный компонент: VT82C580VP

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VT82C580VP
A
POLLO
VP
Green Pentium/P54C/M1/K5
PCI/ISA System
with Unified Memory Architecture,
Universal Serial Bus and
Master Mode PCI-IDE Controller
DATE : February, 1996
VIA TECHNOLOGIES, INC.
Copyright Notice:
Copyright
1995, 1996 Via Technologies Incorporated. Printed in Taiwan. A
LL
R
IGHTS
R
ESERVED
.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval
system, or translated into any language, in any form or by any means, electronic, mechanical,
magnetic, optical, chemical, manual or otherwise without the prior written permission of Via
Technologies Incorporated.
The VT82C580VP, VT82C585VP, VT82C586 and VT82C587VP may only be used to identify
products of VIA Technologies.
PS/2
TM
is a registered trademark of International Business Machines Corp.
Pentium
TM
, and P54C
TM
are registered trademarks of Intel Corp.
M1
TM
is a registered trademark of Cyrix Corp.
K86
TM
(K5) is a registered trademark of Advanced Micro Devices Corp.
Windows 95
TM
and Plug and Play
TM
are registered trademarks of Microsoft Corp.
PCI
TM
is a registered trademark of the PCI Special Interest Group.
Cache
TM
is a registered trademark of Mosys Inc.
All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies.
VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to
the products described in this document. The information provided by this document is believed
to be accurate and reliable to the publication date of this document. However, VIA Technologies
assumes no responsibility for any errors in this document. Furthermore, VIA Technologies
assumes no responsibility for the use or misuse of the information in this document and for any
patent infringements that may arise from the use of this document. The information and product
specifications within this document are subject to change at any time, without notice and without
obligation to notify any person of such change.
Offices:
5020 Brandin Court
8th Floor, No. 533
Fremont, CA
94538
Chung-Cheng Rd., Hsin-Tien
USA
Taipei, Taiwan ROC
Tel:
(510) 683-3300
Tel:
(886-2) 218-5452
Fax:
(510) 683-3301
Fax:
(886-2) 218-5453
VIA Technologies, Inc.
VT82C580VP
-i-
R
EVISION
H
ISTORY
Document
Release
Revision
Date
Revision 1.0
2/15/96
Preliminary Release
10/25/95
VIA Technologies, Inc.
VT82C580VP
-ii-
Table of Contents
Features............................................................................................................... 1
Overview.............................................................................................................. 4
Configuration Register of VT82C580VP............................................................ 7
VT82C585VP (Host -PCI)
.............................................................................. 7
VT82C586 (PCI-ISA/IDE/USB)
...................................................................... 16
AC Timing Characteristics ............................................................................... 33
VT82C580VP Pin Description .......................................................................... 51
Electrical Characteristics................................................................................. 67
VT82C580VP Packages .................................................................................... 68
Appendix A: Schematics
Appendix B: Operating Guide of VT5063B
Appendix C: Performance of VT82C580VP
VIA Technologies, Inc.
VT82C580VP
-1-
VIA VT82C580VP A
POLLO
-VP
P
ENTIUM
/P54C PCI/ISA
G
REEN
PC
S
YSTEMS
WITH
U
NIFIED MEMORY ARCHITECTURE
,
U
NIVERSAL
S
ERIAL
B
US AND
M
ASTER
M
ODE
PCI-IDE C
ONTROLLER
F
EATURES
PCI/ISA Green PC Ready
High Integration
-
VT82C585VP system controller
-
VT82C586 PCI to ISA bridge
-
Two instances of the VT82C587VP data buffers
-
Six TTLs for a complete main board implementation
Flexible CPU Interface
-
64-bit P54C
TM
, K5
TM
and M1
TM
CPU interface
-
CPU external bus speed up to 66Mhz (internal 200Mhz and above)
-
Supports CPU internal write-back cache
-
Concurrent CPU/cache and PCI/DRAM operation
-
System management interrupt, memory remap and STPCLK mechanism
-
Cyril M1 linear burst support
-
CPU NA#/Address pipeline capability
Advanced Cache Controller
-
Direct map write back or write through secondary cache
-
Burst Synchronous (Pipelined or non-pipelined), asynchronous SRAM, and Cache Module support
-
Eight-pin CWE# and GWE# control options
-
Flexible cache size: 0K/256K/512K/1M/2MB
-
32 byte line size to match the primary cache
-
Integrated 10-bit tag comparator
-
3-1-1-1 read/write timing for Burst Synchronous SRAM access at 66Mhz
-
3-1-1-1-1-1-1-1 back to back read timing for Burst Synchronous SRAM access at 66Mhz
-
Sustained 3 cycle write access for Burst Synchronous SRAM access or CPU to DRAM and PCI bus
post write buffers at 66Mhz
-
3-2-2-2 (read) and 4-2-2-2 (write) timing for interleaved asynchronous SRAM access at 66Mhz
-
Data streaming for simultaneous primary and secondary cache line fill
-
System and video BIOS cacheable and write-protect
-
Programmable cacheable region and cache timing
-
Optional combined tag and alter bit SRAM for write-back scheme
Fast DRAM Controller
-
Concurrent DRAM writeback
-
Four Cache lines (16 quadwords) of CPU/cache to DRAM write buffers
-
Fast Page Mode/EDO/Burst EDO/Synchronous-DRAM support in a mixed combination
-
Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs