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VT82C586B

Revision 1.0 May 13, 1997

-i-

Revision History

EVISION

ISTORY

Document Release

Date

Revision

Initials

Revision 0.1

10/13/96

Initial release for 586A

Revision 0.5

12/23/96

reprinted

1/8/97

to fix

Acrobat

PDF file

size

problem

Update to reflect 586B:
· Updated pin definitions:

Pins 18,31,33,58,60,131,133 (removed EXTSMI2-7 & DACEN)
Pins 77-78,80-83,85-86 (added GPI8-15 and GPO8-15)
Pins 94,87-88,92,136 (changed to GPIO0-4 and added alternate functions)
Pins 90,106,137 (added MIRQ0, MIRQ1, and MIRQ2 functions)
Pins 91,93,103,107 (changed to PWRBTN#, RI#, VDD-5VSB, PWRON)
Pins 113-114,116-119,121-122 (added GPI, GPO, and EXTSMI functions)
Fixed doc error DACK0-7 pin names changed to active low (DACK0-7#)
Removed options: IRQ12 (pin 137), strap (pin 48), RTCAS (pin 94)

· Updated register definitions

Removed VIA-specific port A8/A9 registers
Updated function 0 Rx5-4[3], Rx7-6[13], Rx41[0-4,6-7], Rx42[4-7], Rx44,

Rx46[2-4], Rx47[3], Rx48[3], Rx4A[4-6], Removed Rx50 (MDRQ)

Rx55[7-4] change PIRQD# to MIRQ1, Rx56 swap A/B, Rx57 swap C/D
Added 58-5B for PnP, XD, KBC/RTC config; added 60-6F for DDMA ctrl
Removed power mgmt regs 80-94 & added function 3 ACPI Power Mgmt

· Straps: moved 95-96 to 5A, allow RW after powerup, removed strap XD3
· Expanded CMOS RAM: added ports 72-75 & table 5 CMOS Reg Summary
· Added Power Management Subsystem Overview
· Incorporated App Note #53 APM-Compliant Pwr Mgmt Model of 82C586A
· Added AC Timing Section with IDE Interface Timing Diagrams & Specs

Revision 1.0

5/13/97

· Overview Changes: Added System Block Diagram

· Pin Function Changes:

Pin 90 added alternate function "POS" output (3040F and 3041 silicon)
Pin 106 added alternate function "IRQ8#" input (3040F and 3041 silicon)
Pin 137 added alternate function "SDDIR" output (3041 only silicon)

· Register Definition Changes:

Fixed typos: Port 75 note, Fn0 Rx48[3], Rx55-57[7:0]; Fn1 Rx4[7]; Fn2

Rx3C-3D; Fn3 Rx26[9], Rx2F, Rx62-63, Table 7

Added missing register: Function 0 Rx59[3] MIRQ Pin Config Register
Function 0 PCI-to-ISA Bridge (3041 only silicon)

Rx08[7:0] (changed) Revision Code Register
Rx2C[31:0] (new) Subsystem ID Register (read)
Rx41[0] (changed) ISA Test Mode Register
Rx46[7:5] and Rx48[5:4] (new) Misc Control Registers 1 and 3
Rx5C[0] (new) DMA Control Register
Rx70[31:0] (new) Subsystem ID Register (write)

Function 1 IDE Controller (3041 only silicon)

Rx43[7] (new) FIFO Configuration Register
Rx44[1:0] (new) Misc Control Register 1

Function 3 Power Management (3040F and 3041 silicon)

Rx04[0] (moved to Rx41[7]) Command Register
Rx08[7:0] (changed) Revision ID Register
Rx10[4:1], Rx14 (changed) Processor Control and Processor Level 2
Rx20[31:0] (moved to Rx48) I/O Base Address Register

Power Management I/O(3040F and 3041 silicon)

Rx40[6:5] (new) GPIO Direction Control Register

· Electrical Spec Changes: Added PCI Cycle Timing
· Mechanical Spec Changes: Added marking specs for 3040E/F, 3041 silicon

Incorrect

Change

9,$7HFKQRORJLHV,QF

VT82C586B

Revision 1.0 May 13, 1997

-ii-

Table of Contents

ABLE OF

ONTENTS

REVISION HISTORY........................................................................................................................................................................I

TABLE OF CONTENTS .................................................................................................................................................................. II

LIST OF FIGURES..........................................................................................................................................................................III

LIST OF TABLES ...........................................................................................................................................................................IV

OVERVIEW ....................................................................................................................................................................................... 3

PINOUTS ............................................................................................................................................................................................ 4

REGISTERS ..................................................................................................................................................................................... 14

EGISTER

VERVIEW

................................................................................................................................................................. 14

ONFIGURATION

PACE

I/O ....................................................................................................................................................... 20

EGISTER

ESCRIPTIONS

............................................................................................................................................................ 21

Legacy I/O Ports ................................................................................................................................................................... 21

Keyboard Controller Registers.............................................................................................................................................................. 22
DMA Controller I/O Registers .............................................................................................................................................................. 24
Interrupt Controller Registers ............................................................................................................................................................... 25
Timer / Counter Registers ..................................................................................................................................................................... 25
CMOS / RTC Registers......................................................................................................................................................................... 26

PCI to ISA Bridge Registers (Function 0) .......................................................................................................................... 27

PCI Configuration Space Header .......................................................................................................................................................... 27
ISA Bus Control.................................................................................................................................................................................... 27
Plug and Play Control ........................................................................................................................................................................... 30
Distributed DMA Control ..................................................................................................................................................................... 32
Miscellaneous ....................................................................................................................................................................................... 32

Enhanced IDE Controller Registers (Function 1).............................................................................................................. 33

Universal Serial Bus Controller Registers (Function 2) .................................................................................................... 38

Power Management Registers (Function 3)........................................................................................................................ 40

PCI Configuration Space Header .......................................................................................................................................................... 40
Power Management-Specific PCI Configuration Registers .................................................................................................................. 41
Power Management Subsystem Overview ............................................................................................................................................ 43
Power Management I/O-Space Registers .............................................................................................................................................. 46

ELECTRICAL SPECIFICATIONS ............................................................................................................................................... 55

BSOLUTE

AXIMUM

ATINGS

................................................................................................................................................. 55

DC C

HARACTERISTICS

................................................................................................................................................................ 55

AC T

IMING

PECIFICATIONS

...................................................................................................................................................... 56

PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 63

9,$7HFKQRORJLHV,QF

VT82C586B

Revision 1.0 May 13, 1997

-iii-

List of Figures

IST OF

IGURES

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3
FIGURE 2. PIN DIAGRAM......................................................................................................... .................................................... 4
FIGURE 3. STRAP OPTION CIRCUIT....................................................................................................................................... 31
FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 43
FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 58
FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 58
FIGURE 7. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................... 59
FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND ...... 60
FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND ... 60
FIGURE 10. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND...... 61
FIGURE 11. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 61
FIGURE 12. ULTRADMA-33 IDE TIMING - PIO CYCLE ...................................................................................................... 62
FIGURE 13. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE.................................................. 63

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VT82C586A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VT82C586A