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VT82C596B
Revision 0.3 June 17, 1999
-i-
Revision History
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R
EVISION
H
ISTORY
Document Release
Date
Revision
Initials
Revision 0.1
2/23/99
Initial release based on 82C596A Data Sheet revision 1.1
- Added UltraDMA-66 to feature bullets and overview
- Added integrated APIC (changed H18, K18, J17 pin descriptions)
- Added note to RTC CMOS Register Summary
- Added / changed function 0 Rx42[6], Rx48[7-4], Rx5B[3], Rx5C[7-4, 2],
Rx74[29-24, 8, 1], Rx87-89
- Added / changed function 3 Rx8, Rx4D[2-0], Rx54-55, Rx58-5B, Rx90-91,
RxD2-D6 (80-88 renumbered), PMU I/O Offset 0[11], 20[14, 7-1],
22[14, 7-1], 24[14, 7-1], 28[15-11], 2A[15-11], 2C[11-10], 38[2-1],
44[10-1], 4C[30-0]
DH
Revision 0.2
3/9/99
Updated feature bullets, overview, and pin descriptions
Replaced IDE function 1 with registers from 686B to reflect UltraDMA-66
Added / changed PMU function 3 registers Rx42[7-6, 4], Rx58-5B, PMU I/O
Offset 0[8], 2C[2], 30[10-0], 34[10-0], 38[6, 4-3], 40 (removed)
DH
Revision 0.3
6/17/99
Changed Function 0 Rx42[2-0], 43[5-4], 50 default, 55[3-0], 57[3-0], 58[3-0],
88[5], Function 1 RxD, 42-43, 45[3-2], 54[4-3], 70, 74-75, 78, 7C-7D,
Function 2 Rx41[7-3], Function 3 Rx4C-4F default value
DH
VT82C596B
Revision 0.3 June 17, 1999
-ii-
Table of Contents
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T
ABLE OF
C
ONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS .................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
OVERVIEW ....................................................................................................................................................................................... 3
PINOUTS ............................................................................................................................................................................................ 4
REGISTERS ..................................................................................................................................................................................... 21
R
EGISTER
O
VERVIEW
................................................................................................................................................................. 21
C
ONFIGURATION
S
PACE
I/O ....................................................................................................................................................... 28
R
EGISTER
D
ESCRIPTIONS
............................................................................................................................................................ 29
Legacy I/O Ports ................................................................................................................................................................... 29
Keyboard Controller Registers.............................................................................................................................................................. 30
DMA Controller I/O Registers .............................................................................................................................................................. 32
Interrupt Controller Registers ............................................................................................................................................................... 33
Timer / Counter Registers ..................................................................................................................................................................... 33
CMOS / RTC Registers......................................................................................................................................................................... 34
Function 0 Registers - PCI to ISA Bridge........................................................................................................................... 35
PCI Configuration Space Header .......................................................................................................................................................... 35
ISA Bus Control.................................................................................................................................................................................... 36
Plug and Play Control ........................................................................................................................................................................... 39
Distributed DMA / Serial IRQ Control ................................................................................................................................................. 41
Miscellaneous / General Purpose I/O.................................................................................................................................................... 42
Function 1 Registers - Enhanced IDE Controller .............................................................................................................. 47
PCI Configuration Space Header .......................................................................................................................................................... 47
IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 49
IDE I/O Registers.................................................................................................................................................................................. 54
Function 2 Registers - Universal Serial Bus Controller..................................................................................................... 55
PCI Configuration Space Header .......................................................................................................................................................... 55
USB-Specific Configuration Registers.................................................................................................................................................. 56
USB I/O Registers................................................................................................................................................................................. 57
Function 3 Registers - Power Management and SMBus .................................................................................................. 58
PCI Configuration Space Header .......................................................................................................................................................... 58
Power Management-Specific PCI Configuration Registers .................................................................................................................. 59
System Management Bus-Specific Configuration Registers ................................................................................................................. 65
System Management Bus I/O-Space Registers...................................................................................................................................... 66
Power Management I/O-Space Registers .............................................................................................................................................. 70
FUNCTIONAL DESCRIPTIONS .................................................................................................................................................. 78
P
OWER
M
ANAGEMENT
................................................................................................................................................................ 78
Power Management Subsystem Overview ............................................................................................................................................ 78
Processor Bus States ............................................................................................................................................................................. 78
System Suspend States and Power Plane Control ................................................................................................................................. 79
General Purpose I/O Ports..................................................................................................................................................................... 79
Power Management Events ................................................................................................................................................................... 80
System and Processor Resume Events .................................................................................................................................................. 80
Legacy Power Management Timers ...................................................................................................................................................... 81
System Primary and Secondary Events ................................................................................................................................................. 81
Peripheral Events .................................................................................................................................................................................. 81
ELECTRICAL SPECIFICATIONS ............................................................................................................................................... 82
VT82C596B
Revision 0.3 June 17, 1999
-iii-
Table of Contents
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A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................................. 82
DC C
HARACTERISTICS
................................................................................................................................................................ 82
AC T
IMING
S
PECIFICATIONS
...................................................................................................................................................... 83
PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 90
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