H
FRQQHFW
Z
97&$
$SROOR3UR
0+]
6LQJOH&KLS6ORW6RFNHW1RUWK%ULGJH
IRU'HVNWRSDQG0RELOH3&6\VWHPV
ZLWK$*3[DQG3&,
SOXV$GYDQFHG(&&0HPRU\&RQWUROOHU
VXSSRUWLQJ6'5$09&0('2DQG)3*'5$0
5HYLVLRQ
-XO\
9,$7(&+12/2*,(6,1&
&RS\ULJKW1RWLFH
&RS\ULJKW
9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3ULQWHG LQ WKH 8QLWHG 6WDWHV $
//
5
,*+76
5
(6(59('
1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG LQ D UHWULHYDO V\VWHP RU WUDQVODWHG LQWR
DQ\ ODQJXDJH LQ DQ\ IRUP RU E\ DQ\ PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RU RWKHUZLVH
ZLWKRXW WKH SULRU ZULWWHQ SHUPLVVLRQ RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG
97 97& 97&% 97& 97& 97& 97&% 97& 97&
97& 97& 97&% 97& 97& 97& 97& 97&$ 97&
97&$ 97&; 97 0RELOH 6RXWK 6XSHU 6RXWK $SROOR 93 $SROOR 93; $SROOR 93 $SROOR 93 $SROOR
093 $SROOR 093 $SROOR 3 $SROOR 3UR $SROOR 3UR $SROOR 3UR$ DQG $SROOR 3UR0HGLD PD\ RQO\ EH XVHG WR
LGHQWLI\ SURGXFWV RI 9,$ 7HFKQRORJLHV
36
%
LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS
3HQWLXP
%
&HOHURQ
%
00;
%
DQG ,QWHO
%
DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS
&\UL[
;
%
LV D UHJLVWHUHG WUDGHPDUN RI &\UL[ &RUS
$0'
.
%
$0'
.
%
$0'.
%
DQG $0'.
%
DUH UHJLVWHUHG WUDGHPDUNV RI $GYDQFHG 0LFUR 'HYLFHV &RUS
:LQGRZV
%
DQG 3OXJ DQG 3OD\
%
DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS
3&,
%
LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS
9(6$ LV D WUDGHPDUN RI WKH 9LGHR (OHFWURQLFV 6WDQGDUGV $VVRFLDWLRQ
$OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV
'LVFODLPHU1RWLFH
1R OLFHQVH LV JUDQWHG LPSOLHG RU RWKHUZLVH XQGHU DQ\ SDWHQW RU SDWHQW ULJKWV RI 9,$ 7HFKQRORJLHV 9,$ 7HFKQRORJLHV
PDNHV QR ZDUUDQWLHV LPSOLHG RU RWKHUZLVH LQ UHJDUG WR WKLV GRFXPHQW DQG WR WKH SURGXFWV GHVFULEHG LQ WKLV GRFXPHQW
7KH LQIRUPDWLRQ SURYLGHG E\ WKLV GRFXPHQW LV EHOLHYHG WR EH DFFXUDWH DQG UHOLDEOH WR WKH SXEOLFDWLRQ GDWH RI WKLV
GRFXPHQW +RZHYHU 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV LQ WKLV GRFXPHQW )XUWKHUPRUH 9,$
7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU WKH XVH RU PLVXVH RI WKH LQIRUPDWLRQ LQ WKLV GRFXPHQW DQG IRU DQ\ SDWHQW
LQIULQJHPHQWV WKDW PD\ DULVH IURP WKH XVH RI WKLV GRFXPHQW 7KH LQIRUPDWLRQ DQG SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV
GRFXPHQW DUH VXEMHFW WR FKDQJH DW DQ\ WLPH ZLWKRXW QRWLFH DQG ZLWKRXW REOLJDWLRQ WR QRWLI\ DQ\ SHUVRQ RI VXFK FKDQJH
2IILFHV
86$ 2IILFH
7DLSHL 2IILFH
0LVVLRQ &RXUW
WK
)ORRU 1R
)UHPRQW &$
&KXQJ&KHQJ 5RDG +VLQ7LHQ
86$
7DLSHL 7DLZDQ 52&
7HO
7HO
)D[
)D[
2QOLQH6HUYLFHV
+RPH 3DJH
http://www.via.com.tw
7DLZDQ RU
http://www.viatech.com
86$
)73 6HUYHU
ftp.via.com.tw
7DLZDQ
%%6
VT82C693A
Revision 1.0, July 22, 1999
-i-
Revision History
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
R
EVISION
H
ISTORY
Document Release
Date
Revision
Initials
0.1
12/9/98
Initial internal release as VT82C694
EC
0.2
12/31/98
Changed part number to VT82C693A
Fixed definition of strapping option on MAB8#
Fixed pin numbers of RESET#, PREQ#, and REQ0#
Updated register definitions: Device 0 Rx68[1-0], Rx69[5], Rx50[3-1],
Rx53[5], Rx69[6-5,1], Rx7A[4-1], RxF8-F9, RxAD, Device 1 Rx2 (Device
ID=8691), Rx4[5], Rx41[0], Rx42[0]
DH
0.21
1/6/99
Fixed minor typo in AGP feature bullets
DH
0.22
1/13/99
Fixed placement diagram in pin descriptions
DH
0.3
4/1/99
Fixed typo in pinout section footer
Changed pin AC4 from SUSCLK to PCKRUN#
Added DCLKRD function to pin AB22 (MAA14)
Updated function 0 registers Rx50[5,3-1], 51[5,2-1], 53[5-3, 67-64[2], 69[7-
5,1], 6B[5,3-1], 6C[4], 73[4], 76[7], 7A[3], AD[4], F9, FC
DH
0.4
5/26/99
Updated & fixed typos in feature bullets and intro
Modified device 0 Rx6[6], 8 default, 68[1-0], 69[7-6], 70[3], 72[7], 76[5-4],
A7 readback value, FC[1-0], FD[2-0]
Modified device 1 Rx2-3 and added 1B and F0-F7
DH
0.5
7/13/99
Added SDRAM AC Timing
Fixed AGPREF pin description
DH
0.51
7/15/99
Fixed CPURST# and CPURSTD# pin descriptions and pin directions
Added Host CPU Interface AC Timing
DH
1.0
7/22/99
Product announced so "NDA Req'd" watermark removed (content unchanged)
DH
VT82C693A
Revision 1.0, July 22, 1999
-ii-
Table of Contents
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
T
ABLE OF
C
ONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS .................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................III
LIST OF TABLES ...........................................................................................................................................................................IV
APOLLO PRO133 ............................................................................................................................................................................. 1
OVERVIEW ....................................................................................................................................................................................... 4
PINOUTS ............................................................................................................................................................................................ 6
PIN DESCRIPTIONS ........................................................................................................................................................................ 9
REGISTERS ..................................................................................................................................................................................... 17
R
EGISTER
O
VERVIEW
................................................................................................................................................................. 17
M
ISCELLANEOUS
I/O................................................................................................................................................................... 20
C
ONFIGURATION
S
PACE
I/O ....................................................................................................................................................... 20
R
EGISTER
D
ESCRIPTIONS
............................................................................................................................................................ 21
Device 0 Header Registers - Host Bridge ............................................................................................................................ 21
Device 0 Configuration Registers - Host Bridge ................................................................................................................ 23
Host CPU Control ................................................................................................................................................................................. 23
DRAM Control ..................................................................................................................................................................................... 25
PCI Bus Control.................................................................................................................................................................................... 32
GART / Graphics Aperture Control ...................................................................................................................................................... 36
AGP Control ......................................................................................................................................................................................... 38
Device 1 Header Registers - PCI-to-PCI Bridge ................................................................................................................ 40
Device 1 Configuration Registers - PCI-to-PCI Bridge..................................................................................................... 42
AGP Bus Control .................................................................................................................................................................................. 42
ELECTRICAL SPECIFICATIONS ............................................................................................................................................... 44
A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................................. 44
DC C
HARACTERISTICS
................................................................................................................................................................ 44
AC T
IMING
S
PECIFICATIONS
...................................................................................................................................................... 44
MECHANICAL SPECIFICATIONS ............................................................................................................................................. 46
VT82C693A
Revision 1.0, July 22, 1999
-iii-
List of Figures
7HFKQRORJLHV ,QF
:H &
:H &RRQQQQHFW
HFW
L
IST OF
F
IGURES
FIGURE 1. APOLLO PRO133 SYSTEM BLOCK DIAGRAM USING THE VT82C596B MOBILE SOUTH BRIDGE ..... 4
FIGURE 2. VT82C693A BALL DIAGRAM (TOP VIEW)........................................................................................................... 6
FIGURE 3. VT82C693A PIN LIST (NUMERICAL ORDER) ..................................................................................................... 7
FIGURE 4. VT82C693A PIN LIST (ALPHABETICAL ORDER)............................................................................................... 8
FIGURE 5. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 36
FIGURE 6. MECHANICAL SPECIFICATIONS - 492-PIN BALL GRID ARRAY PACKAGE ........................................... 46
PDF 
ZIP