SPICE Device Model SUP80N15-20L
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72425
www.vishay.com
12-Jun-04
1
N-Channel 150-V (D-S) 175C MOSFET
CHARACTERISTICS
N- and P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the -55 to 125C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the
-55 to 125C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched C
gd
model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model SUP80N15-20L
Vishay Siliconix
www.vishay.com
Document Number: 72425
2
12-Jun-04
SPECIFICATIONS (T
J
= 25
C UNLESS OTHERWISE NOTED)
Parameter Symbol
Test
Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
A
1.7 V
On-State Drain Current
a
I
D(on)
V
DS
= 5 V, V
GS
= 10 V
314
A
V
GS
= 10 V, I
D
= 30 A
0.016
0.016
V
GS
= 10 V, I
D
= 30 A, T
J
= 125C
0.023
V
GS
= 10 V, I
D
= 30 A, T
J
= 175C
0.026
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 4.5 V, I
D
= 20 A
0.017
Forward Transconductance
a
g
fs
V
DS
= 15 V, I
D
= 30 A
93
S
Forward Voltage
a
V
SD
I
S
= 80 A, V
GS
= 0 V
0.92
1
V
Dynamic
b
Input Capacitance
C
iss
6590
6500
Output Capacitance
C
oss
510
520
Reverse Transfer Capacitance
C
rss
V
GS
= 0 V, V
DS
= 25 V, f = 1 MHz
320 270
Pf
Total Gate Charge
c
Q
g
114
110
Gate-Source Charge
c
Q
gs
21
21
Gate-Drain Charge
c
Q
gd
V
DS
= 50 V, V
GS
= 10 V, I
D
= 80 A
33 33
NC
Turn-On Delay Time
c
t
d(on)
176
20
Rise Time
c
t
r
43
100
Turn-Off Delay Time
c
t
d(off)
43
70
Fall Time
c
t
f
V
DD
= 50 V, R
L
= 0.93
I
D
80 A, V
GEN
= 10 V, R
G
= 2.5
49 135
Ns
Notes
a.
Pulse test; pulse width
300 s, duty cycle 2%.
b.
Guaranteed by design, not subject to production testing.
c.
Independent of operating temperature.
SPICE Device Model SUP80N15-20L
Vishay Siliconix
Document Number: 72425
www.vishay.com
12-Jun-04
3
COMPARISON OF MODEL WITH MEASURED DATA (T
J
=25
C UNLESS OTHERWISE NOTED)
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